ST STM32F101 Series, STM32F103 Series Reference Manual

RM0008

Reference manual

STM32F101xx and STM32F103xx

advanced ARM-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on
how to use the STM32F101xx and STM32F103xx microcontroller memory and peripherals.
The STM32F101xx and STM32F103xx will be referred to as STM32F10xxx throughout the
document.

The STM32F10xxx is a family of microcontro llers with diff erent memory sizes, pac kages and
peripherals.

For ordering info rmation, mechanical and electrical device char acteristics please ref er to the
STM32F101xx and STM32F103xx datasheets.

For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Fla sh programming manual.

For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical
Reference Manual.

Related documents

Available from www.arm.com:

■

Cortex™-M3 Technical Reference Manual

Available from www.st.com:

■

STM32F101xx STM32F103xx datasheets

■

STM32F10xxx Flash programming manual

November 2007 Rev 2 1/501

www.st.com

Contents RM0008

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.3.1 Peripheral memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3.3 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . 33

3.1.2 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2.1 Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 35

3.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.3.6 Auto Wakeup (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . 41

3.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 45

3.5 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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4 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.1.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.1.3 Backup domain Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.3 RCC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 56

4.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.3.4 APB2 Peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . . 62

4.3.5 APB1 Peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . . 64

4.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . . 66

4.3.7 APB2 Peripheral Clock enable register (RCC_APB2ENR) . . . . . . . . . . 67

4.3.8 APB1 Peripheral Clock enable register (RCC_APB1ENR) . . . . . . . . . . 69

4.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . 71

4.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.4 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5 General-purpose and alternate-function I/Os (GPIOs and AFIOs) . . . 75

5.1 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.1.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.1.2 Atomic bit set or bit reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.1.3 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . . 79

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5.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.1.10 Analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.2 GPIO register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.2.1 Port configuration register low (GPIOx_CRL) (x=A..E) . . . . . . . . . . . . . 83

5.2.2 Port configuration register high (GPIOx_CRH) (x=A..E) . . . . . . . . . . . . 84

5.2.3 Port input data register (GPIOx_IDR) (x=A..E) . . . . . . . . . . . . . . . . . . . 85

5.2.4 Port output data register (GPIOx_ODR) (x=A..E) . . . . . . . . . . . . . . . . . 85

5.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..E) . . . . . . . . . . . . . . . . 86

5.2.6 Port bit reset register (GPIOx_BRR) (x=A..E) . . . . . . . . . . . . . . . . . . . . 86

5.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..E) . . . . . . . . . . . 87

5.3 Alternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . . 88

5.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . . 88

5.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . . . . . . . . 88

5.3.3 BXCAN alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.3.4 JTAG/SWD alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . 88

5.3.5 Timer alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.3.6 USART Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.3.7 I2C 1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.3.8 SPI 1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.4 AFIO register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.4.1 Event control register (AFIO_EVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) . . . . . . . 93

5.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) . . . . . . . . . 95

5.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) . . . . . . . . . 95

5.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) . . . . . . . . . 96

5.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) . . . . . . . . . 96

5.5 GPIO and AFIO register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.5.1 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.5.2 AFIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 98

6.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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6.2 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 101

6.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.3 EXTI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.3.1 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.3.4 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.3.5 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.4 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 113

7.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 114

7.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1 ..7) . . . . . . 115

7.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1 ..7) . 116

7.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7) 117

7.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1 ..7) . 117

7.5 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

8 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

8.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

8.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

8.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

8.3.2 Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

8.3.3 Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

8.3.4 Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8.3.5 RTC flag assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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8.4 RTC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

8.4.1 RTC control register High (RTC_CRH) . . . . . . . . . . . . . . . . . . . . . . . . 124

8.4.2 RTC control register low (RTC_CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 125

8.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) . . . . . . . . . . . 127

8.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . . . . . . . 128

8.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) . . . . . . . . . . . . . . . . 129

8.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . . . . . . . . . . . 130

8.5 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

9 Backup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.3 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.4 RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.5 BKP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.5.1 Backup data register x (BKP_DRx) (x = 1 ..10) . . . . . . . . . . . . . . . . . . 133

9.5.2 RTC clock calibration register (BKP_RTCCR) . . . . . . . . . . . . . . . . . . . 133

9.5.3 Backup control register (BKP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

9.5.4 Backup control/status register (BKP_CSR) . . . . . . . . . . . . . . . . . . . . . 135

9.6 BKP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

10 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

10.1.1 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

10.1.2 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

10.1.3 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

10.2 IWDG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

10.2.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

10.2.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

10.2.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

10.2.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.3 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

11 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

11.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

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11.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

11.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 144

11.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

11.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

11.6.1 Control Register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

11.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 146

11.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

11.7 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

12 Advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

12.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

12.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

12.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

12.4.1 Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

12.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

12.4.3 Repetition downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

12.4.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

12.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

12.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

12.4.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

12.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

12.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

12.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

12.4.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 172

12.4.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

12.4.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 176

12.4.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

12.4.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

12.4.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

12.4.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

12.4.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

12.4.19 TIM1 and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 184

12.4.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.4.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.5 TIM1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

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12.5.1 Control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

12.5.2 Control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.5.3 Slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . . . . . . 192

12.5.4 DMA/Interrupt enable register (TIM1_DIER) . . . . . . . . . . . . . . . . . . . . 195

12.5.5 Status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

12.5.6 Event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 198

12.5.7 Capture/compare mode register 1 (TIM1_CCMR1) . . . . . . . . . . . . . . . 199

12.5.8 Capture/compare mode register 2 (TIM1_CCMR2) . . . . . . . . . . . . . . . 202

12.5.9 Capture/compare enable register (TIM1_CCER) . . . . . . . . . . . . . . . . . 203

12.5.10 Counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

12.5.11 Prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

12.5.12 Auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

12.5.13 Repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . . . . . 207

12.5.14 Capture/compare register 1 (TIM1_CCR1) . . . . . . . . . . . . . . . . . . . . . 207

12.5.15 Capture/compare register 2 (TIM1_CCR2) . . . . . . . . . . . . . . . . . . . . . 208

12.5.16 Capture/compare register 3 (TIM1_CCR3) . . . . . . . . . . . . . . . . . . . . . 208

12.5.17 Capture/compare register 4 (TIM1_CCR4) . . . . . . . . . . . . . . . . . . . . . 209

12.5.18 Break and dead-time register (TIM1_BDTR) . . . . . . . . . . . . . . . . . . . . 209

12.5.19 DMA control register (TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

12.5.20 DMA address for burst mode (TIM1_DMAR) . . . . . . . . . . . . . . . . . . . . 212

12.6 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

13 General purpose timer (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

13.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.4.1 Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

13.4.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

13.4.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

13.4.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

13.4.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

13.4.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

13.4.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

13.4.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

13.4.10 One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

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13.4.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 238

13.4.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

13.4.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

13.4.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 242

13.4.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

13.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

13.5 TIMx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

13.5.1 Control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

13.5.2 Control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

13.5.3 Slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . . . . . 254

13.5.4 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . . . . 257

13.5.5 Status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

13.5.6 Event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 260

13.5.7 Capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . . . . . 261

13.5.8 Capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . . . . . 264

13.5.9 Capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . . . . . 266

13.5.10 Counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

13.5.11 Prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

13.5.12 Auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

13.5.13 Capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . . . . . 268

13.5.14 Capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . . . . . 268

13.5.15 Capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . . . . . 269

13.5.16 Capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . . . . . 269

13.5.17 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

13.5.18 DMA address for burst mode (TIMx_DMAR) . . . . . . . . . . . . . . . . . . . . 270

13.6 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

14 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

14.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

14.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

14.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 274

14.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

14.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

14.3.5 Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

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14.4 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

14.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

14.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

14.4.3 Sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

14.4.4 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

14.4.5 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

14.4.6 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

14.4.7 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 278

14.5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

14.5.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

14.5.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 280

14.5.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

14.5.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

14.5.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

14.5.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

14.5.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

14.7 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

14.8 CAN register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

14.8.1 Control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

14.8.2 Mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

14.8.3 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

14.9 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

15 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 316

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

15.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

15.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

15.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

15.4.1 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

15.4.2 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

15.4.3 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

15.4.4 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

15.4.5 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

15.4.6 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

15.4.7 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

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15.5 Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

15.6 I

15.7 I

2

C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

2

C register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

15.7.1 Control register 1(I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

15.7.2 Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

15.7.3 Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 338

15.7.4 Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 338

15.7.5 Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

15.7.6 Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

15.7.7 Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

15.7.8 Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

15.7.9 TRISE Register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

15.8 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

16 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

16.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

16.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

16.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

16.4.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

16.4.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

16.4.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

16.4.4 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

16.4.5 Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

16.4.6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

16.4.7 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

16.4.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

16.4.9 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

16.4.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

16.5 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

16.6 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

16.7 Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 356

16.8 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

16.9 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

16.10 Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

16.10.1 Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

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16.10.2 Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

16.10.3 Fast interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

16.10.4 Slow interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

16.10.5 Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

16.10.6 Independent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

16.10.7 Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 363

16.10.8 Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 363

16.10.9 Combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . . 364

16.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

16.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

16.13 ADC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

16.13.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

16.13.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

16.13.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

16.13.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 373

16.13.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 374

16.13.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . 375

16.13.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 375

16.13.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 376

16.13.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 376

16.13.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 377

16.13.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 377

16.13.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 378

16.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 379

16.13.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 379

16.14 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

17 USB full speed device interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . 382

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

17.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

17.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

17.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

17.4.1 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

17.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

17.5.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

17.5.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

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17.5.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

17.5.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

17.5.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

17.6 USB register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

17.6.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

17.6.2 Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

17.6.3 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

17.7 USB Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

18.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

18.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

18.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

18.3.2 SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

18.3.3 SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

18.3.4 Simplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

18.3.5 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

18.3.6 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

18.3.7 SPI communication using DMA (direct memory addressing) . . . . . . . 421

18.3.8 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

18.3.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

18.4 SPI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

18.4.1 SPI Control Register 1 (SPI_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

18.4.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

18.4.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

18.4.4 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

18.4.5 SPI CRC polynomial register (SPI_CRCPR) . . . . . . . . . . . . . . . . . . . . 427

18.4.6 SPI Rx CRC register (SPI_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . . 428

18.4.7 SPI Tx CRC register (SPI_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . . 428

18.5 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

19 Universal synchronous asynchronous receiver

transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

19.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

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19.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

19.3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

19.3.2 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

19.3.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

19.3.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

19.3.5 Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

19.3.6 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

19.3.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

19.3.8 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 444

19.3.9 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

19.3.10 Single wire half duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 448

19.3.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

19.3.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

19.3.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 452

19.3.14 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

19.4 Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

19.5 USART register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

19.5.1 Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

19.5.2 Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

19.5.3 Baud Rate Register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . 459

19.5.4 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

19.5.5 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

19.5.6 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

19.5.7 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 466

19.6 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

20 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

20.2 Referenced ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

20.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . 469

20.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . . 470

20.4 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

20.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

20.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

20.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . 472

20.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . . 473

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20.5 STM32F10xxx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . 473

20.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

20.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

20.6.2 TMC TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

20.6.3 Cortex-M3 T AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

20.6.4 Cortex-M3 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

20.7 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

20.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

20.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

20.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

20.8.3 SW-DP state machine (Reset, idle states, ID code) . . . . . . . . . . . . . . 478

20.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

20.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

20.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

20.9 AHB-AP (AHB Access Port) - valid for both JTAG-DP or SW-DP . . . . . 480

20.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

20.11 Capability of the debugger host to connect under system reset . . . . . . 482

20.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

20.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

20.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . 483

20.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

20.14.2 Timestamp packets, synchronization and overflow packets . . . . . . . . 483

20.15 MCU debug component (MCUDBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

20.15.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 485

20.15.2 Debug support for timers, watchdog, bxCAN and I

20.15.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

2

C . . . . . . . . . . . . . 485

20.16 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

20.16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

20.16.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

20.16.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

20.16.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . . 491

20.16.5 Emission of synchronization frame packet . . . . . . . . . . . . . . . . . . . . . . 491

20.16.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

20.16.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

20.16.8 TRACECLKIN connection inside STM32F10xxx . . . . . . . . . . . . . . . . . 492

20.16.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

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20.16.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

20.17 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Appendix A Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

A.1 PD0 and PD1 use in output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

A.2 ADC auto-injection channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

A.3 ADC combined injected simultaneous + interleaved. . . . . . . . . . . . . . . . 495

A.4 Voltage glitch on ADC input 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

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List of tables

Table 1. Register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 2. Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 3. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 4. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 5. Sleep-now. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6. Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 7. Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 8. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 9. PWR - register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 10. RCC - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 11. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 12. Output MODE bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 13. BXCAN alternate function remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 14. Debug interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 15. Debug port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 16. Timer 4 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 17. Timer 3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 18. Timer 2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 19. Timer 1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 20. USART3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 21. USART2 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 22. USART1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 23. I2C1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 24. SPI1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 25. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 26. AFIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 27. Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 28. External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 107

Table 29. Summary of DMA requests for each channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 30. DMA - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 31. RTC - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 32. BKP - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 33. Watchdog timeout period (with 40 kHz input clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 34. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 35. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 36. Counting direction versus encoder signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 37. Output control bits for complementary OCx and OCxN channels with break feature. . . . 205

Table 38. TIM1 - Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 39. Counting direction versus encoder signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 40. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Table 41. TIMx - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 42. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 43. Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table 44. bxCAN - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Table 45. SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Table 46. I2C Interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Table 47. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

Table 48. ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

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Table 49. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Table 50. External trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

Table 51. External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

Table 52. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Table 53. ADC - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

Table 54. Double-buffering buffer flag definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Table 55. Bulk double-buffering memory buffers usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Table 56. Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

Table 57. Resume event detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Table 58. Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Table 59. Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Table 60. Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Table 61. Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Table 62. Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

Table 63. USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

Table 64. SPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

Table 65. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

Table 66. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

Table 67. Error calculation for programmed baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

Table 68. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Table 69. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Table 70. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

Table 71. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

Table 72. Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Table 73. JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Table 74. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 476

Table 75. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Table 76. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Table 77. DATA transfer (33 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Table 78. SW-DP registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Table 79. Cortex-M3 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

Table 80. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

Table 81. Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

Table 82. Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Table 83. Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489

Table 84. Flexible TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

Table 85. Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3

Table 86. DBG - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Table 87. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

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RM0008 List of figures

List of figures

Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 2. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 3. Power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 4. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 6. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 7. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 8. HSE/ LSE clock sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 9. Basic structure of a standard I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 10. Basic structure of a five-volt tolerant I/O port bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 11. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 12. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 13. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 14. High impedance-analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 15. External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 16. External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 17. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 18. DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 19. RTC simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 20. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . 123

Figure 21. RTC Overflow waveform example with PR=0003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 22. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 23. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 24. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 25. Advanced control timer (TIM1) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 26. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 151

Figure 27. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 151

Figure 28. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 29. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 30. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 31. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 32. Counter timing diagram, update event when ARPE=0 (TIM1_ARR not preloaded). . . . . 153

Figure 33. Counter timing diagram, update event when ARPE=1 (TIM1_ARR preloaded). . . . . . . . 154

Figure 34. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 35. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 36. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 37. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 38. Counter timing diagram, update event when repetition counter is not used. . . . . . . . . . . 156

Figure 39. Counter timing diagram, internal clock divided by 1, TIM1_ARR=0x6 . . . . . . . . . . . . . . . 157

Figure 40. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 41. Counter timing diagram, internal clock divided by 4, TIM1_ARR=0x36 . . . . . . . . . . . . . . 158

Figure 42. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 43. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 158

Figure 44. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 159

Figure 45. Update rate examples depending on mode and TIM1_RCR register settings . . . . . . . . . 160

Figure 46. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 47. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 48. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

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Figure 49. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 50. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 51. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 164

Figure 52. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 53. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 54. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 55. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7

Figure 56. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 57. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 58. Center-aligned PWM waveforms (ARR=8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 59. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 60. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 172

Figure 61. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 173

Figure 62. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 63. Clearing TIM1 OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 64. 6-step generation, COM example (OSSR=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 65. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 66. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 67. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 181

Figure 68. Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 69. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 70. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 71. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 72. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 73. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 74. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 216

Figure 75. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 217

Figure 76. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 77. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 78. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 79. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 80. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloade d). . . . . 219

Figure 81. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 220

Figure 82. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 83. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 84. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 85. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 86. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 222

Figure 87. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 223

Figure 88. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 89. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 224

Figure 90. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 91. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 224

Figure 92. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 225

Figure 93. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 94. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 95. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 96. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 97. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 98. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 228

Figure 99. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 100. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 229

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RM0008 List of figures

Figure 101. PWM input mode timing.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 102. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 103. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 104. Center-aligned PWM waveforms (ARR=8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 105. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 106. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 107. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 108. Example of encoder interface mode with IC1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 240

Figure 109. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 110. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 111. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 112. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 113. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 114. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 115. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 116. Triggering timer 2 with Update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 117. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 118. Triggering timer 1 and 2 with timer 1 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 119. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Figure 120. CAN block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 121. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 122. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Figure 123. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Figure 124. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 125. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 126. Receive FIFO states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 127. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Figure 128. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Figure 129. Filtering mechanism - example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Figure 130. CAN error state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 131. Bit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Figure 132. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Figure 133. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 134. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 135. I2C block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Figure 136. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 137. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Figure 138. Transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Figure 139. Transfer sequence diagram for master receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure 140. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Figure 141. Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

Figure 142. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Figure 143. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Figure 144. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

Figure 145. Calibration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

Figure 146. Right alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Figure 147. Left alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Figure 148. Dual ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

Figure 149. Injected simultaneous mode on 4 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Figure 150. Regular simultaneous mode on 16 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

Figure 151. Fast interleaved mode on 1 channel in continuous conversion mode . . . . . . . . . . . . . . . 361

Figure 152. Slow interleaved mode on 1 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

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List of figures RM0008

Figure 153. Alternate trigger: injected channel group of each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Figure 154. Alternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . . . . . . . . 363

Figure 155. Alternate + Regular simultaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Figure 156. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Figure 157. Interleaved single channel with injected sequence CH11, CH12 . . . . . . . . . . . . . . . . . . . 364

Figure 158. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 365

Figure 159. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

Figure 160. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 388

Figure 161. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

Figure 162. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Figure 163. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Figure 164. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Figure 165. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3

Figure 166. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Figure 167. Configurable stop bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Figure 168. Data sampling for noise detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

Figure 169. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

Figure 170. Mute mode using Address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Figure 171. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . . . . . . . . . . . . . . 445

Figure 172. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 446

Figure 173. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Figure 174. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Figure 175. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

Figure 176. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

Figure 177. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

Figure 178. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

Figure 179. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

Figure 180. IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

Figure 181. Hardware flow control between 2 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

Figure 182. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

Figure 183. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

Figure 184. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

Figure 185. Block diagram of STM32F10xxx-level and Cortex-M3-level debug support. . . . . . . . . . . 468

Figure 186. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

Figure 187. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

Figure 188. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

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RM0008 Documentation conventions

1 Documentation conventions

1.1 List of abbreviations for registers

The following abbreviations are used in register descriptions:

read/write (rw) Software can read and write to these bits.
read-only (r) Software can only read these bits.
write-only (w) Software can only write to this bit. Reading the bit returns the reset

value.
read-clear (rc) The software can only read or clear this bit.
read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has

no effect on the bit value.
read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has

no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the

bit value.
toggle (t) The software can only toggle this bit by writing ‘1’. Writing ‘0’ has no

effect.

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Memory and bus architecture RM0008

2 Memory and bus architecture

2.1 System architecture

The main system consists of:

● Four masters:

– Cortex™-M3 core ICode bus (I-bus), DCode bus (D-bus), and System bus (S-bus)
– GP-DMA (General Purpose DMA)

● Three slaves:

– Internal SRAM
– Internal Flash memory
– AHB to APB bridges (AHB2APBx) which connect all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:

Figure 1. System architecture

Cortex-M3

DCode

System

ICode

FLITF

Flash

memory

SRAM

DMA

Ch.1
Ch.2

Ch.7

AHB system bus

DMA request

Bridge 1
Bridge 2

GPIOA
GPIOB
GPIOC
GPIOD
GPIOE

EXTI

APB2 APB1

USART1
SPI1
ADC1

ADC2

TIM1
AFIO

USART2
USART3
SPI2
I2C1
I2C2
USB

IWDG

WWDG
CAN
BKP
PWR
TIM2
TIM3
TIM4

ICode bus

This bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory
instruction interface. Prefetching is perfo rmed on this bus.

DCode bus

This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core
to the Flash memory Data interface.

System bus

This bus connects the system b us of the Cortex™-M3 co re (peripherals bus) to a BusMatrix
which manages the arbitration between the core and the DMA.

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RM0008 Memory and bus architecture

DMA bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.

BusMatrix

The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of
three masters (CPU DCode, System bus and DMA bus) and three slav es (FLITF, SRAM,
and AHB2APB bridges).

AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB/APB bridges (APB)

The two AHB/APB bridges provide full synchronous connections between the AHB and the
2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz
depending on device).

Refer to Table 1 on page 27 for the address mapping of the peripherals connected to each
bridge.

2.2 Memory organization

Program memory, data memory, register s and I/O ports are organized within the same linear
4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The low est numbered b yte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.

Figure 2 on page 26 shows the STM32F10xxx Memory Map. For the detailed mapping of

peripheral registers, please refer to the related chapters.
The addressable memory space is divided into 8 main blocks, each of 512MB.
All the memory areas that are not allocated to on-chip memories and peripherals are

considered “Reserved” (gray shaded areas in the Figure 2 on page 26).

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Memory and bus architecture RM0008

b

2.3 Memory map

Figure 2. Memory map

APB memory space

Addressable memory space

4 Gbytes

0xFFFF FFFF

0xFFFF F000

7

0xE010 0000

0xE000 0000

Cortex-M3 internal

peripherals

6

0xC000 0000

5

0xA000 0000

4

0x8000 0000

3

0x6000 0000

2

0x4000 0000

Peripherals

1

0x2000 0000

SRAM

0

0x0000 0000

Code

Reserved

0x1FFF FFFF

0x1FFF F80F

0x1FFF F800

0x1FFF F000

0x0801 FFFF

0x0800 0000

reserved

Option Bytes

System memory

reserved

Flash memory

0xFFFF FFFF

0xE010 0000

0x6000 0000

0x4002 3400

0x4002 2400

0x4002 2000

0x4002 1400

0x4002 1000

0x4002 0400

0x4002 0000

0x4001 3C00

0x4001 3800

0x4001 3400

0x4001 3000

0x4001 2C00

0x4001 2800

0x4001 2400

0x4001 1C00

0x4001 1800

0x4001 1400

0x4001 1000

0x4001 0C00

0x4001 0800

0x4001 0400

0x4001 0000

0x4000 7400

0x4000 7000

0x4000 6C00

0x4000 6800

0x4000 6400

0x4000 6000

0x4000 5C00

0x4000 5800

0x4000 5400

0x4000 4C00

0x4000 4800

0x4000 4400

0x4000 3C00

0x4000 3800

0x4000 3400

0x4000 3000

0x4000 2C00

0x4000 2800

0x4000 0C00

0x4000 0800

0x4000 0400

0x4000 0000

reserved
reserved

reserved
reserved

Flash memory Interface

reserved

RCC

reserved

DMA

reserved

USART1
reserved

SPI1
TIM1

ADC2
ADC1

reserved

Port E
Port D
Port C

Port B
Port A

EXTI
AFIO

reserved

PWR

BKP

reserved

bxCAN

shared USB/CAN SRAM

512 bytes

USB Registers

I2C2
I2C1

reserved

USART3
USART2

reserved

SPI2

reserved

IWDG

WWDG

RTC

reserved

TIM4

TIM3
TIM2

4 Kb
4 Kb

1 Kb
3 Kb
1 Kb
3 Kb
1 Kb

1 Kb

1 Kb
1 Kb

1 Kb
1 Kb
1 Kb
1 Kb

2 Kb

1 Kb
1 Kb
1 Kb
1 Kb

1 Kb
1 Kb

1 Kb

35 K

1 Kb
1 Kb
1 Kb
1 Kb
1 Kb
1 Kb
1 Kb

1 Kb

2 Kb

1 Kb
1 Kb

2 Kb

1 Kb
1 Kb
1 Kb
1 Kb
1 Kb

7 Kb

1 Kb
1 Kb
1 Kb

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RM0008 Memory and bus architecture

2.3.1 Peripheral memory map

Table 1. Register boundary addresses

Boundary address Peripheral Bus Register map

0x4002 2400 - 0x4002 3FFF Reserved
0x4002 2000 - 0x4002 23FF Flash memory interface
0x4002 1400 - 0x4002 1FFF Reserved
0x4002 1000 - 0x4002 13FF Reset and Clock control RCC Section 4.4 on page 74
0x4002 0400 - 0x4002 0FFF Reserved
0x4002 0000 - 0x4002 03FF DMA Section 7.5 on page 117
0x4001 3C00 - 0x4001 3FFF Reserved
0x4001 3800 - 0x4001 3BFF USART1 Section 19.6 on page 467
0x4001 3400 - 0x4001 37FF Reserved
0x4001 3000 - 0x4001 33FF SPI 1 Section 18.5 on page 429
0x4001 2C00 - 0x4001 2FFF TIM1 timer Section 12.6 on page 212
0x4001 2800 - 0x4001 2BFF ADC2 Section 16.14 on page 380
0x4001 2400 - 0x4001 27FF ADC1 Section 16.14 on page 380
0x4001 2000 - 0x4001 1FFF Reserved

AHB

APB2
0x4001 1800 - 0x4001 1BFF GPIO Port E Section 5.5.1 on page 97
0x4001 1400 - 0x4001 17FF GPIO Port D Section 5.5.1 on page 97
0x4001 1000 - 0x4001 13FF GPIO Port C Section 5.5.1 on page 97
0X4001 0C00 - 0x4001 0FFF GPIO Port B Section 5.5.1 on page 97
0x4001 0800 - 0x4001 0BFF GPIO Port A Section 5.5.1 on page 97
0x4001 0400 - 0x4001 07FF EXTI Section 6.2 on page 101
0x4001 0000 - 0x4001 03FF AFIO Section 5.5 on page 97

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Memory and bus architecture RM0008

Table 1. Register boundary addresses (continued)

Boundary address Peripheral Bus Register map

0x4000 8000 - 0x4000 77FF Reserved
0x4000 7000 - 0x4000 73FF Power control PWR Section 3.5 on page 46
0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) Section 9.6 on page 136
0x4000 6800 - 0x4000 6BFF Reserved
0x4000 6400 - 0x4000 67FF bxCAN Section 14.9 on page 313

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF USB Registers Section 17.7 on page 412
0x4000 5800 - 0x4000 5BFF I2C2 Section 15.8 on page 346
0x4000 5400 - 0x4000 57FF I2C1 Section 15.8 on page 346
0x4000 5000 - 0x4000 4FFF Reserved
0x4000 4800 - 0x4000 4BFF USART3 Section 19.6 on page 467
0x4000 4400 - 0x4000 47FF USART2 Section 19.6 on page 467
0x4000 4000 - 0x4000 3FFF Reserved
0x4000 3800 - 0x4000 3BFF SPI2 Section 18.5 on page 429

shared USB/CAN SRAM 512
bytes

APB1

0x4000 3400 - 0x4000 37FF Reserved
0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG) Section 10.3 on page 142
0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG)
0x4000 2800 - 0x4000 2BFF RTC Section 8.5 on page 131
0x4000 2400 - 0x4000 0FFF Reserved
0x4000 0800 - 0x4000 0BFF TIM4 timer Section 13.6 on page 271
0x4000 0400 - 0x4000 07FF TIM3 timer Section 13.6 on page 271
0x4000 0000 - 0x4000 03FF TIM2 timer Section 13.6 on page 271

2.3.2 Embedded SRAM

The STM32F10xxx features 20 Kbytes of static SRAM. It can be accessed as bytes, half­words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.

2.3.3 Bit banding

The Cortex™-M3 memory map includes two bit-band regions. These regions map each
word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word
in the alias region has the same eff ect as a read-modify-write oper ation on the t argeted bit in
the bit-band region.

In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region.
This allows single bit-band write and read operations to be performed.

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RM0008 Memory and bus architecture

A mapping formula shows ho w to ref erence each word in th e alias region to a correspon ding
bit in the bit-band region. The mapping formula is:

bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)

where:

bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit.

bit_band_base is the starting address of the alias region
byte_offset is the number of the by te in the b it-band reg ion that con tains the ta rgeted bit
bit_number is the bit position (0-31) of the targeted bit.

Example:

The following example shows how to map bit 2 of the byte located at SRAM address
0x20000300 in the alias region:

0x22006008 = 0x22000000 + (0x300*32) + (2*4).

Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit
2 of the byte at SRAM address 0x20000300.

Reading address 0x22006008 returns the v alue (0x0 1 o r 0 x00) of bit 2 o f th e byte at SRAM
address 0x20000300 (0x01: bit set; 0x00: bit reset ).

For more information on Bit-Banding, please refer to the Cortex™-M3 Technical Reference
Manual.

2.3.4 Embedded Flash memory

The high-performance Flash memory module has the following key features:

● Density of 128 Kbytes

● Memory organization: the Flash memory is organized as a main block and an

information block:
– Main memory block of size 16 Kb × 64 bits. The main block is divided into 128

pages of 1 Kbyte each (see Table 3).

– Information block of size 258 × 64 bits. The information block is divided into 2

pages of 2 Kbytes and 16 bytes, respectively (see Table 3).

The Flash memor y inte r face features:

● Read interface with prefetch buffer (2x64-bit words)

● Option byte Loader

● Flash Program / Erase operation

● Access / Write Protection

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Memory and bus architecture RM0008

Table 2. Flash module organization

Block Name Addresses Size (bytes)

Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte
Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte
Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte
Page 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte

Main memory

Page 4 0x0800 1000 - 0x0800 13FF 1 Kbyte

.
.
.

.
.
.

.
.
.

Page 127 0x0801 FC00 - 0x0801 FFFF 1 Kbyte

Information block

System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes

Option Bytes 0x1FFF F800 - 0x1FFF F80F 16
FLASH_ACR 0x4002 2000 - 0x4002 2003 4

FLASH_KEYR 0x4002 2004 - 0x4002 2007 4

FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4

FLASH_SR 0x4002 200C - 0x4002 200F 4

Flash memory

registers

FLASH_CR 0x4002 2010 - 0x4002 2013 4
FLASH_AR 0x4002 2014 - 0x4002 2017 4

Reserved 0x4002 2018 - 0x4002 201B 4

FLASH_OBR 0x4002 201C - 0x4002 201F 4

FLASH_WRPR 0x4002 2020 - 0x4002 2023 4

Reserved 0x4002 2024 - 0x4002 2087 100

Note: For further information on the Flash memory registers, please refer to the STM32F10xxx

Flash programming manual.

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RM0008 Memory and bus architecture

Reading Flash memory

Flash memory instructions and data access are performed through the AHB bus. The
prefetch block is used for instruction f etches thr ough the ICode bus. Arbitration is performed
in the Flash memory interface, and priority is given to data access on the DCode bus.

Read accesses can be performed with the f ollowing configuration options:

● Latency: number of wait states for a read operation programmed on-the-fly

● Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be

replaced with a single read from the Flash memory as the size of the b lock mat ches the
bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is
possible as the CPU fetches one word at a time with the next word readily available in
the prefetch buffer

● HalfCycle: for power optimization

Note: 1 These options should be used in accordance with the Flash memory access time. The wait

states represent the ratio of the SYSCLK ( system cloc k) period to the Flash memory access
time:

zero wait state, if 0 < SYSCLK
one wait state, if 24 MHz < SYSCLK
two wait states, if 48 MHz < SYSCLK

2 Half cycle configuration is not available in combination with a prescaler on the AHB. The

clock system should be equal to the HCLK clock. This feature can therefore be used only
with a direct clock from the internal, 8 MHz RC (HSI) oscillator or with the HSE oscillator.

3 The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB

clock

4 Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode

instructions. The DMA provides one free cycle after each tr ansf er. Some instructions can be
performed together with DMA transfer.

≤

24 MHz

≤

48 MHz

≤

72 MHz

Programming and erasing Flash memory

The Flash memory can be programmed 16 bits (half words) at a time.
The Flash memory erase operation can be performed at page level or on the whole Flash

area (mass-erase). The mass-erase does not affect the information blocks.
To ensure that there is no over-programming, the Flash Programming and Erase Controller

blocks are clocked by a fixed clock.
The End of write operation (programming or erasing) can trigger an interrupt. This interrupt

can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the
interrupt is served only after an exit from WFI.

Note: F or further information on Flash memory operations and register configura tions, please ref er

to the STM32F10xxx Flash programming manual.

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Memory and bus architecture RM0008

2.4 Boot configuration

In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as
shown in Table 3.

Table 3. Boot modes

Boot mode

selection pins

BOOT1 BOOT0

x 0 User Flash memory User Flash memory is selected as boot space
0 1 SystemMemory SystemMemory is selected as boot space
1 1 Embedded SRAM Embedded SRAM is selected as boot space

This aliases the physical memory associated with each boot mode to Block 000 (boot
memory). The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after
a Reset. It is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the
required boot mode.

The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they
must be kept in the required Boot mo de configuration in Standby mode.

Boot mode Aliasing

Even when aliased in the boot memory space, the related memory (Flash memory or
SRAM) is still accessible at its original memory space.

After this startup delay has elapsed, the CPU starts code ex ecution from the boot memory,
located at the bottom of the memory address space starting from 0x0000 0000.

Embedded boot loader

The embedded boot loader is used to reprogram the Flash memory using the USART1
serial interface. This program is located in the SystemMemory and is pro grammed by ST
during production.

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RM0008 Power control (PWR)

3 Power control (PWR)

3.1 Power supplies

The device requires a 2.0-to-3.6 V operating voltage supply (VDD). An embedded regulator
is used to supply the internal 1.8 V digital power.

The real-time clock (R TC) and back up registers can be po wered from the V
the main V

supply is powered off.

DD

Figure 3. Power supply overview

V

domain

DDA

A/D converter
Temp. sensor
Reset block

PLL

V

domain

DD

I/O Ring

Standby circuitry
(Wakeup logic,
IWDG)

Voltage Regulator

Backup domain

LSE crystal 32K osc
BKP registers
RCC BDCR register
RTC

1.8 V domain

Core

Memories

digital

peripherals

(from 2 V up to V

(V

DD

(V

SSA
DDA

)

(3.3 V)

(V

DD

)

V

REF-

V

)

REF+

V

DDA

V

SSA

V

SS

V

DD

Low voltage detector

)

V

BAT

voltage when

BAT

Note: 1 V

DDA

and V

must be connected to VDD and VSS, respectively.

SSA

3.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply which can be
separately filtered and shielded from noise on the PCB.

● The ADC voltage supply input is available on a separate V

● An isolated supply ground connection is provided on pin V

When available (according to package), V

must be tied to V

REF-

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DDA
SSA

SSA

pin.

.

.

Power control (PWR) RM0008

On 100-pin packages

To ensure a better accuracy on low voltage inputs , the user can connect a separ ate e xternal
reference voltage ADC input on V

2.4 V to V

DDA

.

REF+

and V

. The voltage on V

REF-

can range from

REF+

On packages with 64 pins or less

The V
voltage supply (V

REF+

and V

pins are not available, they are internally connected to the ADC

REF-

) and ground (V

DDA

3.1.2 Battery backup domain

To retain the content of the Backup registers and supply the RTC function when V
turned off, V
by another source.

The V

BAT

the RTC to operate even when the main digital supply (V
V

supply is controlled by the Power Down Reset embedded in the Reset bloc k.

BAT

Warning: During the t

If no external battery is used in the application, V
When the backup domain is supplied by V

following functions are available:

● PC14 and PC15 can be used as either GPIO or LSE pins

● PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or

second output (refer to Section 9: Backup registers (BKP) on page 132)

pin can be connected to an optional standby v oltage supplied b y a battery or

BAT

pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing

switch between V
V

rises fast and may become established during this time,

DD

a current may be injected into V
connected between V
VDD−0.6V. Refer to the datasheet for t h e value of t

SSA

RSTTEMPO

BAT

).

) is turned off. The switch to the

DD

temporization at VDD startup, the power

and VDD remains connected to V

through a diode

and V

DD

(analog switch connected to VDD), the

DD

BAT

when V

BAT

must be connected externally to VDD.

BAT

is lower than

BAT

RSTTEMPO.

BAT

. As

DD

is

Note: Due t o the f act that the switch o nly sinks a limited amount of current, the use of GPIOs PC13

to PC15 is restricted: only one I/O at a time can be used as an output, the speed has to be
limited to 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current
source (e.g. to drive an LED).

When the backup domain is supplied by V
V

is not present), the following functions are available:

DD

● PC14 and PC15 can be used as LSE pins only

● PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to section

(analog switch connected to V

BAT

because

BAT

Section 9.5.2: RTC clock calibration register (BKP_RTCCR) on page 133).

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RM0008 Power control (PWR)

3.1.3 Voltage regulator

The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.

● In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories

and digital peripherals).

● In Stop mode the regulator supplies low-pow er to the 1.8 V domain, preserving

contents of registers and SRAM

● In Standby Mode, the regulator is pow ered off . The conten ts of the registe rs and SRAM

are lost except for the Standby circuitry and the Backup Domain.

3.2 Power supply supervisor

3.2.1 Power on reset (POR)/power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting
from/down to 2 V.

The device remains in Reset mode when V

is below a specified threshold, V

DD

without the need for an external reset circuit. For more details concerning the power
on/power down reset threshold, refer to the electrical characteristics of the datasheet.

Figure 4. Power on reset/power down reset waveform

V

DD

POR

40 mV

hysteresis

Temporization
t

RSTTEMPO

Reset

3.2.2 Programmable voltage detector (PVD)

POR/PDR

PDR

,

You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting t he PVDE bit.
A PVDO flag is available , in the Power control/status register (PWR_CSR), to indicate if V

DD

is higher or lower than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if ena bled through the EXTI registers. The PVD output
interrupt can be generated when V

drops below the PVD threshold and/or when VDD

DD

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Power control (PWR) RM0008

rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration.
As an example the service routine could perform emergency shutdown tasks.

Figure 5. PVD thresholds

V

DD

PVD output

PVD threshold

100 mV
hysteresis

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RM0008 Power control (PWR)

3.3 Low-power modes

By default, the microcont roller is in Run mode aft er a system or a po wer Reset. I n Run mode
the CPU is clocked by HCLK an d the program code is executed. Several low-power modes
are available to save power when the CPU does not need to be kept running, for example
when waiting for an external event. It is up to the user to select the mo de that gi ves the best
compromise between low-po wer consumption, short startup time and available wakeup
sources.

The STM32F10xxx devices feature three low-power modes:

● Sleep mode (Cortex-M3 core stopped, peripherals kept running)

● Stop mode (all clocks are stopped)

● Standby mode (1.8V domain powered-off)

In addition, the power consumption in Run mode can be reduce by one of the following
means:

● Slowing down the system clocks

● Gating the clocks to the APB and AHB peripherals when they are unused.

Table 4. Low-power mode summary

Effect on

Mode name Entry wakeup

Effect on 1.8V

domain clocks

V

DD

domain

clocks

Voltage

regulator

Sleep
(Sleep now or

Sleep-on ­exit)

Stop

Standby

WFI Any interrupt CPU CLK OFF

WFE Wakeup event

PDDS and LPDS
bits +
SLEEPDEEP bit
+ WFI or WFE

PDDS bit +
SLEEPDEEP bit
+ WFI or WFE

Any EXTI line
(configured in the
EXTI registers)

WKUP pin rising
edge, RTC alarm,
external reset in
NRST pin,
IWDG reset

3.3.1 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by progra mming the prescaler reg isters. Th ese prescalers can also be u sed to slow
down peripherals before entering Sleep mode.

For more details refer to Section 4.3.2: Clock configuration register (RCC_CFGR).

3.3.2 Peripheral clock gating

no effect on other
clocks or analog
clock sources

All 1.8V domain
clocks OFF

None ON

ON or in low­power mode

(depends on

HSI and
HSE
oscillators
OFF

Power control
register
(PWR_CR))

OFF

In Run mode, the HCLK and PCLKx for individual peripherals and me mories can be stopped
at any time to reduce power consumption.

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Power control (PWR) RM0008

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing th e WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB Peripheral Clock enable register

(RCC_AHBENR), APB1 Peripheral Clock enable register (RCC_APB1ENR) and APB2
Peripheral Clock enable register (RCC_APB2ENR).

3.3.3 Sleep mode

Entering Sleep mode

The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism,
depending on the SLEEPONEXIT bit in the Cortex-M3 System Control register:

● Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon

as WFI or WFE instruction is executed.

● Sleep-on-exit: if the SLEEPONEXIT bit is set when the WFI instruction is executed, the

MCU enters Sleep mode as soon as it exits the lowest priority ISR.

Refer to Table 5 and Table 6 for details on how to enter Sleep mode.

Exiting Sleep mode

If the WFI instruction is used to enter Sleep mode, an y peripheral interrupt ac knowledg ed by
the nested vectored interrupt controller (NVI C) can wake up the device from Sleep mode.

If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as
an event occurs. This event can be either an interrupt enabled in the peripheral control
register but not in the NVIC, or an EXTI line configured in event mode.

This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.
Refer to Table 5 and Table 6 for more details on how to exit Sleep mode.

Table 5. Sleep-now

Sleep-now mode Description

WFI (Wait for Interrupt) or WFE (Wait fo r Event) while:

Mode entry

Mode exit

Wakeup la tency None

– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex™-M3 System Control register.

If WFI was used for entry:

Interrupt: Refer to Table 27: Vector table

If WFE was used for entry

Wakeup event: Refer to Section 6.2.3 : Wakeup event management

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RM0008 Power control (PWR)

Table 6. Sleep-on-exit

Sleep-on-exit Description

WFI (wait for interrupt) while:

Mode entry

Mode exit Interrupt: refer to Table 27: Vector table.
Wakeup la tency None

– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex™-M3 System Control register.

3.3.4 Stop mode

The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral cloc k
gating. The volta ge regulator can be configur ed either in normal or low- pow er mode . In Stop
mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved.

Entering Stop mode

Refer to Table 7 for details on how to enter Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be

put in low-power mode. This is configured by the LPDS bit of the Power control register

(PWR_CR).

If Flash memory programming is ongoing, the Stop entry is delayed until the memory
access is finished.

If an access to APB domain is ongoing, Stop mode entry is delayed until the APB access is
finished.

In Stop mode, the following features can be selected by programming individual control bits:

● Independent Watchdog (IWDG): t he IWDG is started by writing to its Key register or by

hardware option. Once started it cannot be stopped except by a Reset. See

Section 10.1 in Section 10: Independent watchdog (IWDG).

● real-time clock (RTC): this is configured by the R TCEN bit in the Back up domain control

register (RCC_BDCR)

● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status

register (RCC_CSR).

● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

Backup domain control register (RCC_BDCR).

Exiting Stop mode

Refer to Table 7 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is

selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is

incurred when waking up from St op mode . By k eeping the in ternal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.

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Power control (PWR) RM0008

Table 7. Stop mode

Stop mode Description

WFI (Wait for Interrupt) or WFE (Wait fo r Event) while:
– Set SLEEPDEEP bit in Cortex™-M3 System Control register
– Clear PDDS bit in Power Control register (PWR_CR)

Mode entry

Mode exit

Wakeup la tency HSI RC wakeup time + regulator wakeup time from Low-power mode

– Select the voltage regulator mode by configuring LPDS bit in PWR_CR

Note: To enter Stop mode, all EXTI Line pending bits (in Pending register

(EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the Stop mode

entry procedure is ignored and program execution continues.
If WFI was used for entry:

Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Table 27: Vector

table on page 98

If WFE was used for entry:

Any EXTI Line configured in event mode . Refer to Section 6.2.3: Wakeup

event management on page 102

3.3.5 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V dom ain is
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
switched off . SRAM and register contents are lost e xcept f or r egisters in the Backup domain
and Standby circuitry (see Figure 3).

Entering Standby mode

Refer to Table 8 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control

bits:

● Independent Watchdog (IWDG): t he IWDG is started by writing to its Key register or by

hardware option. Once started it cannot be stopped e xcept by a reset. See

Section 10.1 in Section 10: Independent watchdog (IWDG).

● real-time clock (RTC): this is configur ed by the R TCEN bit in the Bac kup domain control

register (RCC_BDCR)

● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status

register (RCC_CSR).

● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

Backup domain control register (RCC_BDCR)

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RM0008 Power control (PWR)

Exiting Standby mode

The microcontroller exits Standby mode when an external Reset (NRST pin), IWDG Reset,
a rising edge on WKUP pin or an RTC alarm occurs. All registers are reset after wakeup
from Standby e xcept for Power control/status register (PWR_CSR).

After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power

control/status register (PWR_CSR) indicates that the MCU was in Standby mode.

Refer to Table 8 for more details on how to exit Standby mode.

Table 8. Standby mode

Standby mode Description

WFI (Wait for Interrupt) or WFE (Wait fo r Event) while:

Mode entry

– Set SLEEPDEEP in Cortex™-M3 System Control register
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)

Mode exit

Wakeup la tency Regulator start up. Reset phase

WKUP pin rising edge, RTC alarm, external Reset in NRST pin, IWDG
Reset.

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except:

● Reset pad (still available)

● TAMPER pin if configured for tamper or calibration out

● WKUP pin, if enabled

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug f ea tures are used . This is due to the f act that the Cortex™-M3 core is
no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to

Section 20.15.1: Debug support for low-power modes.

3.3.6 Auto Wakeup (AWU) from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an
external interrupt (Auto Wakeup mode). The RTC provides a programmable time base for
waking-up from Stop or Standb y mode at regular interva ls. F or this purpose, two of the three

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Power control (PWR) RM0008

alternative RTC clock sources can be selected b y p rog r amming t he RTCSEL[1:0] bits in the

Backup domain control register (RCC_BDCR):

● Low-power 32.768 kHz external crystal oscillator (LSE OSC).

This clock source provides a precise time base with very low-power consumption (less
than 1µA added co nsu m pt ion in typic al co nd itio ns )

● Low-power internal RC Oscillator (LSI RC)

This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.

To wakeup from Stop mode with an RTC alarm event, it is necessary to:

● Configure the EXTI Line 17 to be sensitive to rising edge

● Configure the RTC to generate the RTC alarm

To wakeup from Standby mode, there is no need to configure the EXTI Line 17.

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RM0008 Power control (PWR)

3.4 Power control registers

3.4.1 Power control register (PWR_CR)

Address offset: 0x00
Reset value: 0x0000 0000 (reset by wakeup from Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Res.

1514131211109876543210

Reserved DBP PLS[2:0] PVDE CSBF CWUF PDDS LPDS

Res rwrwrwrwrwrc_w1rc_w1rwrw

Bits 31:9 Reserved, always read as 0.

Bit 8 DBP: Disable Backup Domain write protection.

In reset state, the RTC and backup registers are protected against parasitic write access. This bit
must be set to enable write access to these registers.

0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled

Bits 7:5 PLS[2:0]: PVD Level Selection.

These bits are written by software to select the voltage threshold detected by the Power Voltage
Detector

000: 2.2V
001: 2.3V
010: 2.4V
011: 2.5V
100: 2.6V
101: 2.7V
110: 2.8V
111: 2.9V

Note: Refer to the electrical characteristics of the datasheet for more details.

Bit 4 PVDE: Power Voltage Detector Enable.

This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled

Bit 3 CSBF: Clear Standby Flag.

This bit is always read as 0.
0: No effect
1: Clear the SBF Standby Flag (write).

Bit 2 CWUF: Clear Wakeup Flag.

This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cyc les. (write)

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Power control (PWR) RM0008

Bit 1 PDDS: Power Down Deepsleep.

This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.

Bit 0 LPDS: Low-Power Deepsleep.

This bit is set and cleared by software. It works together with the PDDS bit. 0: Voltage regulator on
during Stop mode
1: Voltage regulator in low-power mode during Stop mode

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RM0008 Power control (PWR)

3.4.2 Power control/status register (PWR_CSR)

Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Res.

1514131211109876543210

Reserved

Res. rw Res. r r r

Bits 31:9 Reserved, always read as 0.

Bit 8 EWUP: Enable WKUP pin

This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the

device from Standby mode.
1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration

(rising edge on WKUP pin wakes-up the system from Standby mode).

Note: This bit is reset by a system Reset.

Bits 7:3 Reserved, always read as 0.

Bit 2 PVDO: PVD Output

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V

is higher than the PVD threshold selected with the PLS[2:0] bits.

DD

1: V

is lower than the PVD threshold selected with the PLS[2:0] bits.

DD

Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or
reset until the PVDE bit is set.

Bit 1 SBF: Standby Flag

This bit is set by hardware and cleared only by a POR/PDR (Power On Reset/Power Down Reset)
or by setting the CSBF bit in the Power control register (PWR_CR)
0: Device has not been in Standby mode
1: Device has been in Standby mode

Bit 0 WUF: Wakeup Flag

This bit is set by hardware and cleared only by a POR/PDR (Power On Reset/Power Down Reset)
or by setting the CWUF bit in the Power control register (PWR_CR)

0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm
Note: An additional wakeup ev ent is detected if the WKUP pin is enab led (b y setting the EWUP bit)

when the WKUP pin level is already high.

EWUP

Reserved

PVDO SBF WUF

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Power control (PWR) RM0008

3.5 PWR register map

The following table summarizes the PWR registers.

Table 9. PWR - register map and reset values

Offset Register

000h

004h

313029282726252423222120191817161514131211

PWR_CR

Reset value 000000000

PWR_CSR

Reset value 0000

Reserved

Reserved

987654321

10

PLS[2:0]

DBP

EWUP

PVDE

Reserved

CSBF

PDDS

CWUF

SBF

PVDO

Refer to Table 1 on page 27 for the register boundary addresses.

0

LPDS

WUF

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RM0008 Reset and clock control (RCC)

4 Reset and clock control (RCC)

4.1 Reset

There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.

4.1.1 System Reset

A system Reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 3.).

A system Reset is generated when one of the following events occurs:

1. A low lev el on the NRST pin (External Reset)

2. Window Watchdog end of count condition (WWDG Reset)

3. Independent Watchdog end of count condition (IWDG Reset)

4. A software Reset (SW Reset) (see Section : Software Reset)

5. Low-power management Reset (see Section : Low-power management Reset)
The reset source can be identified by chec king the Rese t flags in the Control/Stat us register ,

RCC_CSR (see Section 4.3.10: Control/status register (RCC_CSR)).

Software Reset

The SYSRESETREQ bit in Cortex™-M3 Application Interrupt and Reset Control Register
must be set to force a software Reset on the device. Refer to the Cortex™-M3 technical
reference manual for more details.

Low-power management Reset

There are two ways to generate a low-power management Reset:

1. Reset generated when entering Stan d by mode:
This type of reset is enab led by re setting nRST_STDBY bit in User Option Bytes . In this

case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.

2. Reset when entering Stop mode:
This type of reset is enab led by resetting NRST_STOP bit in User Option Bytes. In t his

case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.

For further information on the User Option Bytes, refer to the STM32F10xxx Flash
programming manual.

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Reset and clock control (RCC) RM0008

4.1.2 Power reset

A power Reset is generated when one of the following events occurs:

1. Power On/Power down Reset (POR/PDR Reset)

2. When exiting Standby mode

A power Reset sets all registers to their reset values except the Backup domain (see

Figure 3)

These sources act on the RESET
RESET service routine vector is fixed at addresses
map.

Figure 6. Reset circuit

EXTERNAL

RESET

NRST

The Backup domain has two specific resets that affect only the Backup domain (see

Figure 3)

4.1.3 Backup domain Reset

A backup domain Reset is generated when one of the following events occurs:

1. Software Reset, triggered by setting the BDRST bit in the Backup domain control

register (RCC_BDCR).

2. V

DD

or V

power on, if both supplies have previously been powered off.

BAT

pin and it is always kept low during the delay phase. The

0x0000_0000-0x0000_0004 in the memory

V

DD

R

ON

Filter

PULSE

GENERATOR

(min 20µs)

WWDG Reset
IWDG Reset
POR/PDR Reset
Software Reset

Low-power management Reset

SYSTEM NRESET

4.2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):

● HSI oscillator clock

● HSE oscillator clock

● PLL clock

The devices have the following two secondary clock sources:

● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and

optionally the RTC used for Auto Wakeup from Stop/Standby mode.

● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-

time clock (RTCCLK)

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RM0008 Reset and clock control (RCC)

Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.

Figure 7. Clock tree

OSC_OUT

OSC_IN

OSC32_IN

OSC32_OUT

8 MHz

HSI RC

PLLSRC

4-16 MHz

HSE OSC

LSE OSC

32.768 kHz

HSI

PLLMUL

..., x16

x2, x3, x4

PLL

PLLXTPRE

/2

/128

LSE

RTCSEL[1:0]

USB

Prescaler

/2

SW

HSI

SYSCLK

HSE

CSS

72 MHz

max

to RTC

PLLCLK

RTCCLK

/1, 1.5

AHB
Prescaler
/1, 2..512

48 MHz

72 MHz max

Clock

Enable (3 bits)

/8

APB1

Prescaler

/1, 2, 4, 8, 16

TIM2, 3, 4

x1, 2 Multiplier

APB2

Prescaler

/1, 2, 4, 8, 16

TIM1 Timer

x1, 2 Multiplier

ADC
Prescaler
/2, 4, 6, 8

USBCLK

to USB interface

HCLK
to AHB bus, core,
memory and DMA

to Cortex System timer

FCLK Cortex
free running clock

36 MHz max

Peripheral Clock

Enable (13 bits)

Peripheral Clock
Enable (3 bits)

72 MHz max

Peripheral Clock

Enable (11 bits)

Peripheral Clock
Enable (1 bit)

ADCCLK

PCLK1
to APB1

peripherals

to TIM2, 3
and 4

TIMXCLK

PCLK2

to APB2
peripherals

to TIM1

TIM1CLK

to ADC

to Independent Watchdog (IWDG)

IWDGCLK

PLLCLK

HSI
HSE
SYSCLK

Legend:

HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal

MCO

LSI RC
40 kHz

Main
Clock Output

LSI

/2

MCO

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.

Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The AHB and the APB2 domains
maximum frequency is 72 MHz. The APB1 domains maximum allowed frequency is 36
MHz. The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
divided by 8. The SysTick can work either with this clock or with the Cortex clock (AHB),
configurable in the SysTick Control and Status Register. The ADCs are clocked by the cloc k
of the High Speed domain (APB2) divided by 2, 4, 6 or 8.

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Reset and clock control (RCC) RM0008

The timer clock frequencies are twice the frequency of the APB domain which they are
connected to. Nevertheless, if the APB prescaler is 1, the clock frequency of the timer is the
same as the frequency of the APB domain which it is connected to.

FCLK acts as Cortex™-M3 free running clock. For more details refer to the ARM Cortex™­M3 Technical Reference Manual.

4.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possibl e clock
sources:

● HSE external crystal/ceramic resonator

● HSE user external clock

The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Figure 8. HSE/ LSE clock sources

Hardware configuration

OSC_OUT

(HiZ)

External ClockCrystal/Ceramic Resonators

EXTERNAL

SOURCE

OSC_IN OSC_OUT

C

L1

LOAD

CAPACITORS

C

L2

External source (HSE bypass)

In this mode, an exte rnal clock source must be pro vided . It can ha v e a frequency of up to 25
MHz. You select this mode by setting the HSEBYP and HSEON

register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% dut y

cycle has to drive the OSC_IN pin while the OSC_OUT pin should b e left hi-Z. See Figure 8.

bits in the Clock control

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RM0008 Reset and clock control (RCC)

External crystal/ceramic resonator (HSE crystal)

The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.

The associated hardware configuration is shown in Figure 8. Refer to the electrical
characteristics section of the datasheet for more details.

The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register

(RCC_CIR).

The HSE Crystal can be switched on and off using the HSEON bit in the Clock control

register (RCC_CR).

4.2.2 HSI clock

The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used
directly as a system clock or divided by 2 to be used as PLL input.

The HSI RC oscillator has the advantage of providing a clock source at low cost (no e xternal
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T

After Reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock

control register (RCC_CR).

If the application is subject to voltage or temperature variations this ma y affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR).

The HSIRD Y flag in the Clock control register (RCC_CR) indicates if the HSI RC is stab le or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.

The HSI RC can be switched on and off using the HSION bit in the Clock control register

(RCC_CR).

The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 4.2.7: Clock security system (CSS) on page 53.

4.2.3 PLL

The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock
frequency. Refer to Figure 7 and Clock control register (RCC_CR).

The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL
input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL
enabled, these parameters cannot be changed.

=25°C.

A

An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt

register (RCC_CIR).

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Reset and clock control (RCC) RM0008

If the USB interface is used in the a pplica tion, th e PL L m ust be pr og rammed to output 48 or
72 MHz. This is needed to provide a 48 MHz USBCLK.

4.2.4 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.

The LSE crystal is switched on and off using the LSEON bit in Backup domain control

register (RCC_BDCR).

The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE
crystal is stable or not. At startup, the LSE crystal output clock signal is not released until
this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt

register (RCC_CIR).

External source (LSE bypass)

In this mode, an ext ernal clock source must be provided. It must have a frequency of

32.768 kHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup

domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle)

with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left Hi-Z. See Figure 8.

4.2.5 LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto Wakeup unit (AWU). The
clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to
the electrical characteristics section of the datasheets.

The LSI RC can be switched on and off using the LSION bit in the Contro l/st at us re gis te r

(RCC_CSR).

The LSIRDY flag in the Control/status registe r (RCC _C SR) indicates if the low-speed
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register

(RCC_CIR).

4.2.6 System clock (SYSCLK) selection

After a system Reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the Clock

control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently

used as system clock.

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RM0008 Reset and clock control (RCC)

4.2.7 Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a
clock failure event is sent to the break input of the TIM1 Advanced control timer and an
interrupt is generated to inform the software about the failure (Clock Security System
Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is link ed to the
Cortex™-M3 NMI (Non-Maskable Interrupt) exception vector.

Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is

automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the Clock interrupt register (RCC_CIR).

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disab ling of the external
HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used
as system clock when the failure occurs, the PLL is disabled too.

4.2.8 RTC clock

The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain.

The LSE clock is in the Backup do main, whereas the HSE and LSI clocks are not.
Consequently:

● If LSE is selected as RTC clock:

– The RTC continues to work even if the V

V

supply is maintained.

BAT

● If LSI is selected as Auto Wakeup unit (AWU) clock:

– The AWU state is not guaranteed if the V

● If the HSE clock divided by 128 is used as RTC clock:

– The RTC state is not guaranteed if the V

voltage regulator is powered off (removing power from the 1.8 V domain).

4.2.9 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.

4.2.10 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be

supply is switched off, provided the

DD

supply is powered off.

DD

supply is powered off or if the internal

DD

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Reset and clock control (RCC) RM0008

programmed in alternate function mode. One of 4 cloc k signals can be select ed as the MCO
clock.

● SYSCLK

● HSI

● HSE

● PLL clock divided by 2

The selection is controlled by the MCO[2:0] bits of the Clock configuration register

(RCC_CFGR).

4.3 RCC register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

4.3.1 Clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83 where X is undef ined.
Access: no wait state, word , half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Res. r rw Res. rw rw r rw

1514131211109 87654321 0

HSICAL[7:0] HSITRIM[4:0] Res.

rrrrrrr rrwrwrwrwrw rrw

PLL

PLLON Reserved

RDY

Bits 31:26 Reserved, always read as 0.

CSS ONHSE

BYP

HSE
RDY

HSI

RDY

HSE

ON

HSION

Bit 25 PLLRDY PLL clock ready flag

Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked

Bit 24 PLLON PLL enable

Set and reset by software to enable PLL.
Reset by hardware when entering Stop and Standby mode. This bit can not be reset if the PLL clock
is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON

Bits 23:20 Reserved, always read as 0.

Bit 19 CSSON Clock Security System enable

Set and reset by software to enable clock detector.
0: Clock detector OFF
1: Clock detector ON if external 1-25 MHz oscillator is ready.

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RM0008 Reset and clock control (RCC)

Bit 18 HSEBYP External High Speed clock Bypass

Set and reset by software in debug for bypassing oscillator with external clock. This bit can be
written only if the external 1-25 MHz oscillator is disabled.
0: external 1-25 MHz oscillator not bypassed
1: external 1-25 MHz oscillator bypassed with external clock

Bit 17 HSERDY External High Speed clock ready flag

Set by hardware to indicate that external 1-25 MHz oscillator is stable. This bit needs 6 cycles of
external 1-25 MHz oscillator clock to fall down after HSEON reset.

0: external 1-25 MHz oscillator not ready
1: external 1-25 MHz oscillator ready

Bit 16 HSEON External High Speed clock enable

Set and reset by software.
Reset by hardware to stop the external 1-25MHz oscillator when entering in Stop and Standby

mode. This bit can not be reset if the external 1-25 MHz oscillator is used directly or indirectly as
system clock or is selected to become the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON

Bits 15:8 HSICAL[7:0] Internal High Speed clock Calibration

These bits are initialized automatically at startup.

Bits 7:3 HSITRIM[4:0] Internal High Speed clock trimming

These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that
influence the frequency of the internal HSI RC.

The default v alue i s 16, wh ich, w hen adde d to th e HSICAL v alue , sh ould trim th e HSI t o 8 MHz a t T
= 25 °C. The HSI RC frequency increases when the HSICAL value increases and decreases when
the HSICAL value decreases. The trimming step is 40 kHz between two consecutive HSICAL steps.

A

Bit 2 Reserved, always read as 0.
Bit 1 HSIRDY Internal High Speed clock ready flag

Set by hardware to indicate that internal 8 MHz RC oscillator is stable. This bit needs 6 cycles of the
internal 8 MHz RC oscillator clock to fall down after HSION reset.

0: internal 8 MHz RC oscillator not ready
1: internal 8 MHz RC oscillator ready

Bit 0 HSION Internal High Speed clock enable

Set and reset by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop and Standby mode

or in case of failure of the external 1-25 MHz oscillator used directly or indirectly as system clock.
This bit can not be reset if the internal 8 MHz RC is used directly or indirectly as system clock or is
selected to become the system clock.
0: internal 8 MHz RC oscillator OFF
1: internal 8 MHz RC oscillator ON

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Reset and clock control (RCC) RM0008

4.3.2 Clock configuration register (RCC_CFGR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved MCO[2:0] Res.

Res. rw rw rw Res. rw rw rw rw rw rw rw

1514131211109 87654321 0

ADC PRE[1:0] PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw r r rw rw

USB
PRE

PLLMUL[3:0]

PLL

XTPRE

Bits 31:26 Reserved, always read as 0.
Bits 26:24 MCO Microcontroller Clock Output

Set and reset by software.
0xx: No clock
100: System clock selected
101: Internal 8 MHz RC oscillator clock selected
110: External 1-25 MHz oscillator clock selected

111: PLL clock divided by 2 selected
Notes:
– This clock output could have some truncated cycle at start-up or during MCO clock source

switching.
– When the System Clock is selected to output onto MCO, make sure that this clock does not exceed

50 MHz (the maximum I/O speed).

Bit 22 USBPRE USB prescaler

Set and reset by software to generate 48 MHz USB clock. This bit must be valid bef ore enab ling the

USB clock in the RCC_APB1ENR register. This bit can’t be reset if the USB clock is enabled.

0: PLL clock is divided by 1.5

1: PLL clock is not divided

PLL

SRC

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RM0008 Reset and clock control (RCC)

Bits 21:18 PLLMUL PLL Multiplication Factor

These bits are written by software to define the PLL multiplication factor. These bits can be written

only when PLL is disabled.

Caution: The PLL output frequency must not exceed 72 MHz.

0000: PLL input clock x 2

0001: PLL input clock x 3

0010: PLL input clock x 4

0011: PLL input clock x 5

0100: PLL input clock x 6

0101: PLL input clock x 7

0110: PLL input clock x 8

0111: PLL input clock x 9

1000: PLL input clock x 10

1001: PLL input clock x 11

1010: PLL input clock x 12

1011: PLL input clock x 13

1100: PLL input clock x 14

1101: PLL input clock x 15

1110: PLL input clock x 16

1111: PLL input clock x 16

Bit 17 PLLXTPRE HSE divider for PLL entry

Set and reset by software to divide HSE before PLL entry. This bit can be written only when PLL is

disabled.

0: HSE clock not divided

1: HSE clock divided by 2

Bit 16 PLLSRC PLL entry clock source

Set and reset by software to select PLL clock source. This bit can be written only when PLL is

disabled.

0: HSI oscillator clock / 2 selected as PLL input clock

1: HSE oscillator clock selected as PLL input clock

Bits 14:14 ADCPRE ADC prescaler

Set and reset by software to select the frequency of the clock to the ADCs.

00: PLCK2 divided by 2

01: PLCK2 divided by 4

10: PLCK2 divided by 6

11: PLCK2 divided by 8

Bits 13:11 PPRE2 APB High speed prescaler (APB2)

Set and reset by software to control APB High speed clocks division factor.

0xx: HCLK not divided

100: HCLK divided by 2

101: HCLK divided by 4

110: HCLK divided by 8

111: HCLK divided by 16

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Reset and clock control (RCC) RM0008

Bits 10:8 PPRE1 APB Low speed prescaler (APB1)

Set and reset by software to control APB Low speed clocks division factor.

Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain.

0xx: HCLK not divided

100: HCLK divided by 2

101: HCLK divided by 4

110: HCLK divided by 8

111: HCLK divided by 16

Bits 7:4 HPRE AHB prescaler

Set and reset by software to control AHB clock division factor.

0xxx: SYSCLK not divided

1000: SYSCLK divided by 2

1001: SYSCLK divided by 4

1010: SYSCLK divided by 8

1011: SYSCLK divided by 16

1100: SYSCLK divided by 64

1101: SYSCLK divided by 128

1110: SYSCLK divided by 256

1111: SYSCLK divided by 512

Note: The prefetch b uffer must be k ept on when using a prescaler different from 1 on the AHB clock.

Refer to Reading Flash memory on page 31 section for more details.

Bits 3:2 SWS System Clock Switch Status

Set and reset by hardware to indicate which cloc k source is used as system clock.

00: HSI oscillator used as system clock

01: HSE oscillator used as system clock

10: PLL used as system clock

11: not applicable

Bits 1:0 SW System clock Switch

Set and reset by software to select SYSCLK source.

Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of

the HSE oscillator used directly or indirectly as system clock (if the Cloc k Sec urity System is

enabled).

00: HSI selected as system clock

01: HSE selected as system clock

10: PLL selected as system clock

11: not allowed

58/501

RM0008 Reset and clock control (RCC)

4.3.3 Clock interrupt register (RCC_CIR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word , half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLL

HSE

HSI

HSI

LSE

RDYC

LSE

RDYF

Reserved CSSC Reser ved

Res. w wwww w

1514131211109 87654321 0

PLL

Reserved

Res. rw rw rw rw rw r r r r r r

RDYIE

HSE

RDYIE

HSI

RDYIE

LSE

RDYIE

LSI

RDYIE

CSSF Reserved

RDYC

PLL

RDYF

RDYC

HSE

RDYF

RDYC

RDYF

Bits 31:24 Reserved, always read as 0.

Bit 23 CSSC Clock Security System Interrupt Clear

Set by software to clear CSSF.
Reset by hardware when clear done.
0: CSSF not cleared
1: CSSF cleared

LSI

RDYC

LSI

RDYF

Bits 22:21 Reserved, always read as 0.

Bit 20 PLLRDYC PLL Ready Interrupt Clear

Set by software to clear PLLRDYF.
Reset by hardware when clear done.
0: PLLRDYF not cleared
1: PLLRDYF cleared

Bit 19 HSERDYC HSE Ready Interrupt Clear

Set by software to clear HSERDYF.
Reset by hardware when clear done.
0: HSERDYF not cleared
1: HSERDYF cleared

Bit 18 HSIRDYC HSI Ready Interrupt Clear

Set by software to clear HSIRDYF.
Reset by hardware when clear done.
0: HSIRDYF not cleared
1: HSIRDYF cleared

Bit 17 LSERDYC LSE Ready Interrupt Clear

Set by software to clear LSERDYF.
Reset by hardware when clear done.
0: LSERDYF not cleared
1: LSERDYF cleared

59/501

Reset and clock control (RCC) RM0008

Bit 16 LSIRDYC LSI Ready Interrupt Clear

Set by software to clear LSIRDYF.
Reset by hardware when clear done.
0: LSIRDYF not cleared
1: LSIRDYF cleared

Bits 15:13 Reserved, always read as 0.

Bit 12 PLLRDYIE PLL Ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled

Bit 11 HSERDYIE HSE Ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by the external 1-25 MHz oscillator
stabilization.

0: HSE ready interrupt disabled
1: HSE ready interrupt enabled

Bit 10 HSIRDYIE HSI Ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator
stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled

Bit 9 LSERDYIE LSE Ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by the external 40 kHz oscillator
stabilization.

0: LSE ready interrupt disabled
1: LSE ready interrupt enabled

Bit 8 LSIRDYIE LSI Ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by internal RC 40 kHz oscillator
stabilization.

0: LSI ready interrupt disabled
1: LSI ready interrupt enabled

Bit 7 CSSF Clock Security System Interrupt flag

Reset by software by writing CSSC.
Set by hardware when a failure is detected in the external 1-25 MHz oscillator.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure

Bits 6:5 Reserved, always read as 0.

Bit 4 PLLRDYF PLL Ready Interrupt flag

Reset by software by writing PLLRDYC.
Set by hardware when the PLL locks and PLLRDYDIE is set.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock

Bit3 HSERDYF HSE Ready Interrupt flag

Reset by software by writing HSERDYC.
Set by hardware when External Low Speed clock becomes stable and HSERDYDIE is set.
0: No clock ready interrupt caused by the external 1-25 MHz oscillator
1: Clock ready interrupt caused by the external 1-25 MHz oscillator

60/501

RM0008 Reset and clock control (RCC)

Bit 2 HSIRDYF HSI Ready Interrupt flag

Reset by software by writing HSIRDYC.
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator

Bit 1 LSERDYF LSE Ready Interrupt flag

Reset by software by writing LSERDYC.
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator

Bit 0 LSIRDYF LSI Ready Interrupt flag

Reset by software by writing LSIRDYC.
Set by hardware when Internal Low Speed clock becomes stable and LSIRDYDIE is set.
0: No clock ready interrupt caused by the internal RC 40 kHz oscillator
1: Clock ready interrupt caused by the internal RC 40 kHz oscillator

61/501

Reset and clock control (RCC) RM0008

4.3.4 APB2 Peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word , half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Res.

151413121110987654321 0

USART

Res.

Res. rw Res. rw rw rw rw Res. rw rw rw rw rw Res. rw

1

RST

Res.

SPI1
RST

TIM1
RST

ADC2

RST

ADC1

RST

Reserved

IOPE

RST

IOPD

RST

IOPC

RST

IOPB

RST

IOPA

RST

Bits 31:15 Reserved, always read as 0.

Bit 14 USART1RST USART1 reset

Set and reset by software.
0: No effect
1: Reset USART1

Bit 13 Reserved, always read as 0.

Res.

AFIO

RST

Bit 12 SPI1RST SPI 1 reset

Set and reset by software.
0: No effect
1: Reset SPI 1

Bit 11 TIM1RST TIM1 Timer reset

Set and reset by software.
0: No effect
1: Reset TIM1 timer

Bit 10 ADC2RST ADC 2 interface reset

Set and reset by software.
0: No effect
1: Reset ADC 2 interface

Bit 9 ADC1RST ADC 1 interface reset

Set and reset by software.
0: No effect
1: Reset ADC 1 interface

Bits 8:7 Reserved, always read as 0.

Bit 6 IOPERST IO port E reset

Set and reset by software.
0: No effect
1: Reset IO port E

62/501

RM0008 Reset and clock control (RCC)

Bit 5 IOPDRST IO port D reset

Set and reset by software.
0: No effect
1: Reset I/O port D

Bit 4 IOPCRST IO port C reset

Set and reset by software.
0: No effect
1: Reset I/O port C

Bit 3 IOPBRST IO port B reset

Set and reset by software.
0: No effect
1:Reset I/O port B

Bit 2 IOPARST I/O port A reset

Set and reset by software.
0: No effect

1: Reset I/O port A
Bit 1 Reserved, always read as 0.
Bit 0 AFIORST Alternate Function I/O reset

Set and reset by software.

0: No effect

1: Reset Alternate Function

63/501

Reset and clock control (RCC) RM0008

4.3.5 APB1 Peripheral reset register (RCC_APB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word , half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

USART

USB

I2C2

PWR

Reserved

Res. rw rw Res. rw Res. rw rw rw Res. rw rw res.

1514131211109 8765432 1 0

SPI2

Res.

RST

Res. rw Res. rw Res. rw rw rw

Reserved

RST

BKP
RST

WWD
GRST

Res.

CAN
RST

Res.

RST

Reserved

RST

I2C1

RST

Reserved

Bits 31:29 Reserved, always read as 0.

Bit 28 PWRRST Power interface reset

Set and reset by software.
0: No effect
1: Reset power interface

Bit 27 BKPRST Backup interface reset

Set and reset by software.
0: No effect
1: Reset backup interface

Bit 26 Reserved, always read as 0.

USART

3

RST

TIM4
RST

2

RST

TIM3

RST

Res.

TIM2

RST

Bit 25 CANRST CAN reset

Set and reset by software.
0: No effect

1: Reset CAN
Bit 24 Reserved, always read as 0.
Bit 23 USBRST USB reset

Set and reset by software.

0: No effect

1: Reset USB
Bit 22 I2C2RST I2C 2 reset

Set and reset by software.

0: No effect

1: Reset I2C 2
Bit 21 I2C1RST I2C 1 reset

Set and reset by software.

0: No effect

1: Reset I2C 1

Bits 20:19 Reserved, always read as 0.

64/501

RM0008 Reset and clock control (RCC)

Bit 18 USART3RST USART 3 reset

Set and reset by software.

0: No effect

1: Reset USART 3
Bit 17 USART2RST USART 2 reset

Set and reset by software.

0: No effect

1: Reset USART 2

Bits 16:15 Reserved, always read as 0.

Bit 14 SPI2RST SPI 2 reset

Set and reset by software.

0: No effect

1: Reset SPI 2

Bits 13:12 Reserved, always read as 0.

Bit 11 WWDGRST Window Watchdog reset

Set and reset by software.

0: No effect

1: Reset window watchdog

Bits 10:3 Reserved, always read as 0.

Bit 2 TIM4RST Timer 4 reset

Set and reset by software.

0: No effect

1: Reset timer 4

Bit 1 TIM3RST Timer 3 reset

Set and reset by software.

0: No effect

1: Reset timer 3

Bit 0 TIM2RST Timer 2 reset

Set and reset by software.

0: No effect

1: Reset timer 2

65/501

Reset and clock control (RCC) RM0008

4.3.6 AHB Peripheral Clock enable register (RCC_AHBENR)

Address offset: 0x14
Reset value: 0x0000 0014
Access: no wait state, word , half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109 87654321 0

Reserved

Bits 31:5 Reserved, always read as 0.

Bit 4 FLITFEN FLITF clock enable

Set and reset by software to disable/enable FLITF clock during sleep mode.

0: FLITF clock disabled during Sleep mode

1: FLITF clock enabled during Sleep mode

Bit 3 Reserved, always read as 0.
Bit 2 SRAMEN SRAM interface clock enable

Set and reset by software to disable/enable SRAM interface clock during Sleep mode.

0: SRAM interface clock disabled during Sleep mode.

1: SRAM interface clock enabled during Sleep mode

Bit 1 Reserved, always read as 0.

FLITF

EN

rw rw rw

Res.

SRAM

EN

Res.

DMA

EN

Bit 0 DMAEN DMA clock enable

Set and reset by software.

0: DMA clock disabled

1: DMA clock enabled

66/501

RM0008 Reset and clock control (RCC)

4.3.7 APB2 Peripheral Clock enable register (RCC_APB2ENR)

Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in APB2 domain

is on going. In this case, wait states are inserted until this access to APB2 peripheral is
finished.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Res.

1514131211109 87654321 0

USAR

Res;

Res. rw Res. rw rw rw rw Res. rw rw rw rw rw Res. rw

T1

EN

SPI1ENTIM1ENADC2ENADC1

Res;

EN

Reserved

IOPEENIOPDENIOPCENIOPBENIOPA

EN

Res.

AFIO

EN

Bits 31:15 Reserved, always read as 0.

Bit 14 USART1EN USART1 clock enable

Set and reset by software.

0: USART1 clock disabled

1: USART1 clock enabled
Bit 13 Reserved, always read as 0.
Bit 12 SPI1EN SPI 1 clock enable

Set and reset by software.

0: SPI 1 clock disabled

1: SPI 1 clock enabled
Bit 11 TIM1EN TIM1 Timer clock enable

Set and reset by software.

0: TIM1 timer clock disabled

1: TIM1 timer clock enabled
Bit 10 ADC2EN ADC 2 interface clock enable

Set and reset by software.

0: ADC 2 interface clock disabled

1: ADC 2 interface clock enabled

Bit 9 ADC1EN ADC 1 interface clock enable

Set and reset by software.

0: ADC 1 interface disabled

1: ADC 1 interface clock enabled

Bits 8:7 Reserved, always read as 0.

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Reset and clock control (RCC) RM0008

Bit 6 IOPEEN I/O port E clock enable

Set and reset by software.

0: I/O port E clock disabled

1: I/O port E clock enabled

Bit 5 IOPDEN I/O port D clock enable

Set and reset by software.

0: I/O port D clock disabled

1: I/O port D clock enabled

Bit 4 IOPCEN I/O port C clock enable

Set and reset by software.

0: I/O port C clock disabled

1:I/O port C clock enabled

Bit 3 IOPBEN I/O port B clock enable

Set and reset by software.

0: I/O port B clock disabled

1:I/O port B clock enabled

Bit 2 IOPAEN I/O port A clock enable

Set and reset by software.

0: I/O port A clock disabled

1:I/O port A clock enabled

Bit 1 Reserved, always read as 0.
Bit 0 AFIOEN Alternate Function I/O clock enable

Set and reset by software.

0: Alternate Function I/O clock disabled

1:Alternate Function I/O clock enabled

68/501

RM0008 Reset and clock control (RCC)

4.3.8 APB1 Peripheral Clock enable register (RCC_APB1ENR)

Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain

is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

Res. rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPI2

Res.

Res. rw Res. rw Res. rw rw rw

EN

PWRENBKP

Reserved

EN

WWD

GEN

Bits 31:29 Reserved, always read as 0.

Bit 28 PWREN Power interface clock enable

Set and reset by software.

0: Power interface clock disabled

1: Power interface clock enable

Bit 27 BKPEN Backup interface clock enable

Set and reset by software.

0: Backup interface clock disabled

1: Backup interface clock enabled

Bit 26 Reserved, always read as 0.

Res.

CAN

EN

Res.

USBENI2C2ENI2C1

Reserved

EN

Reserved

USART3ENUSART2

TIM4ENTIM3ENTIM2

EN

Res.

EN

Bit 25 CANEN CAN clock enable

Set and reset by software.

0: CAN clock disabled

1: CAN clock enabled

Bit 24 Reserved, always read as 0.
Bit 23 USBEN USB clock enable

Set and reset by software.

0: USB clock disabled

1: USB clock enabled

Bit 22 I2C2EN I2C 2 clock enable

Set and reset by software.

0: I2C 2 clock disabled

1: I2C 2 clock enabled

Bit 21 I2C1EN I2C 1 clock enable

Set and reset by software.

0: I2C 1 clock disabled

1: I2C 1 clock enabled

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Reset and clock control (RCC) RM0008

Bits 20:19 Reserved, always read as 0.

Bit 18 USART3EN USART 3 clock enable

Set and reset by software.

0: USART 3 clock disabled

1: USART 3 clock enabled

Bit 17 USART2EN USART 2 clock enable

Set and reset by software.

0: USART 2 clock disabled

1: USART 2 clock enabled

Bits 16:15 Reserved, always read as 0.

Bit 14 SPI2EN SPI 2 clock enable

Set and reset by software.

0: SPI 2 clock disabled

1: SPI 2 clock enabled

Bits 13:12 Reserved, always read as 0.

Bit 11 WWDGEN Window Watchdog clock enable

Set and reset by software.

0: Window watchdog clock disabled

1: Window watchdog clock enabled

Bits 10:3 Reserved, always read as 0.

Bit 2 TIM4EN Timer 4 clock enable

Set and reset by software.

0: Timer 4 clock disabled

1: Timer 4 clock enabled

Bit 1 TIM3EN Timer 3 clock enable

Set and reset by software.

0: Timer 3 clock disabled

1: Timer 3 clock enabled

Bit 0 TIM2EN Timer 2 clock enable

Set and reset by software.

0: Timer 2 clock disabled

1: Timer 2 clock enabled

70/501

RM0008 Reset and clock control (RCC)

4.3.9 Backup domain control register (RCC_BDCR)

Address: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register

(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write

protected and the DBP bit in the Power control register (PWR_CR)has to be set before
these can be modified. Refer to Section 9.1 on page 132 for further information. These bits
are only reset after a Backup domain Reset and V
Reset will not have any effect on these bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved BDRST

Res. rw

1514131211109 87654321 0

RTC

EN

rw Res. rw rw Res. rw r rw

Bits 31:17 Reserved, always read as 0.

Reserved RTCSEL[1:0] Reserved

power on. Any inte rnal or external

BAT

LSE

BYP

LSE

RDY

LSEON

Bit 16 BDRST Backup domain software reset

Set and reset by software.

0: Reset not activated

1: Resets the entire Backup domain
Bit 15 RTCEN RTC clock enable

Set and reset by software.

0: RTC clock disabled

1: RTC clock enabled

Bits 14:10 Reserved, always read as 0.

Bits 9:8 RTCSEL[1:0] RTC clock source selection

Set by software to select the clock source for the RTC. Once the RTC clock source has been

selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be

used to reset them.

00: No clock

01: LSE oscillator clock used as RTC clock

10: LSI oscillator clock used as RTC clock

11: HSE oscillator clock divided by 128 used as RTC clock

Bits 7:3 Reserved, always read as 0.

Bit 2 LSEBYP External Low Speed oscillator Bypass

Set and reset by software to bypass oscillator in debug mode. This bit can be written only when the

external 32 kHz oscillator is disabled.

0: LSE oscillator not bypassed

1: LSE oscillator bypassed

71/501

Reset and clock control (RCC) RM0008

Bit 1 LSERDY External Low Speed oscillator Ready

Set and reset by hardware to indicate when the external 32 kHz oscillator is stable. This bit needs 6

cycles of external Low Speed oscillator clock to fall down after LSEON reset.

0: External 32 kHz oscillator not ready

1: External 32 kHz oscillator ready

Bit 0 LSEON External Low Speed oscillator enable

Set and reset by software.

0: External 32 kHz oscillator OFF

1: External 32 kHz oscillator ON

4.3.10 Control/status register (RCC_CSR)

Address: 0x24
Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LPWR

WWDG

RSTF

rw rw rw rw rw rw Res. rw Res.
1514131211109 87654321 0

Bit 31 LPWRRSTF Low-Power reset flag

Bit 30 WWDGRSTF Window watchdog reset flag

Bit 29 IWDGRSTF Independent Watchdog reset flag

RSTF

IWDG
RSTF

SFT

RSTF

POR

RSTF

PIN

RSTF

Res. RMVF Reserved

Reserved

Res. r rw

LSI

RDY

Reset by software by writing the RMVF bit.

Set by hardware when a Low-power management reset occurs.

0: No Low-power management reset occurred

1: Low-power management reset occurred

For further information on Low-power management reset, refer to Section : Low-power management

Reset.

Reset by software by writing the RMVF bit.

Set by hardware when a window watchdog reset occurs.

0: No window watchdog reset occurred

1: Window watchdog reset occurred

Reset by software by writing the RMVF bit.

Set by hardware when a watchdog reset from V

domain occurs.

DD

0: No watchdog reset occurred

1: Watchdog reset occurred

LSION

72/501

RM0008 Reset and clock control (RCC)

Bit 28 SFTRSTF Software Reset flag

Reset by software by writing the RMVF bit.

Set by hardware when a software reset occurs.

0: No software reset occurred

1: Software reset occurred

Bit 27 PORRSTF POR/PDR reset flag

Reset by software by writing the RMVF bit.

Set by hardware when a POR/PDR reset occurs.

0: No POR/PDR reset occurred

1: POR/PDR reset occurred

Bit 26 PINRSTF PIN reset flag

Reset by software by writing the RMVF bit.

Set by hardware when a reset from the NRST pin occurs.

0: No reset from NRST pin occurred

1: Reset from NRST pin occurred

Bit 25 Reserved, always read as 0.
Bit 24 RMVF Remove reset flag

Set and reset by software to reset the value of the reset flags.

0: Reset of the reset flags not activated

1: Reset the value of the reset flags

Bits 23:2 Reserved, always read as 0.

Bit 1 LSIRDY Internal Low Speed oscillator Ready

Set and reset by hardware to indicate when the internal RC 40 kHz oscillator is stable. This bit

needs 3 cycles of internal RC 40 kHz oscillator to fall down after LSION reset.

0: Internal RC 40 kHz oscillator not ready

1: Internal RC 40 kHz oscillator ready

Bit 0 LSION Internal Low Speed oscillator enable

Set and reset by software.

0: Internal RC 40 kHz oscillator OFF

1: Internal RC 40 kHz oscillator ON

73/501

Reset and clock control (RCC) RM0008

4.4 RCC register map

Table 10. RCC - register map and reset values

Offset Register

000h

004h

008h

00Ch

010h

014h

313029282726252423222120191817161514131211

RCC_CR

Reset value 00 0000000 00 000 10 000 11

RCC_CFGR

Reset value 000 0000 0000000000000000000

RCC_CIR

Reset value 0 00000 000000 00000

RCC_APB2RSTR

Reset value 0 0000 00000 0

RCC_APB1RSTR

Reset value 00 0 000 00 0 0 000

RCC_AHBENR

Reset value 1 1 0

Reserved

Reserved

Reserved

Reserved

PWRRST

MCO [2:0]

BKPRST

Reserved

PLL ON

PLL RDY

Reserved

CANRST

Reserved

Reserved

PLLMUL[3:0]

USBPRE

Reserved

CSSC

Reserved

USBRST

I2C2RST

I2C1RST

CSSON

PLLRDYC

HSERDYC

Reserved

Reserved

HSEBYP

HSIRDYC

USART3RST

HSERDY

PLLXTPRE

LSERDYC

USART2RST

HSEON

PLLSRC

LSIRDYC

987654321

10

HSICAL[7:0] HSITRIM[4:0]

ADC

Reserved

PRE
[1:0]

Reserved

USART1RST

SPI2RST

PPRE2

[2:0]

Reserved

Reserved

PLLRDYIE

SPI1RST

PPRE1

HSERDYIE

TIM1RST

WWDGRST

[2:0]

HSIRDYIE

LSERDYIE

ADC2RST

ADC1RST

HPRE[3:0]

CSSF

LSIRDYIE

Reserved

Reserved

Reserved

IOPERST

SWS

[1:0]

PLLRDYF

HSERDYF

IOPBRST

IOPDRST

IOPCRST

FLITFEN

Reserved

HSIRDY

Reserved

SW
[1:0]

HSIRDYF

LSERDYF

Reserved

IOPARST

TIM4RST

TIM3RST

SRAMEN

Reserved

0

HSION

LSIRDYF

AFIORST

TIM2RST

DMAEN

018h

01Ch

020h

024h

RCC_APB2ENR

Reset value 0 0000 00000 0

RCC_APB1ENR

Reset value 00 0 000 00 0 0 000

RCC_BDCR

Reset value 00 00 000

RCC_CSR

Reset value 000011 0 00

Reserved

LPWRSTF

WWDGRSTF

BKPEN

PWREN

SFTRSTF

PORRSTF

IWDGRSTF

CANEN

Reserved

Reserved

PINRSTF

Reserved

Reserved

USBEN

Reserved

RMVF

SPI1EN

TIM1EN

ADC2EN

USART1EN

Reserved

I2C2EN

I2C1EN

USART3EN

USART2EN

Reserved

Reserved

BDRST

RTCEN

SPI2EN

Reserved

Reserved

Reserved

ADC1EN

WWDGEN

RTC

SEL
[1:0]

IOPEEN

Reserved

Reserved

Reserved

IOPDEN

IOPBEN

IOPCEN

IOPAEN

TIM4EN

LSEBYP

Refer to Table 1 on page 27 for the register boundary addresses.

Reserved

TIM3EN

LSERDY

LSIRDY

AFIOEN

TIM2EN

LSEON

LSION

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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

5 General-purpose and alternate-function I/Os (GPIOs

and AFIOs)

5.1 GPIO functional description

Each of the general-purpose I/O ports has two 32-bit configuration registers (G PIOx_CRL,
GPIOx_CRH), two 32-bit data reg isters (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset
register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register
(GPIOx_LCKR).

Subject to the specific hardware chara cteristics of each I/O port listed in the datasheet, each
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
in several modes:

– Input floating
– Input pull-up
– Input-pull-down
– Analog Input
– Output open-drain
– Output push-pull
– Alternate function pu sh- p ull
– Alternate function open-drain

Each I/O port bit is freely programmable , how ev er the I /O port registers hav e to be accessed
as 32-bit words (half-word or byte accesses are not allowed). The purpose of the
GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to an y of
the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the
modify access.

Figure 9 shows the basic structure of an I/O Port bit.

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General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

Figure 9. Basic structure of a standard I/O port bit

V

V

V

on/off

on/off

DD

P-MOS

N-MOS

SS

DD

V

SS

Push-pull,
open-drain or
disabled

V

DD

V

SS

Protection
diode

Protection
diode

ai14781

I/O pin

To on-chip
peripheral

Read

Write

Read/write

From on-chip
peripheral

Analog Input

Alternate Function Input

Input data register

Bit set/reset registers

Output data register

Alternate Function Output

TTL Schmitt

trigger

Input driver

Output driver

on/off

Output
control

Figure 10. Basic structure of a five-volt tolerant I/O port bit

V

V

on/off

on/off

DD

P-MOS

N-MOS

SS

V

V

Push-pull,
open-drain or
disabled

1. V

To on-chip
peripheral

Analog Input

Alternate Function Input

on/off

Read

TTL Schmitt

Input data register

Write

trigger

Input driver

Output driver

Bit set/reset registers

Read/write

From on-chip
peripheral

is a potential specific to five-volt tolerant I/Os and different from VDD.

DD_FT

Output data register

Alternate Function Output

Output
control

DD

(1)

V

DD_FT

Protection
diode

ai14782

I/O pin

SS

V

SS

76/501

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

Table 11. Port bit configuration table

Configuration mode CNF1 CNF0 MODE1 MODE0

General purpose
output

Alternate Function
output

Push-pull
Open-drain 1 0 or 1
Push-pull
Open-drain 1 don’t care
Analog input
Input floating 1 don’t care

Input

Input pull-down
Input pull-up 1

Table 12. Output MODE bits

MODE[1:0] Meaning

00 Reserved
01 Max. output speed 10 MHz
10 Max. output speed 2 MHz
11 Max. output speed 50 MHz

0

0

0 don’t care

1

0

0

10

01
10
11

see Table 12

00

PxODR

Register

0 or 1

don’t care

0

77/501

General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

5.1.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and the I/O ports are
configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b).

The JTAG pins are in input PU/PD after reset:

PA15: JTDI in PU
PA14: JTCK in PD
PA13: JTMS in PU
PB4: JNTRST in PU

When configured as output, the value written to the Output Data register (GPIOx_ODR) is
output on the I/O pin. It is possible t o use the output driv er in Push-Pull mode o r Open-Drain
mode (only the N-MOS is activat ed when outputting 0).

The Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every
APB2 clock cycle.

All GPIO pins have a internal weak pull-up and weak pull-down which can be activated or
not when configured as input.

5.1.2 Atomic bit set or bit reset

There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify only one or several bits in a single atomic APB2 write
access.

This is achieved by programming to ‘1’ the Bit Set/Reset Register (GPIOx_BSRR, or for
reset only GPIOx_BRR) to select the bits you want to modify. The unselected bits will not be
modified.

5.1.3 External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode. For more information on external interrupts, refer to:

● Section 6.2: External interrupt/event controller (EXTI) on page 101 and

● Section 6.2.3: Wakeup event management on page 102.

5.1.4 Alternate functions (AF)

It is necessary to program the Po rt Bit Configuration Register before using a default
alternate function.

● For alternate function inputs, the port can be configured either:

– in Input mode (floating, pull-up or pull-down)
– in Alternate Function Output mode. In this case the input driver is configured in

input floating mode

● For Alternate Function Outputs, the port must be configured in Alternate Function

Output mode (Push-Pull or Open-Drain).

● For bidirectional Alternate Functions, the port bit must be configured in Alternate

Function Output mode (Push-Pull or Open-Drain). In this case the input driver is
configured in input floating mode

78/501

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

If you configure a port bit as Alternate Function Output, this disconnects the output register
and connects the pin to the output signal of an on-chip peripheral.

If software configures a GPIO pin as Alternate Function Output, but peripheral is not
activated, its output is not specified.

5.1.5 Software remapping of I/O alternate functions

To optimize the number of peripheral I/O functions for different device packages, it is
possible to remap some alternate functions to some other pins. This is achieved by
software, by progr ammin g the correspon ding registers ( ref e r to AFIO regi ster description on

page 92. In that case, the alternate functions are no longer mapped to their original

assignations.

5.1.6 GPIO locking mechanism

The locking mechanism allows the IO configur ation to be f rozen . When th e LOCK sequence
has been applied on a port bit, it is no longer possible to modify the value of the port bit until
the next reset.

5.1.7 Input configuration

When the I/O Port is programmed as Input:

● The Output Buffer is disabled

● The Schmitt Trigger Input is activated

● The weak pull-up and pull-down resistors are activated or not depending on input

configuration (pull-up, pull-down or floating):

● The data present on the I/O pin is sampled into the Input Data Register every APB2

clock cycle

● A read access to the Input Data Register obtains the I/O State.

The Figure 11 on page 79 shows the Input Configuration of the I/O Port bit.

Figure 11. Input floating/pull up/pull down configurations

V

DD

on/off

on

TTL Schmitt

trigger

on/off

V

SS

79/501

1. V

Read

Write

Bit set/reset registers

Read/write

is a potential specific to five-volt tolerant I/Os and different from VDD.

DD_FT

Input data register

input driver

output driver

Output data register

V

DD

V

SS

or V

DD_FT

protection
diode

protection
diode

(1)

I/O pin

ai14783

General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

5.1.8 Output configuration

When the I/O Port is programmed as Output:

● The Output Buffer is enabled:

– Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in

the Output register leaves the port in Hi-Z. (the P-MOS is never activated)

– Push-Pull Mode: A “0” in the Output register a ctiva tes the N-MOS while a “ 1” in the

Output register activates the P-MOS.

● The Schmitt Trigger Input is activated.

● The weak pull-up and pull-down resistors are disabled.

● The data present on the I/O pin is sampled into the Input Data Register every APB2

clock cycle

● A read access to the Input Data Register gets the I/O state in open dra in mode

● A read access to the Output Data register gets the last written value in Push-Pull mode

The Figure 12 on page 80 shows the Output configuration of the I/O Port bit.

Figure 12. Output configuration

Read

TTL Schmitt

trigger

Write

Read/write

1. V

Input data register

Input driver

Output driver

Bit set/reset registers

Output data register

is a potential specific to five-volt tolerant I/Os and different from VDD.

DD_FT

5.1.9 Alternate function configuration

When the I/O Port is programmed as Alternate Function:

● The Output Buffer is turned on in Open Drain or Push-Pull configuration

● The Output Buffer is driven b y the sign al coming from t he periphera l (alternate function

out)

● The Schmitt Trigger Input is activated

● The weak pull-up and pull-down resistors are disabled.

● The data present on the I/O pin is sampled into the Input Data Register every APB2

clock cycle

● A read access to the Input Data Register gets the I/O state in open dra in mode

● A read access to the Output Data register gets the last written value in Push-Pull mode

Output

control

on

DD_FT

ai14784

(1)

I/O pin

V

V

DD

P-MOS

N-MOS

SS

Push-pull or
Open-drain

V

DD

V

SS

or V

Protection
diode

Protection
diode

80/501

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

The Figure 13 on page 81 shows the Alternate Function Configuration of the I/O Port bit.
Also, refer to Section 5.4: AFIO register description on page 92 for further information.

A set of Alternate Function I/O registers allow you to remap some alternate functions to
different pins. Refer to

Figure 13. Alternate function configuration

To on-chip
peripheral

Read

Write

Read/write

From on-chip
peripheral

1. V

DD_FT

Alternate Function Input

Input data register

Bit set/reset registers

Output data register

Alternate Function Output

is a potential specific to five-volt tolerant I/Os and different from VDD.

5.1.10 Analog input configuration

When the I/O Port is programmed as Analog Input Configuration:

● The Output Buffer is disabled.

● The Schmitt Trigger Input is de-activated providing ze ro consumption for every analog

value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0).

● The weak pull-up and pull-down resistors are disabled.

● Read access to the Input Data Register gets the value “0”.

TTL Schmitt

trigger

Input driver

Output driver

Output
control

on

DD_FT

I/O pin

ai14785

(1)

V

V

DD

SS

P-MOS

N-MOS

push-pull or
open-drain

V

DD

VSS

or V

Protection
diode

Protection
diode

The Figure 14 on page 82 shows the High impedance-Analog Input Configu r ation of the I/ O
Port bit.

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General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

Figure 14. High impedance-analog input configuration

To on-chip
peripheral

Read

Write

Read/write

From on-chip
peripheral

Analog Input

Bit set/reset registers

off

0

Input data register

Input driver

Output data register

TTL Schmitt

trigger

V

DD

V

SS

or V

Protection
diode

DD_FT

Protection
diode

I/O pin

ai14786

(1)

82/501

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

5.2 GPIO register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

5.2.1 Port configuration register low (GPIOx_CRL) (x=A..E)

Address offset: 0x00
Reset value: 0x4444 4444

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CNF7[1:0] MODE7[1:0] CNF6[1:0] MODE6[1:0] CNF5[1:0] MODE5[1:0] CNF4[1:0] MODE4[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210

CNF3[1:0] MODE3[1:0] CNF2[1:0] MODE2[1:0] CNF1[1:0] MODE1[1:0] CNF0[1:0] MODE0[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30, 27:26, 23:22,

19:18, 15:14, 11:10, 7:6, 3:2

Bits 29:28, 25:24, 21:20,

17:16, 13:12, 9:8, 5:4, 1:0

CNFy[1:0]: Port x configuration bits (y= 0 .. 7)

These bits are written by software to configure the corresponding I/O port.
Refer to Table 11: Port bit configuration table on page 77.
In input mode (MODE[1:0]=00):
00: Analog input mode
01: Floating input (reset state)
10: Input with pull-up / pull-down
11: Reserved

In output mode (MODE[1:0]

> 00):

00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain

MODEy[1:0]: Port x mode bits (y= 0 .. 7)

These bits are written by software to configure the corresponding I/O port.
Refer to Table 11: Port bit configuration table on page 77.
00: Input mode (reset state)
01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.

83/501

General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

5.2.2 Port configuration register high (GPIOx_CRH) (x=A..E)

Address offset: 0x04
Reset value: 0x4444 4444

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210

CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30, 27:26, 23:22,

19:18, 15:14, 11:10, 7:6, 3:2

CNFy[1:0]: Port x configuration bits (y= 8 .. 15)

These bits are written by software to configure the corresponding I/O port.
Refer to Table 11: Port bit configuration table on page 77.
In input mode (MODE[1:0]=00):
00: Analog input mode
01: Floating input (reset state)
10: Input with pull-up / pull-down
11: Reserved

In output mode (MODE[1:0]

> 00):

00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain

Bits 29:28, 25:24, 21:20,

17:16, 13:12, 9:8, 5:4, 1:0

MODEy[1:0]: Port x mode bits (y= 8 .. 15)

These bits are written by software to configure the corresponding I/O port.
Refer to Table 11: Port bit configuration table on page 77.
00: Input mode (reset state)
01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.

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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

5.2.3 Port input data register (GPIOx_IDR) (x=A..E)

Address offset: 0x08h
Reset value: 0x00000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109876543210

IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0

rrrrrrr r r rrrrrrr

Bits 31:16 Reserved, always read as 0.

Bits 31:0 IDRy[15:0]: Port input data (y= 0 .. 15)

These bits are read only and can be accessed in Word mode only. They contain
the input value of the corresponding I/O port.

5.2.4 Port output data register (GPIOx_ODR) (x =A..E)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109876543210

ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, always read as 0.

Bits 15:0 ODRy[15:0]: Port output data (y= 0 .. 15)

These bits can be read and written by software and can be accessed in Word
mode only.

Note: For atomic bit set/reset, the ODR bits can be individually set and reset by
writing to the GPIOx_BSRR register (x = A .. E).

85/501

General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

5.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..E)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0

www ww wwwwwwwwwww

1514131211109876543210

BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0

www ww wwwwwwwwwww

Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit

Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BSy: Port x Set bit y (y= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Set the corresponding ODRx bit

5.2.6 Port bit reset register (GPIOx_BRR) (x=A..E)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109876543210

BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0

www ww wwwwwwwwwww

Bits 31:16 Reserved

Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit

86/501

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

5.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..E)

This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit it is no longer possible to modify the value of
the port bit until the next reset.

Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).
Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved LCKK

rw

1514131211109876543210

LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved

Bit 16 LCKK[16:0]: Lock key

This bit can be read anytime. It can only be modified using the Lock Key Writing
Sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. GPIOx_LCKR register is locked until an
MCU reset occurs.

LOCK Key Writing Sequence:

Write 1
Write 0
Write 1
Read 0

Read 1 (this read is optional but confirms that the lock is active)
Notes:
During the LOCK Key Writing sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence will abort the lock.

Bits 15:0 LCKy: Port x Lock bit y (y= 0 .. 15)

These bits are read write but can only be written when the LCKK bit is 0.

0: Port configuration not locked

1: Port configuration locked.

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General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

5.3 Alternate function I/O and debug configuration (AFIO)

To optimize the number of peripherals available for the 64-pin or the 100-pin package, it is
possible to remap some alternate functions to some other pins. This is achieved by
software, by programming the AF remap and debug I/O configuration register

(AFIO_MAPR) on page 93. In this case, the alternate functions are no longer mapped to

their original assignations.

5.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15

The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O
PC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the
GP IOs function.

Note: 1 The PC14/PC15 GPIO functionality is lost when the 1.8 V domain is powered off (by

entering standby mode) or when the backup domain is supplied by V
supplied). In this case the IOs are set in analog input mode.

2 Refer to the note on IO usage restrictions in Section 3.1.2 on page 34.

5.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1

The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1
by programming the PD01 _REMAP bit in the AF remap and de bug I/O config uration register

(AFIO_MAPR).

(VDD no more

BAT

This remap is available only on 36-, 48- and 64-pin packag es (P D0 and PD1 are available
on 100-pin packages, no need for remapping).

Note: The use of PD0 and PD1 in output mode is limited since PD0 and PD1 can only be used in

output mode at 50 MHz.

5.3.3 BXCAN alternate function remapping

The BXCAN signal can be mapped on Port A, Port B or Port D as shown in Table 13.

Table 13. BXCAN alternate function remapping

Alternate function

CANRX PA11 PB8 PD0
CANTX PA12 PB9 PD1

1. Remap not available on 36-pin package

CAN_REMAP[1:0] =

“00”

CAN_REMAP[1:0] =

“10”

(1)

CAN_REMAP[1:0] =

“11”

5.3.4 JTAG/SWD alternate function remapping

The debug interface signals are mapped on the GPIO ports as shown in Table 14.

Table 14. Debug interface signals

Alternate function GPIO port

JTMS / SWDIO PA13

JTCK / SWCLK PA14

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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

Table 14. Debug interface signals (continued)

Alternate function GPIO port

JTDI PA15

JTDO / TRACESWO PB3

JNTRST PB4
TRACECK PE2
TRACED0 PE3
TRACED1 PE4
TRACED2 PE5
TRACED3 PE6

To optimize the number of free GPIOs during deb ug gin g, this m app ing ca n be conf ig ured in
different ways by programming the SWJ_CFG[1:0] bi ts in the AF remap and debug I/O

configuration register (AFIO_MAPR). Refer to Table 15

Table 15. Debug port mapping

SWJ I/O pin assigned

SWJ

_CFG

[2:0]

Available debug ports

PA.13 /

JTMS/

SWDIO

PA.14 /

JTCK/S

WCLK

PA.15 /

JTDI

PB.3 /

JTDO/

TRACE

SWO

PB.4/

JNTRST

Full SWJ (JTAG-DP + SW-DP)

000

(Reset state)
Full SWJ (JTAG-DP + SW-DP)

001

but without JNTRST
JTAG-DP Disabled and

010

SW-DP Enabled
JTAG-DP Disabled and

100

SW-DP Disabled

free free free free free

Other Forbidden

1. Released only if not using asynchronous trace.

5.3.5 Timer alternate function remapping

Timer 4 channels 1 to 4 can be remapped from Port B to Port D.
Other timer remapping possibilities are listed in Table 17 to Table 19.
Refer to AF remap and debug I/ O configuration register (AFIO_MAPR).

Table 16. Timer 4 alternate function remapping

Alternate function TIM4_REMAP = 0 TIM4_REMAP = 1

TIM4_CH1 PB6 PD12

XXX X X

XXX xfree

X X free free

(1)

free

(1)

TIM4_CH2 PB7 PD13

89/501

General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

Table 16. Timer 4 alternate function remapping

Alternate function TIM4_REMAP = 0 TIM4_REMAP = 1

TIM4_CH3 PB8 PD14
TIM4_CH4 PB9 PD15

1. Remap available only for 100-pin package.

Table 17. Timer 3 alternate function remapping

(1)

Alternate function

TIM3_REMAP[1:0] =

“00” (no remap)

TIM3_REMAP[1:0] =
“10” (partial remap)

TIM3_REMAP[1:0] =

“11” (full remap)

TIM3_CH1 PA6 PB4 PC6
TIM3_CH2 PA7 PB5 PC7
TIM3_CH3 PB0 PC8
TIM3_CH4 PB1 PC9

1. Remap available only for 64-pin, 100-pin packages.

Table 18. Timer 2 alternate function remapping

Alternate function

TIM2_REMAP[1:

0] = “00” (no

remap)

TIM2_REMAP[1:

0] = “01” (partial

remap)

TIM2_REMAP[1:
0] = “10” (partial

remap)

(1)

TIM2_REMAP[1:

TIM2_CH1/ETR PA0 PA15 PA0 PA15

TIM2_CH2 PA1 PB3 PA1 PB3
TIM2_CH3 PA2 PB10
TIM2_CH4 PA3 PB11

1. Remap not available on 36-pin package.

Table 19. Timer 1 alternate function remapping

Alternate functions

mapping

TIM1_REMAP[1:0] =

“00” (no remap)

TIM1_REMAP[1:0] =
“01” (partial remap)

TIM1_REMAP[1:0] =

“11” (full remap)

(1)

0] = “11” (full

remap)

(1)

(1)

TIM1_ETR PA12 PE7
TIM1_CH1 PA8 PE9
TIM1_CH2 PA9 PE11
TIM1_CH3 PA10 PE13
TIM1_CH4 PA11 PE14

TIM1_BKIN PB12
TIM1_CH1N PB13
TIM1_CH2N PB14
TIM1_CH3N PB15

1. Remap available only for 100-pin packages.

2. Remap not available on 36-pin package.

90/501

(2)
(2)
(2)

(2)

PA6 PE15

PA7 PE8
PB0 PE10
PB1 PE12

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

5.3.6 USART Alternate function remapping

Refer to AF remap and debug I/ O configuration register (AFIO_MAPR)

Table 20. USART3 remapping

Alternate function

USART3_REMAP[1:0]

= “00” (no remap)

USART3_REMAP[1:0]
= “01” (partial remap)

(1)

USART3_REMAP[1:0]

= “11” (full remap)

USART3_TX PB10 PC10 PD8
USART3_RX PB11 PC11 PD9

USART3_CK PB12 PC12 PD10
USART3_CTS PB13 PD11
USART3_RTS PB14 PD12

1. Remap available only for 64-pin, 100-pin packages

2. Remap available only for 100-pin packages.

Table 21. USART2 remapping

Alternate functions USART2_REMAP = 0 USART2_REMAP = 1

USART2_CTS PA0 PD3
USART2_RTS PA1 PD4

USART2_TX PA2 PD5
USART2_RX PA3 PD6
USART2_CK PA4 PD7

1. Remap available only for 100-pin packages.

Table 22. USART1 remapping

(2)

(1)

Alternate function USART1_REMAP = 0 USART1_REMAP = 1

USART1_TX PA9 PB6
USART1_RX PA10 PB7

5.3.7 I2C 1 alternate function remapping

Refer to AF remap and debug I/ O configuration register (AFIO_MAPR)

Table 23. I2C1 remapping

Alternate function I2C1_REMAP = 0 I2C1_REMAP = 1

I2C1_SCL PB6 PB8
I2C1_SDA PB7 PB9

1. Remap not available on 36-pin package.

5.3.8 SPI 1 alternate function remapping

Refer to AF remap and debug I/ O configuration register (AFIO_MAPR)

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General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

Table 24. SPI1 remapping

Alternate function SPI1_REMAP = 0 SPI1_REMAP = 1

SPI1_NSS PA4 PA15

SPI1_SCK PA5 PB3
SPI1_MISO PA6 PB4
SPI1_MOSI PA7 PB5

5.4 AFIO register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions .

5.4.1 Event control register (AFIO_EVCR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109876543210

Reserved EVOE PORT[2:0] PIN[3:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved

Bit 7 EVOE Event Output Enable

Set and cleared by software. When set the EVENTOUT Cortex output is connected to the I/O
selected by the PORT[2:0] and PIN[3:0] bits.

Bits 6:4 PORT[2:0]: Port selection

Set and cleared by software. Select the port used to output the Cortex EVENTOUT signal.
000: PA selected
001: PB selected
010: PC selected
011: PD selected
100: PE selected

Bits 3:0 PIN[3:0] Pin selection (x = A .. E)

Set and cleared by software. Select the pin used to output the Cortex EVENTOUT signal.
0000: Px0 selected
0001: Px1 selected
0010: Px2 selected
0011: Px3 selected
...
1111: Px15 selected

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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

5.4.2 AF remap and debug I/O configuration register (AFIO_MAPR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109876543210

PD01_

REMAP

CAN_REMAP

[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

TIM4_

REMAP

TIM3_REMAP

[1:0]

SWJ_

CFG[2:0]

rw rw rw

TIM2_REMAP

[1:0]

TIM1_REMAP

[1:0]

REMAP[1:0]

Bits 31:27 Reserved
Bits 26:24 SWJ_CFG[2:0] Serial Wire JTAG configuration

These bits are set and cleared by software. They are used to configure the SWJ and trace alternate
function I/Os. The SWJ (Serial Wire JT A G) supports JT A G or SWD access to the Cortex deb ug port.
The default state after reset is SWJ ON without trace. This allows JTAG or SW mode to be enabled
by sending a specific sequence on the JTMS / JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: Forbidden

USART3_

Reserved

USART

REMAP

USART

2_

REMAP

I2C1_

1_

REMAP

SPI1_

REMAP

Bits 23:16 Reserved

Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT

This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality.
When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can
be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48- and 64-pin packages
(PD0 and PD1 are available on 100-pinpackages, no need for remapping).

0: No remapping of PD0 and PD1
1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,

Bits 14:13 CAN_REMAP[1:0] CAN Alternate function remapping

These bits are set and cleared by software. They control the mapping of Alternate Functions
CANRX and CANTX.

00: CANRX mapped to PA11, CANTX mapped to PA12
01: Not used
10: CANRX mapped to PB8, CANTX mapped to PB9 (not available on 36-pin package)
11: CANRX mapped to PD0, CANTX mapped to PD1

Bit 12 TIM4_REMAP TIM4 remapping

This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 on 100-pin
packages only.
0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)

Note: TIM4_ETR on PE0 is not re-mapped.

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General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

Bits 11:10 TIM3_REMAP[1:0] TIM3 remapping

These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on
the GPIO ports.
00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
01: Not used
10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)

Note: TIM3_ETR on PE0 is not re-mapped.

Bits 9:8 TIM2_REMAP[1:0] TIM2 remapping

These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and
external trigger (ETR) on the GPIO ports.
00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)

Bits 7:6 TIM1_REMAP[1:0] TIM1 remapping

These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4, 1N to
3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports.

00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13,
CH2N/PB14, CH3N/PB15)
01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7,
CH2N/PB0, CH3N/PB1)
10: not used
11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,
CH2N/PE10, CH3N/PE12)

Bits 5:4 USART3_REMAP[1:0] USART3 remapping

These bits are set and cleared by software. They control the mapping of USART3 CTS, R TS ,CK,TX
and RX alternate functions on the GPIO ports.
00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
10: not used
11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)

Bit 3 USART2_REMAP USART2 remapping

This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS ,CK,TX and RX
alternate functions on the GPIO ports.

0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)

Bit 2 USART1_REMAP USART1 remapping

This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate
functions on the GPIO ports.

0: No remap (TX/PA9, RX/PA10)
1: Remap (TX/PB6, RX/PB7)

Bit 1 I2C1_REMAP I2C1 remapping

This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate
functions on the GPIO ports.
0: No remap (SCL/PB6, SDA/PB7)
1: Remap (SCL/PB8, SDA/PB9)

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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

Bit 0 SPI1_REMAP SPI1 remapping

This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI
alternate functions on the GPIO ports.
0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)

5.4.3 External interrupt configuration register 1 (AFIO_EXTICR1)

Address offset: 0x08
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3)

These bits are written by software to select the source input for EXTIx external interrupt. Refer to

Section 6.2.5: External interrupt/event line mapping on page 103

0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin

5.4.4 External interrupt configuration register 2 (AFIO_EXTICR2)

Address offset: 0x0C
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7)

These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin

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General-purpose and alternate-functi on I/Os (GPIOs and AFIOs) RM0008

5.4.5 External interrupt configuration register 3 (AFIO_EXTICR3)

Address offset: 0x10
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11)

These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin

5.4.6 External interrupt configuration register 4 (AFIO_EXTICR4)

Address offset: 0x14
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15)

These bits are written by software to select the source input for EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin

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RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs)

5.5 GPIO and AFIO register maps

Refer to Table 1 on page 27 for the register boundary addresses.

5.5.1 GPIO register map

Table 25. GPIO register map and reset values

Offset Register

00h

04h

08h

0Ch

10h

14h

18h

313029282726252423222120191817161514131211

CNF

MODE

CNF

MODE

CNF

GPIOx_CRL

Reset value 01000100010001000100010001000100

GPIOx_CRH

Reset value 01000100010001000100010001000100

GPIOx_IDR

Reset value 0000000000000000

GPIOx_ODR

Reset value 0000000000000000

GPIOx_BSRR BR[15:0] BSR[15:0]

Reset value 00000000000000000000000000000000

GPIOx_BRR

Reset value 0000000000000000

GPIOx_LCKR

Reset value 00000000000000000

7

[1:0]

CNF

15

[1:0]

7

[1:0]

MODE

15

[1:0]

6

[1:0]

CNF

14

[1:0]

6

[1:0]

MODE

14

[1:0]

Reserved

Reserved

Reserved

Reserved

5

[1:0]

CNF

13

[1:0]

MODE

5

[1:0]

MODE

13

[1:0]

5.5.2 AFIO register map

CNF

4

[1:0]

CNF

12

[1:0]

MODE

4

[1:0]

MODE

12

[1:0]

CNF
[1:0]

CNF
[1:0]

LCKK

987654321

CNF

2

[1:0]

CNF

10

[1:0]

10

MODE

2

[1:0]

MODE

10

[1:0]

IDR[15:0]l

ODR[15:0]

BR[15:0]

LCK[15:0]

CNF

1

[1:0]

CNF

9

[1:0]

MODE

1

[1:0]

MODE

9

[1:0]

CNF

0

[1:0]

CNF

8

[1:0]

MODE

3

3

[1:0]

MODE

11

11

[1:0]

MODE

0

[1:0]

MODE

8

[1:0]

0

Table 26. AFIO register map and reset values

Offset Register

00h

04h

08h

0Ch

10h

14h

313029282726252423222120191817161514131211

AFIO_EVCR

Reset value 0000000

AFIO_MAPR

Reset value 000 000 00 00000000000

AFIO_EXTICR1

Reset value 0000000000000000

AFIO_EXTICR2

Reset value 0000000000000000

AFIO_EXTICR3

Reset value 0000000000000000

AFIO_EXTICR4

Reset value 0000000000000000

Reserved

SWJ_CFG[2]

SWJ_CFG[1]

SWJ_CFG[0]

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

987654321

10

PORT[2:0] PIN[3:0]

EVOE

PD01_REMAP

EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]

EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]

EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]

EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]

TIM4_REMPA P

CAN_REMAP[1]

CAN_REMAP[0]

TIM3_REMPAP[1]

TIM3_REMPAP[0]

TIM2_REMPAP[1]

TIM2_REMPAP[0]

TIM1_REMPAP[1]

TIM1_REMPAP[0]

USART3_REMAP[1]

USART3_REMAP[0]

USART2_REMAP

USART1_REMAP

I2C1_REMAP

0

SPI1_REMAP

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Interrupts and events RM0008

6 Interrupts and events

6.1 Nested vectored interrupt controller (NVIC)

Features

● 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)

● 16 programmable priority levels (4 bits of interrupt priority are used)

● Low-latency exception and interrupt handling

● Power management control

● Implementation of System Control Registers

The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed b y th e NVIC. For more information
on exceptions and NVIC programming see Chap 5 Exceptions & Chap 8 Nested Vectored
Interrupt Controller of the ARM Cortex™-M3 Technical Reference Manual.

6.1.1 SysTick calibration value register

The SysTick calibration value is fixed to 9000 which allows the generation of a time base of
1ms with the SysTick clock set to 9 MHz (max HCLK/8).

6.1.2 Interrupt and exception vectors

Table 27. Vector table

Type of
priority

Priority

Position

- - - Reserved 0x0000_0000

-3 fixed Reset Reset 0x0000_0004

-2 fixed NMI

-1 fixed HardFault All class of fault 0x0000_000C
0 settable MemManage Memory management 0x0000_0010
1 settable BusFault Pre-fetch fault, memory access fault 0x0000_0014
2 settable UsageFault Undefined instruction or illegal state 0x0000_0018

- - - Reserved

Acronym Description Address

Non maskable interrupt. The RCC
Clock Security System (CSS) is linked
to the NMI vector.

0x0000_0008

0x0000_001C -

0x0000_002B

3 settable SVCall

4 settable Debug Monitor Debug Monitor 0x0000_0030

- - - Reserved 0x0000_0034

5 settable PendSV Pendable request for system service 0x0000_0038

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System service call via SWI
instruction

0x0000_002C

RM0008 Interrupts and events

Table 27. Vector table (continued)

Type of
priority

Priority

Position

6 settable SysTick System tick timer 0x0000_003C

0 7 settable WWDG Window Watchdog interrupt 0x0000_0040

1 8 settable PVD

2 9 settable TAMPER Tamper interrupt 0x0000_0048
3 10 settable RTC RTC global interrupt 0x0000_004C
4 11 settable FLASH Flash global interrupt 0x0000_0050
5 12 settable RCC RCC global interrupt 0x0000_0054
6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0058
7 14 settable EXTI1 EXTI Line1 interrupt 0x0000_005C
8 15 settable EXTI2 EXTI Line2 interrupt 0x0000_0060

9 16 settable EXTI3 EXTI Line3 interrupt 0x0000_0064
10 17 settable EXTI4 EXTI Line4 interrupt 0x0000_0068
11 18 settable DMA_Channel1 DMA Channel1 global interrupt 0x0000_006C
12 19 settable DMA_Channel2 DMA Channel2 global interrupt 0x0000_0070
13 20 settable DMA_Channel3 DMA Channel3 global interrupt 0x0000_0074
14 21 settable DMA_Channel4 DMA Channel4 global interrupt 0x0000_0078
15 22 settable DMA_Channel5 DMA Channel5 global interrupt 0x0000_007C

Acronym Description Address

PVD through EXTI Line detection
interrupt

0x0000_0044

16 23 settable DMA_Channel6 DMA Channel6 global interrupt 0x0000_0080
17 24 settable DMA_Channel7 DMA Channel7 global interrupt 0x0000_0084
18 25 settable ADC ADC gl obal interrupt 0x0000_0088

19 26 settable

20 27 settable

21 28 settable CAN_RX1 CAN RX1 inte rrupt 0x0000_0094
22 29 settable CAN_SCE CAN SCE interrupt 0x0000_0098
23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C
24 31 settable TIM1_BRK TIM1 Break interrupt 0x0000_00A0
25 32 settable TIM1_UP T IM1 Update interrupt 0x0000_00A4

26 33 settable TIM1_TRG_COM

27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC
28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0
29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4

USB_HP_CAN_TXUSB High Priority or CAN TX

interrupts

USB_LP_CAN_
RX0

USB Low Priority or CAN RX0
interrupts

TIM1 Trigger and Commutation
interrupts

0x0000_008C

0x0000_0090

0x0000_00A8

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Interrupts and events RM0008

Table 27. Vector table (continued)

Position

Type of
priority

Priority

Acronym Description Address

30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8
31 38 settable I2C1_EV I
32 39 settable I2C1_ER I
33 40 settable I2C2_EV I
34 41 settable I2C2_ER I

2

C1 event interrupt 0x0000_00BC

2

C1 error interrupt 0x0000_00C0

2

C2 event interrupt 0x0000_00C4

2

C2 error interrupt 0x0000_00C8
35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC
36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0
37 44 settable USART1 USART1 global interrupt 0x0000_00D4
38 45 settable USART2 USART2 global interrupt 0x0000_00D8
39 46 settable USART3 USART3 global interrupt 0x0000_00DC
40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0
41 48 settable RTCAlarm RTC alarm through EXTI line interrupt 0x0000_00E4

42 49 settable USBWakeup

USB wakeup from suspend through
EXTI line interrupt

0x0000_00E8

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