ST STi7200 User Manual

STi7200

Triple display, HDTV set-top box, dual decoder for H.264 and VC-1

Data brief

Features

■ Single-chip, high-definition STB decoder:

– H.264 and Microsoft –Linux

, Windows® CE and OS21

compatible ST40 CPU core

– Supports NAND flash, NOR flash and

Sflash – Local memory 2 × DDR2 333 MHz – Transport filtering and descrambling – Dual H.264, MPEG-2, VC-1 video decoding – SVP compliant – Windows

DRM support – Triple display composition – Integrated VHF channel 3/4 modulator – Dual audio decoder, including Windows

Media

Audio 9 (WMA-9) and WMA-9 Pro

– DVD data retrieval and decryption

ST40 core

UDI

MMU

16 K Icache

Int. control

32 K Dcache

LMI0

DDR2

SDRAM

LMI1

VC-1 compatible

MII/RMII for 100BT

Ethernet

Hard

disks

3×

USB

2.0

2×

Ethernet MII/RMII

2×

FDMA

2×

SATA

PCM out 1

PCM in

Audio

interfaces

– HD DVD/BD compliant – DVR capable – HDMI/HDCP interface with CEC line

– IQI (Image Quality Improvement) support

■ Connectivity:

– Triple USB 2.0 host controller/ PHY

– Digital audio and video auxiliary inputs – Low-cost modem support – Dual 100BT ethernet controller, MAC and

– Du a l s e r i a l ATA ( S ATA ) – High speed synchronous interface (MPX)

PCM out 2

analog out 1

analog out 2

S/PDIF

Stereo

DACs

controller

interface

MII/RMII interface for external PHY

to STVi498 cable and DOCSIS front-end chip

Peripheral I/O

and external interrupts

8×

GPIO

2× IR

Tx/Rx

interface

ILC

MAFE

4×

UARTs

Audio

decoder

ST231

core

Audio

decoder

ST231

core

2×

SmartCard

interface

2×

DISEqC

PWM

5×

SSCs

STBus

PTI 1

SECTP

TS inputs

Descrmblr

TSG DMA in

TSG DMA out

Clock generator

PTI 2

and system

services

Video decoder

VC-1 (inc WMV-9)

H264/MPEG-2

ST231

core

Video decoder

VC-1 (inc WMV-9)

H264/MPEG-2

ST231

core

DVP

2D gamma

blitter

HDMI

VHF

Local

mod

DACs

Local video

DV out

output (HD)

HDMI

DV i n

VHF

DAC

CH 3/4

out

Display

compositor

mix 1 to 3

Local

TLTXT

DENC

Local video output (SD)

DACs

Flex VPE

HD disp proc

Remote

TLTXT

DACs

DENC

Remote video

output (SD)

DV out

EMI

EMPI

Flash or companion

chip

February 2011 Doc ID 12876 Rev 2 1/4

www.st.com

Description STi7200

1 Description

The STi7200 is a new generation, high-definition set-top box/DVD decoder chip that provides very high performance for low-cost HD systems. With enhanced performance over the STi7109, it includes both Windows Media Video 9 and H.264 video decoders for new, low bitrate applications. The STi7200 is able to decode two HD programs.

Based on the STBus architecture, this system-on-chip is a full back-end processor for digital terrestrial, satellite, cable and IP high-definition set-top boxes, compliant with ATSC, SMPTE VC-1, DVB, DIRECTV, DCII, OpenCable and ARIB BS4 specifications. The STi7200 includes all processing for DVD applications.

2 Applications

The STi7200 demultiplexes, decrypts and decodes HD or SD video streams with associated multichannel audio. Video is output to three independently formatted displays:

● a full resolution display intended for a local HDTV monitor

● a downsampled display intended for a VCR or local SDTV

● an SD resolution display intended for a remote SDTV monitor

Connection to the main TV or display panel can be analog (RGB/YUV) through HD DACs, or digital through a copy protected DVI/HDMI. Composite outputs are provided for connection to local and remote TVs or VCR with Rovi™ or Dwight Cavendish protection.

Audio is output with optional PCM mixing to an S/PDIF interface, dual PCM interface, or through integrated dual stereo audio DACs.

Digitized analog programs can also be input to the STi7200 for reformatting and display.

The STi7200 includes a graphics rendering and display capability with a 2D graphics accelerator. A triple display compositor mixes graphics and video with independent composition for each of the TV and VCR or SDTV outputs. Picture In Picture (PIP) is supported.

The STi7200 handles up to six external transport streams from different sources.

Four transport stream inputs, two transport stream input/outputs and two transport stream outputs are supported. Applications include DVR time-shifted viewing of a terrestrial program, while acquiring an EPG/data stream from a satellite or cable front end.

The transport architecture uncouples the transport packet processing from the transport packet collection. The input transport streams are stored in SDRAM after PID filtering and time stamp collection. DMAs fetch data from external memory and inject them to PTIs or transport stream output ports.

The flexible descrambling engine is compatible with required standards including DVB, DES, AES and Multi2.

The STi7200 has an ST40-210 CPU for applications and device control. A dual 32-bit DDR2 SDRAM interface provides the required bandwidth for dual HD VC-1/H.264 video decoding, and for the CPU and the rest of the system.

2/4 Doc ID 12876 Rev 2

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