ST STi7167 User Manual

STi7167

Advanced STB decoder with inte grated DVB-T/DVB-C demodu lator

Data brief

Features

■ Integrated DVB-C or DVB-T demodulator

– User-selectable mode
– Compatible with low to high IF tuners
– Flexible clock management
– ADC for RF signal strength indicator

■ Advanced high-definition video decoding

(H264/VC-1/MPEG2)

■ Advanced standard-definition video decoding

(H264/VC-1/MPEG2/AVS)

■ Advanced multichannel audio decoding

(MPEG 1, 2, MP3, DD/DD+, AAC/AAC+,
WMA9/WMA9Pro)

■ Linux, Windows CE and OS21 compatible

ST40 applications CPU (450 MHz)

Resets Analog out

JTAG

Clocks
Modes

PCM I/O
S/PDIF out External interrupts

■ 32-bit DDR1/DDR2 compatible local memory

interface

■ Multi-stream, DVR capable transport stream

processing

■ Extensive connectivity (dual USB hosts,

e-SATA (optional), Ethernet MAC/MII/RMII and
PCI)

■ Advanced security and DRM support including

SVP, MS-DRM and DTCP-IP

Description

The STi7167 uses state-of-the-art process
technology to provide a fully featured HD AVC,
DVB-C, and DVB-T demodulator/decoder IC.

It is a highly integrated system-on-chip, suitable
for STB markets across cable, terrestrial, and
terrestrial/IP hybrid networks worldwide.

STB peripherals I/O

CPU/FPU

ST40 450MHz

MMU
Interrupts
I cache
D cache
Timer
Debug

Transport
Security

Dual PTI
TS merger

Transport streams
Parallel/serial in/out

Clock Gen
System serv

Dual FDMA

Bdisp Blitter

Video decoder

ST231 CPU
Delta Mu

Demodulator

DVB-T
DVB-C

streams

IF inTransport

Audio I/O

PCM players
PCM reader
DACs

Audio decoder

ST231 CPU

STBus

Display

Video planes
Graphic planes
Cursor plane
Main VDP
Aux VDP
Deinterlacer
Capture

Peripherals

SSC
UART
MAFE
PWM
Infrared
Smartcard

Video I/O

DVOs
Denc
Teletext
DACs
HDMI
VTGs
DVP

Digital video HD/SD in/out
Analog video HD/SD out

System

interfaces

EMI
PCI
SPI
LMI

Connectivity

Flash, SFlash

Flash, SFlash
NOR, NAND

NOR, NAND

PCI Peripherals

Serial Flash

DDR1/DDR2

Memory

USB

e-SATA

Ethernet

DAA

August 2009 Doc ID 15836 Rev 2 1/10

For further information contact your local STMicroelectronics sales office.

www.st.com

10

Introduction STi7167

1 Introduction

The STi7167 is targeted at the latest Operator and CE manufacturer requirements for STBs
that use advanced HD decoding (H264/VC-1/MPEG2), and which conform to DVB, ISMA,
ATIS-IIF, SCTE, ATSC, ARIB, CEA, ITU, OpenCable and MSTV specifications.

The STi7167 provides a solution for operators to specify a range of low-cost, high
performance HD STBs including low-cost zappers, IP clients, interactive STBs, DVR
standalone and DVR server/home network-capable STBs, and with content delivery
possible using broadcast or broadband networks, or both (hybrid STBs). The STi7167 keeps
pace with the latest conditional access, DRM and trusted platform requirements of major
operators worldwide by incorporating the latest generation of advanced security features.

The STi7167 offers current users of ST’s growing family of advanced decoding ICs
enhancements in performance and features, while reducing cost and time-to-market for the
next generation deployments.

Features Benefits

Combines a configurable DVB-C/DVB-T
demodulator with STB decoding and displ ay
functions

ST40-300 applications CPU @450MHz,
32K I cache, 32K D cache

STMicroelectronics' DELTA video decoding
system with ST231 processor

Dual USB 2.0 hosts, optional e-SATA,
Ethernet MAC with MII/RMII and TMII,
PCI

Low power process, design and architecture Best in class, low power standby mode, to meet

Advanced 2D graphics and display subsystem
which also supports 3D user interface effects
and 1080p60 display output

This highly integrated SoC helps to reduce board
area and manufacturing cost, allowing low cost and
small size STBs to be d esigned for eithe r DVB-C or
DVB-T networks

Up to 800DMIPs superscalar performance from a
single CPU core, using standard tools and
operating systems (Linux, OS21)

Decoding of advan ced high defini tion st andards fo r
MPEG2, H264, VC-1 broadcast, with the
performance and flexibility for web-based content
decoding such as Flash, DivX , MJPEG and Real

Extensive high speed connectivity for the widest
range of STB peripherals, such as Flash drives,
external HDDs, home network controllers (for
example MoCA, Wi-Fi), DOCSIS modem and so
on

emerging energy standar ds for STBs. Dynamic
configuration of power to individual sub-systems
enables power-efficient active standby modes

Allows visually ap pealing u ser in terfaces and video
rich navigation to be offered to consumers, while
high quality progressive output can be watched on
the latest high definition displays

2/10 Doc ID 15836 Rev 2

STi7167 Introduction

1.1 STi7167 feat ur es summary

The STi7167 has the following main features:

● DVB-T demodulator

● General features:

– Wide-range carrier tracking loop for large offsets recovery
– Dual ADC for IQ baseband interface
– Dual SD digital split AGC for RF and IF/BB
– Gain control

● Channel impairments management:

– Nordig Unified (v2.0) compliant
– DTG 5.0 and Dig iten ne co mpl iant
– Built-in channel reception quality indicators
– Out-of-guard interval echoes compatible
– Impulsive noise rejection capa ble
– Outstanding adjacent and co-channel rejection capability with integrated and

flexible digital channel filtering

– High-performance digital carrier, timing and symbol recovery loops

● Decoding capabilities:

– ETSI EN-300744 v1.5.1 compatible
– 2-K and 8-K FFT
– 6, 7 and 8 MHz channel bandwidths
– 1/4, 1/8, 1/16, 1/32 guard-interval length
– QPSK - 16QAM - 64QAM modulations
– Hierarchical modulation capability
– TPS decoding
– Puncture rates are 1/2, 2/3, 3/4, 5/6, 7/8
– Outer Reed-Solomon decoder as per DVB-T standard
– Ene rgy dis persal descrambler

● DVB-C demodulator

● Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams

– High-performance integrated ADC for direct IF architecture in all QAM modes
– Supports 16, 32, 64, 128 and 256 point constellations
– Variable symbol rates
– Front derotator for better low symbol rate performance and relaxed tuner

constraints
– Integrated matched filtering
– Robust integrated adaptive pre- and post- high multi-tap equalizer
– On-chip FEC A/C with ability to bypass individual blocks
– Fast signal acquisition

● ST40-300, dual-issue applications CPU with 32KI, 32KD caches; Target speed

450 MHz delivering 800 DMIPs
– Includes a tightly coupled vector FPU to accelerate 3D graphics transformations

Doc ID 15836 Rev 2 3/10