ST STi5167 User Manual

Low-cost interactive set-top box with advanced features
Features
Enhanced ST20 32-bit VL-RISC CPU
– up to 133 MHz, 16-bit wide SDR SDRAM, – up to 166 MHz, 16-bit wide DDR SDRAM
Programmable Flash memory interface
Demodulator compatible with I and Q or IF
inputs for tuner interface
Channel management
Digital carrier, timing & symbol recovery loops
Decoding
– QPSK - 16 QAM - 64 QAM constellations
MPEG-2 MP@ML video decoder
Graphics and display
– 3 display planes – 2D paced blitter engine with fill function
Programmable transport interface (PTI)
– single transport stream input for DVB
Central DMA controller
STi5167
Data Brief
Advanced security ready
– compatible with latest CA requirement
PAL/NTSC/SECAM encoder
– RGB, CVBS, Y/C and YUV outputs with four
10-bit DAC outputs.
Audio subsystem
– simultaneous MPEG audio decode and
output of Dolby streams on S/PDIF
– IEC958/IEC1937 digital audio output
interface
– inte grated stereo audio DAC
On-chip peripherals
– ASC (UART) with Tx and Rx FIFOs – 3 banks of 8-bit programmable I/O – integrated VCXO
JTAG/TAP interface
Package
– 15 mm x 15mm PBGA 240 0.8 mm pitch
NOR
FLASH 16
FMI + SPI
2x
SSC
Comms block
ST20 C1 core 200 MHz
DCU
4K SRAM
IF
COFDM
4K ICache
Int controller
4K DCache
PTI
DVB/ICAM/DES
TS merger
TS in
DDR/SDR
SDRAM
16
LMI
Audio
decoder
STBus Interconnect
FDMA
Audio output
AudioL/R
S/PDIF
Audio DACs
PCM + S/PDIF
player
Video output
RGB/YC/CVBS
DENC DVO
BDISP
PIO
GDMA
8KB TILE
IR Rx
16
Comms peripherals
Digital video
LCMPEG2
2x ASC (UART)
April 2009 Rev 3 1/8
For further information contact your local STMicroelectronics sales office.
www.st.com
8
Description STi5167

1 Description

1.1 General

The STi5167 is the latest in the family of STBus set-top box ICs providing high-performance, low-cost system-on-chip (SoC) for MPEG processing in digital terrestrial STBs. It is derived from the STi5107, with the addition of a DVB-T COFDM demodulator and supports multiple platforms using a unified architecture. STi5167 is compatible with the latest CA advanced security specifications.
The STi5167 delivers enhanced performance with respect to previous devices. Main memory is based upon a single 16-bit external SDR or DDR SDRAM.
The display architecture of the devices is based upon a high performance blitter engine that supports CLUT8 and RGB16STi5167 formats for background, video and OSD/graphics displays. It makes the porting of middleware easier with improved rendering.

1.2 Application

Figure 1. Terrestrial pay-TV receiver

IR Rx SDR/ DDR
RGB or YC+CVBS
Tuner
STi5167
DVB-T Rx
Smart Card
Smart
Card
CVBS
VCR
Flash
The STi5167 is designed for CA applications with embedded HW security. Its BGA package allows the use of a simple 2-layer PCB, with all signals and power supplies
being routed through the top PCB layer. This leaves the bottom PCB layer dedicated to the ground plane and JTAG connections.
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STi5167 Description
To reduce the system pin complexity, the following conditions apply:
either SDR and DDR SDRAM memory interface available
serial or parallel Flash interfaces for program storage (HW selection for serial or
parallel Flash boot)
FMI interface with NAND Flash support
serial TS input port
two UARTs
two smart card interfaces
HW secu rity support option
digital video output port (exclusive with other features)
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