STi5105
High-performance advanced SD decoder for set-top box
Data Brief
Features
■ Enhanced ST20 32-bit VL-RISC CPU
– 200 MHz, single cycle cache, 4 Kbyte
instruction cache, 4 Kbyte data cache, 2
Kbyte SRAM
■ Unified memory interface
– Up to133 MHz,16-bit wide DDR interface
■ Programmable flash memor y inte rfac e
– SRAM, peripheral, Flash, SFlash™ support
– Sup port for low-c os t DVB-CI and ATAPI
■ Programmable transport interface (PTI)
– Single transport stream input
– Support for DVB transport streams
– Integ ra ted DVB , ICAM descr am bl ers
■ MPEG-2 MP@ML video decoder
– Fully programmable horizontal and vertical
SRCs
■ Graphics/display
– Advanced blitter base compositor
– 8 bpp CLUT graphics, 256 x 30 bits
(AYCbCr) CLUT entries
– 16 bpp true color graphics, RGB565,
ARGB1555, ARGB4444 formats with link-list
control
– Alp ha ble ndi ng, anti alia si ng, antif lu tter,
antiflicker filters
– 2D paced blitter engine with fill function
■ PAL/NTSC/SECAM encoder
– RGB, CVBS, Y/C and YUV outputs with four
10-bit DAC outputs. RGB/CVBS or
YUV/CVBS or YC/CVBS
– Encoding of CGMS, Teletext, WSS, VPS,
close caption
■ Audio subsystem
– MPEG-1 layers I/II
– Simultaneous MPEG audio decode and
output of Dolby streams on S/PDIF
– IEC958/IEC1937 digital audio output
interface
– Integrated stereo audio DAC system
■ Central DMA controller
■ On-chip peripherals
– Two ASCs (UARTs) with Tx and Rx FIFOs
– Three 8-bit banks of parallel I/O and one 7-
bit bank
– One sm ar tca rd inter fac e and cloc k
generator
– Two SSCs for I²C/SPI master/slave
interfaces
– Infrared transmitter/receiver
– Integrated VCXO
– Low-power/RTC/watchdog controller
■ JTAG/TAP interface
■ Package 24 mm x 24 mm LQFP216 or
23 mm x 23 mm BGA.
STV0299
and STB6000
STV0299
tuner
and STV6110A
tuner
STV0297
QAM demodulator
STV0297
+ tuner
QAM demodulator
+ tuner
STV0360
COFDM
STV0360
+ tuner
COFDM
+ tuner
DRAM
stream in
OR
Transport
Smart
card
IR
RX/TX
Audio
buffer
STi5105
Video
buffer
NOR
Flash
November 2008 Rev 1 1/5
For further information contact your local STMicroelectronics sales office.
www.st.com
5
Description STi5105
1 Description
STMicroelectronics sets a new standard for performance, price and integration in the single
chip MPEG-2 set-top box decoder market with the introduction of the STi5105.
This highly integrated solution targets mass market STBs, offers increased performance
over earlier devices, and includes many features to further reduce costs, including a unified
memory architecture.
The STi5105 features the ST20 CPU that is standard across the OMEGA range but boosts
the clock speed to 200 MHz which, when combined with the 2D graphics engine, gives the
new device outstanding graphics performances.
Targeting low-cost, single tuner STB applications, the STi5105’s DDR memory interface
both reduces system costs and minimizes overall system latency, ensuring the new device
can support the most demanding interactive TV applications and middlewares.
The integration of VCXO and audio DACs ensures that manufacturers using the STi5105
cut their bill of materials and significantly simplify board design and assembly.
STi5105 is supplied in either 24 mm x 24 mm LQFP216 or 23 mm x 23 mm BGA package.
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STi5105 Ordering information
2 Ordering information
Table 1. Ordering information
Order code Packaging
STi5105ALC 24 mm x 24 mm LQFP216
STi5105AYC 23 mm x 23 mm BGA
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Revision history STi5105
3 Revision history
Table 2. Document revision history
Date Revision Changes
24-Nov-08 1 Initial release
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STi5105
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