ST STHV748 User Manual

STHV748

Quad ± 90 V, ± 2 A, 3/5 levels, high speed ultrasound pulser

Features

■0 to ±90 V output voltage

■Up to 20 MHz operating frequency

■Embedded low-power, floating high-voltage drivers (external voltage rails can be also used)

■Mode operations:

–3/5-levels output waveform

–±2 A source and sink current

–Down ≤20 ps jitter

–Anti-cross conduction function

–Low 2nd harmonic distortion

■Fully integrated clamping-to-ground function

–8 Ω synchronous active clamp

–Anti-leakage on output node

■Dedicated half bridge for continuous wave (CW) operations

–≤0.1 W power consumption

–±0.6 A source and sink current

–≤10 ps jitter

■Fully integrated T/R switch

–13.5 Ω on resistance

–HV MOS topology to minimize current consumption

–Up to 300 MHz BW

–Receiver multiplexing function

■2.4 V to 3.6 V CMOS logic interface

■Auxiliary integrated circuits

–Noise blocking diodes

–Fully self-biasing architecture

–Anti-memory effect for all internal HV nodes

–Thermal protection

–Standby function

■Latch-up free due to HV SOI technology

■Very few external passive components needed

Datasheet — production data

QFN64 9 x 9 x1.0 mm

Applications

■Medical ultrasound imaging

■Pulse waveform generator

■NDT ultrasound transmission

■Piezoelectric transducers driver

Description

This monolithic, high-voltage, high-speed pulser generator features four independent channels. It is designed for medical ultrasound imaging applications, but it can also be used for driving other piezoelectric, capacitive or MEMS based transducers. The STHV748 comprises a controller logic interface circuit, level translators, MOSFET gate drivers, noise blocking diodes, and high-power P-channel and N-channel MOSFETs as the output stage for each channel, clamping- to-ground circuitry, anti-leakage, anti-memory effect block, thermal sensor, and a T/R switch which guarantees an effective decoupling during the transmission phase. Moreover, the STHV748 includes self-biasing and thermal shutdown blocks. Each channel can support up to five active output levels with two half bridges. The output stage of each channel is able to provide ±2 A peak output current. In order to reduce power dissipation during continuous wave mode, a dedicated half bridge is available and the peak current is limited to 0.6 A.

Table 1.	Device summary
Order code		Package	Packaging
STHV748QTR		QFN64	Tape and reel

May 2012

Doc ID 15450 Rev 4

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This is information on a product in full production.

www.st.com

Contents	STHV748

Contents

1	Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		4
	2.1	Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
	2.2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
	2.3	Additional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
3	Truth table and single channel block description . . . . . . . . . . . . . . . . .		8
4	Power-up / Power-down voltage sequence . . . . . . . . . . . . . . . . . . . . . . .		9
5	Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	5.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
6	Operating supply voltages and average currents . . . . . . . . . . . . . . . .		11
	6.1	Digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	6.2	Output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
7	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
8	Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
9	Oscilloscope acquisitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
10	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24
11	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27

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STHV748	Typical application circuit

1 Typical application circuit

Figure 1. Typical application circuit

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Pin settings	STHV748

2 Pin settings

2.1Connection

Figure 2. Pin connection (top view)

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2.2Description

Table 2.		Pin description (P = power, A = analog, D = digital)
Pin N		Name	Function	IN/OUT	Type
1		AGND	Signal ground	I	A
2		REF_HVM1	Supply for low side 1 gate driver	I	P
3		HVM1_A	Negative high-voltage supply 1 channel A	I	P
4		HVM0_A	Negative high-voltage supply 0 channel A	I	P
5		HVOUT_A	Channel A, high-voltage output before noise blocking	O	P
			diodes
6		HVP0_A	Positive high-voltage supply 0 channel A	I	P
7		REF_HVP1	Supply for high side 1 gate driver	I	P
8		HVP1_A	Positive high-voltage supply 1 channel A	I	P
9		HVP1_B	Positive high-voltage supply 1 channel B	I	P
10		REF_HVP0	Supply for high side 0 gate driver	I	P
11		HVP0_B	Positive high-voltage supply 0 channel B	I	P

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STHV748	Pin settings

Table 2. Pin description (P = power, A = analog, D = digital) (continued)

	Pin N	Name	Function	IN/OUT	Type
	12	HVOUT_B	Channel B, high-voltage output before noise blocking	O	P
			diodes
	13	HVM0_B	Negative high-voltage supply 0 channel B	I	P
	14	HVM1_B	Negative high-voltage supply 1 channel B	I	P
	15	REF_HVM0	Supply for low side 0 gate driver	I	P
	16	D_CTR	Delay control	I	A
	17	IN4	Input signal shared	I	D
	18	IN1_B	Input signal channel B	I	D
	19	IN2_B	Input signal channel B	I	D
	20	IN3_B	Input signal channel B	I	D
	21	VDDP	Positive low-voltage supply	I	A
	22	GND_PWR	Power ground	I	P
	23	XDCR_B	Channel B, high-voltage output	O	P
	24	LVOUT_B	Channel B, low-voltage output	O	A
	25	LVOUT_C	Channel C, low-voltage output	O	A
	26	XDCR_C	Channel C, high-voltage output	O	P
	27	GND_PWR	Power ground	I	P
	28	VDDM	Negative low-voltage supply	I	A
	29	IN3_C	Input signal channel C	I	D
	30	IN2_C	Input signal channel C	I	D
	31	IN1_C	Input signal channel C	I	D
	32	THSD	Thermal shutdown pin	I/O	D
	33	AGND	Signal ground	I	A
	34	REF_HVM1	Supply for low side 1 gate driver	I	P
	35	HVM1_C	Negative high-voltage supply 1 channel C	I	P
	36	HVM0_C	Negative high-voltage supply 0 channel C	I	P
	37	HVOUT_C	Channel C, high-voltage output before noise blocking	O	P
			diodes
	38	HVP0_C	Positive high-voltage supply 0 channel C	I	P
	39	REF_HVP1	Supply for high side 1 gate driver	I	P
	40	HVP1_C	Positive high-voltage supply 1 channel C	I	P
	41	HVP1_D	Positive high-voltage supply 1 channel D	I	P
	42	REF_HVP0	Supply for high side 0 gate driver	I	P
	43	HVP0_D	Positive high-voltage supply 0 channel D	I	P
	44	HVOUT_D	Channel D, high-voltage output before noise blocking	O	P
			diodes

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Pin settings	STHV748

Table 2. Pin description (P = power, A = analog, D = digital) (continued)

Pin N	Name	Function	IN/OUT	Type
45	HVM0_D	Negative high-voltage supply 0 channel D	I	P
46	HVM1_D	Negative high-voltage supply 1 channel D	I	P
47	REF_HVM0	Supply for low side 0 gate driver	I	P
48	DGND	Logic ground	I	A
49	DVDD	Positive logic supply	I	A
50	IN1_D	Input signal channel D	I	D
51	IN2_D	Input signal channel D	I	D
52	IN3_D	Input signal channel D	I	D
53	VDDP	Positive low-voltage supply	I	A
54	GND_PWR	Power ground	I	P
55	XDCR_D	Channel D, high-voltage output	O	P
56	LVOUT_D	Channel D, low-voltage output	O	A
57	LVOUT_A	Channel A, low-voltage output	O	A
58	XDCR_A	Channel A, high-voltage output	O	P
59	GND_PWR	Power ground	I	P
60	VDDM	Negative low-voltage supply	I	A
61	IN3_A	Input signal channel A	I	D
62	IN2_A	Input signal channel A	I	D
63	IN1_A	Input signal channel A	I	D
64	INT_BIAS	Enable internal supply generators	I	D
Exposed-Pad		Substrate	I	P

2.3Additional pin description

The INT_BIAS pin enables the internal reference generators. With INT_BIAS=DVDD, the STHV748 internally generates the reference voltages on REF_HVP1/0 (pin - 7, 10, 39, 42) and REF_HVM1/0 (pin - 2, 15, 34, 47). These voltages are set at VDDP below HVP and respectively at:

●REF_HVM# = HVM# + VDDP

●REF_HVP# = HVP# - VDDP

After enabling INT_BIAS, a period of time is needed to charge the external reference capacitors (about 30 µs in a typical application).

Should INT_BIAS=DGND, it is necessary to apply an external voltage reference to the REF_HVM# and REF_HVP# pins.

THSD is a thermal flag. Being the output stage of the THSD a Nch-MOS open-drain, an external pull-up resist or (Rp≥10 kΩ) connected to a positive low-voltage supply (see Figure 1) is required. If the internal temperature surpasses 153 °C, THSD goes down and all STHV748 channels are in HZ state. The thermal protection can be disabled, by connecting

6/28	Doc ID 15450 Rev 4

STHV748	Pin settings

the THSD pin to a positive low voltage supply. THSD can be also shared among several STHV748 on the same PCB.

D_CTR can be used to optimize 2nd HD performances by tuning the fall propagation delay (tdf - see Table 9). If D_CTR is equal to ground, tdf has the nominal value. If D_CTR is varied from 2 V to 4.2 V, tdf can be changed from -1 ns to +600 ps with respect to the nominal value.

The exposed-pad is internally connected to the substrate of the package. It can be either left floating or connected to a ground via 100 V capacitance toward ground, in order to reduce the noise during the receiving phase.

Figure 3. Typical application with INT_BIAS shorted to ground.

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Truth table and single channel block description	STHV748

3 Truth table and single channel block description

Figure 4. Single channel block description

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Table 3.			Truth table for one channel
Global			Per channel			State			Switches internal state
THSD		IN4	IN3	IN2	IN1		S0	S1	S2	S3	S4	S5	S6	S7	S8	S9
1		x	x	0	0	Clamp	0	0	0	0	0	0	1	0	1	0
1		0	0	0	1	HVM0	0	1	0	0	0	0	0	0	1	0
1		0	0	1	0	HVP0	1	0	0	0	0	0	0	0	1	0
1		x	0	1	1	T/R SW	0	0	0	0	0	0	1	1	0	1
1		0	1	0	1	HVM1	0	0	0	1	0	0	0	0	1	0
1		0	1	1	0	HVP1	0	0	1	0	0	0	0	0	1	0
1		0	1	1	1	HZ	0	0	0	0	0	0	0	0	1	0
1		1	1	1	1	T/R SW	0	0	0	0	0	0	1	1	0	1
1		1	0	0	1	Max. HVM0 and HVM1	0	1	0	1	0	0	0	0	1	0
1		1	0	1	0	Max. HVP0 and HVP1	1	0	1	0	0	0	0	0	1	0
1		1	1	0	1	CW HVM1	0	0	0	0	0	1	0	0	1	0
1		1	1	1	0	CW HVP1	0	0	0	0	1	0	0	0	1	0
0		x	x	x	x	HZ	0	0	0	0	0	0	0	0	1	0

8/28	Doc ID 15450 Rev 4

STHV748	Power-up / Power-down voltage sequence

4 Power-up / Power-down voltage sequence

During the power up/power down phases,the following relationship must be always respected:

●VDDP >= DVDD

●HVM0 <= HVM1

●HVP0 >= HVP1

It is recommended to power up the low voltage supplies before the high voltage supplies.

Doc ID 15450 Rev 4

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