ST STHDLS101A User Manual

STHDLS101A

Enhanced AC coupled HDMI level shifter with configurable HPD output

Features

■Converts low-swing alternating current (AC) coupled differential input to high-definition multimedia interface (HDMI) rev 1.3 compliant

■HDMI level shifting operation up to 2.7 Gbps per lane

■Integrated 50 Ω termination resistors for ACcoupled differential inputs

■Input/output transition minimized differential signaling (TMDS) enable/disable

■Output slew rate control on TMDS outputs to minimize electromagnetic interference (EMI) and eliminate external components such as RC and choke

■Fail safe outputs for backdrive protection

■No re-timing or configuration required

■Inter-pair output skew < 250 ps, intra-pair output skew < 10 ps

■Single power supply of 3.3 V

■ESD protection: ±6 KV HBM on all I/O pins

■Integrated display data channel (DDC) level shifters. Pass-gate voltage limiters allow 3.3 V termination on graphics and memory controller hub (GMCH) pins and 5 V DDC termination on HDMI connector pins

■Level shifter and configurable output for HPD signal from HDMI/DVI connector

■Integrated pull-down resistor on HPD_SINK and OE_N inputs

Applications

■Notebooks, PC motherboards and graphic cards

Table 1. Device summary

QFN48

(7 x 7 mm)

Description

The STHDLS101A is a high-speed high-definition multimedia interface (HDMI) level shifter that converts low-swing AC coupled differential input to HDMI 1.3 compliant open-drain current steering RX-terminated differential output. Through the existing PCI-E pins in the graphics and memory controller hub (GMCH) of PCs or notebook motherboards, the pixel clock provides the required bandwidth (1.65 Gbps, 2.25 Gbps) for the video supporting 720p, 1080i, 1080p with a total of 36-bit resolution. The HDMI is multiplexed onto the PCIe pins in the motherboard where the AC coupled HDMI at 1.2 V is output by GMCH. The AC coupled HDMI is then level shifter by this device to 3.3 V DC coupled HDMI output.

The STHDLS101A supports up to 2.7 Gbps, which is enough for 12-bits of color depth per channel, as indicated in HDMI rev 1.3.

The device operates from a single 3.3 V supply and is available in a 48-pin QFN package.

	Order code	Package	Packing
	STHDLS101AQTR	QFN48	Tape and reel
		(7 x 7 x 1 mm)
	June 2009	Doc ID 15756 Rev 1	1/24
			www.st.com

Contents	STHDLS101A

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		4
3	Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	3.1	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
4	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
5	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	5.1	Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

5.1.1 Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	6.1	Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	6.2	Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	6.3	Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
7	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23

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STHDLS101A	Block diagram

1 Block diagram

Figure 1. STHDLS101A block diagram

	0V
VCC33		OUT_D4+
	50Ω±10%	OUT_D4-
IN_D4+
	RX
IN_D4-
OE_N		10mA current
	0V	driver
		OUT_D3+
	50Ω±10%	OUT_D3-
IN_D3+
	RX
IN_D3-
		10mA current
	0V	driver
		OUT_D2+
	50Ω ±10%	OUT_D2-
IN_D2+
	RX
IN_D2-
		10mA current
	0V	driver
		OUT_D1+
	50Ω±10%	OUT_D1-
IN_D1+
	RX
IN_D1-
REXT
		10mA current
		driver
	HPD level	shifter
HPD_SOURCE	HPD	HPD_SINK
DDC_EN		160K
SCL_SOURCE		SCL_SINK
SDA_SOURCE		SDA_SINK

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System interface	STHDLS101A

2 System interface

Figure 2. System inferface

	0#) %XPRESS
	3$6/
'RAPHICS CHIPSET	($-)	,EVEL SHIFTER
			($-) OUTPUTO
'-#( ON(THE
				CONNECTOR
MOTHERBOARD		34($,3 !

!-6

Figure 3. Cable adapter

($-) $6)

$ONGLE OR CABLE ADAPTER

34($,3 !

$0

!-6

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STHDLS101A	System interface

Figure 4. DP to HDMI/DVI cable adapter

	HPD	DP Connector	HPD_SOURCE		HPD_SINK	HDMI/DVIConnector
HDMI/DVI
					DC TMDS
Transmitter	AC_TMDS		AC_TMDS	STHDLS101A
				HDMI/DVI Cable
	DDC		DDC	Adaptor	DDC
PC chipset
						!-6

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Pin configuration	STHDLS101A

3 Pin configuration

Figure 5. STHDLS101A pin configuration

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6/24	Doc ID 15756 Rev 1

STHDLS101A	Pin configuration

3.1Pin description

Table 2.	Pin description
Pin	Name	Type		Function
number
1	GND	Power	Ground
2	VCC33	Power	3.3 V±10% DC supply
			Function pins are to enable vendor-specific features or
		Vendor-specific	test modes. For normal operation, these pins are tied to
3	FUNCTION1		GND or VCC33
		control or test	For consistent interoperability, GND is the preferred
		pins
			default connection for these signals. Provides equalizer
			6dB lift at high frequencies
			Function pins are to enable vendor-specific features or
			test modes
		Vendor-specific	For normal operation, these pins are tied to GND or
4	FUNCTION2	control or test	VCC33
		pins	For consistent interoperability, GND is the preferred
			default connection for these signals. Provides 5 dB
			equalizer gain at all frequencies
5	GND	Power	Ground
			Connection to external resistor. Resistor value
			specified by device manufacturer.
			Acceptable connections to this pin are:
6	REXT	Analog	– Resistor to GND
			– Resistor to 3.3 V
			– NC (direct connections to VCC or GND are through a
			0 Ω resistor for layout compatibility
			Buffer from the 0 V to 5 V input signal. The output
			buffer stage is configurable based on the FUNCTION3
			pin settings as desribed in the table below:
			FUNCTION3	HPD_SINK		HPD_SOURCE
						Open-drain,
						connected an
7	HPD_SOURCE	Output	0	Low		external pull up to
						the desired
						supply
						(normally 1 V)
			0	High (5 V)		Low (0 V)
			1	Low (0 V)		Low (0 V)
			1	High (5 V)		High (3 V)
			3.3 V DDC data I/O. Pulled-up by external termination
8	SDA_SOURCE	I/O	to 3.3 V. Connected to SDA_SINK through voltage-
			limiting integrated NMOS pass-gate

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Pin configuration				STHDLS101A
	Table 2.	Pin description (continued)
	Pin	Name	Type	Function
	number
				3.3 V DDC clock I/O. Pulled-up by external termination
	9	SCL_SOURCE	Input	to 3.3 V. Connected to SCL_SINK through voltage-
				limiting integrated NMOS pass-gate
				Analog connection determined by vendor. Acceptable
				connections to this pin are:
	10	ANALOG2	Analog	– Resistor or capacitor to GND
				– Resistor or capacitor to 3.3 V
				– Short to 3.3 V or to GND
				– NC
	11	VCC33	Power	3.3 V ±10% DC supply
	12	GND	Power	Ground
				HDMI 1.3 compliant TMDS output
	13	OUT_D4+	Output	OUT_D4+ makes a differential output signal with
				OUT_D4-
				HDMI 1.3 compliant TMDS output
	14	OUT_D4-	Output	OUT_D4makes a differential output signal with
				OUT_D4+
	15	VCC33	Power	3.3 V±10% DC supply
				HDMI 1.3 compliant TMDS output
	16	OUT_D3+	Output	OUT_D3+ makes a differential output signal with
				OUT_D3-
				HDMI 1.3 compliant TMDS output
	17	OUT_D3-	Output	OUT_D3makes a differential output signal with
				OUT_D3+.
	18	GND	Power	Ground
				HDMI 1.3 compliant TMDS output
	19	OUT_D2+	Output	OUT_D2+ makes a differential output signal with
				OUT_D2-.
				HDMI 1.3 compliant TMDS output
	20	OUT_D2-	Output	OUT_D2makes a differential output signal with
				OUT_D2+
	21	VCC33	Power	3.3 V±10% DC supply
	22	OUT_D1+	Output	HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
				differential output signal with OUT_D1-
	23	OUT_D1-	Output	HDMI 1.3 compliant TMDS output. OUT_D1makes a
				differential output signal with OUT_D1+
	24	GND	Power	Ground

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