ST STHDLS101 User Manual

STHDLS101

AC coupled HDMI level shifter

Features

■Converts low-swing alternating current (AC) coupled differential input to high-definition multimedia interface (HDMI) rev 1.3 compliant

■HDMI level shifting operation up to 2.7 Gbps per lane

■Integrated 50 Ω termination resistors for AC-coupled differential inputs

■Input/output transition minimized differential signaling (TMDS) enable/disable

■Output slew rate control on TMDS outputs to minimize electromagnetic interference (EMI)

■Fail-safe outputs for backdrive protection

■No re-timing or configuration required

■Inter-pair output skew < 250 ps

■Intra-pair output skew < 10 ps

■Single power supply of 3.3 V

■ESD protection: ±6 KV HBM on all I/O pins

■Integrated display data channel (DDC) level shifters. Pass-gate voltage limiters allow 3.3 V termination on graphics and memory controller hub (GMCH) pins and 5 V DDC termination on HDMI connector pins

■Hot-plug detect (HPD) signal level shifter from HDMI/DVI connector

■Integrated pull-down resistor on HPD_SINK and OE_N inputs

Applications

■Notebooks

■PC motherboards and graphic cards

■Dongles/cable adapters

Table 1. Device summary

QFN-48

(7 x 7 mm)

Description

The STHDLS101 is a high-speed high-definition multimedia interface (HDMI) level shifter that converts low-swing AC coupled differential input to HDMI 1.3 compliant open-drain current steering RX-terminated differential output. Through the existing PCI-E pins in the graphics and memory controller hub (GMCH) of PCs or notebook motherboards, the pixel clock provides the required bandwidth (1.65 Gbps, 2.25 Gbps) for the video supporting 720p, 1080i, 1080p with a total of 36-bit resolution. The HDMI is multiplexed onto the PCIe pins in the motherboard where the AC coupled HDMI at 1.2 V is output by GMCH. The AC coupled HDMI is then level shifter by this device to 3.3 V DC coupled HDMI output. The STHDLS101 supports up to 2.7 Gbps, which is enough for 12 bits of color depth per channel, as indicated in HDMI rev 1.3. The device operates from a single 3.3 V supply and is available in a 48-pin QFN package.

Order code	Package	Packing
STHDLS101QTR	QFN-48	Tape and reel
December 2008	Rev 4	1/25
		www.st.com

Contents	STHDLS101

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		4
3	Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
	3.1	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
4	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
5	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	5.1	Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

5.1.1 Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	6.1	Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	6.2	Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	6.3	Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
7	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24

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STHDLS101	Block diagram

1 Block diagram

Figure 1. STHDLS101 block diagram

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System interface	STHDLS101

2 System interface

Figure 2.

System inferface

PCI-Express

SDVO

Graphics chipset

HDMI

Level shifter

HDMI output

(GMCH) on the

STHDLS101

connector

motherboard

CS00374

Figure 3.

Cable adapter

($-) $6)

$ONGLE OR

CABLE ADAPTER

34($,3

$0

!-6

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STHDLS101	System interface

Figure 4. DP to HDMI/DVI cable adapter

	HPD	DP Connector	HPD_SOURCE		HPD_SINK	HDMI/DVIConnector
HDMI/DVI
					DC TMDS
Transmitter	AC_TMDS		AC_TMDS	STHDLS101
				HDMI/DVI Cable
	DDC		DDC	Adaptor	DDC
PC chipset
						!-6

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Pin configuration	STHDLS101

3 Pin configuration

Figure 5. STHDLS101 pin configuration

	GND	FUNCTION4	FUNCTION3	VCC33	DDC EN	GND	HPD SINK	SDA SINK	SCL SINK	GND	VCC33	OE N
GND	36	35	34	33	32	31	30	29	28	27	26	25	24
	37
													23
IN_D1-
	38												22
IN_D1+
	39
													21
VCC33
	40
													20
IN_D2-
	41
						QFN-48							19
IN_D2+
	42
													18
GND
	43												17
IN_D3-
	44												16
IN_D3+
	45												15
VCC33
	46												14
IN_D4-
	47												13
IN_D4+	48	1	2	3	4	5	6	7	8	9	10	11	12
		GND	VCC	FUNCTION1	FUNCTION2	GND	REXT	OURCE	OURCE	OURCE		VCC	GND
			33								ANALOG2	33
								_	_	_
								S	S	S
								HPD	S	S

GND

OUT_D1-

OUT_D1+

VCC33

OUT_D2-

OUT_D2+

GND

OUT_D3-

OUT_D3+

VCC33

OUT_D4-

OUT_D4+

CS000118

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STHDLS101	Pin configuration

3.1Pin description

	Table 2.	Pin description
	Pin	Name	Type	Function
	number
	1	GND	Power	Ground
	2	VCC33	Power	3.3 V±10% DC supply
				Function pins are to enable vendor-specific features or
			Vendor-specific	test modes.
	3	FUNCTION1		For normal operation, these pins are tied to GND or
			control or test	VCC33.
			pins
				For consistent interoperability, GND is the preferred
				default connection for these signals.
				Function pins are to enable vendor-specific features or
			Vendor-specific	test modes.
	4	FUNCTION2		For normal operation, these pins are tied to GND or
			control or test	VCC33.
			pins
				For consistent interoperability, GND is the preferred
				default connection for these signals.
	5	GND	Power	Ground
				Connection to external resistor. Resistor value
				specified by device manufacturer.
	6	REXT	Analog	Acceptable connections to this pin are:
				- Resistor to GND
				- Resistor to 3.3 V
				- NC (direct connections to VCC or GND are through a
				0 Ω resistor for layout compatibility
	7	HPD_SOURCE	Output	0 to 3.3 V (nominal) output signal. This is level-shifted
				version of the HPD_SINK signal.
				3.3 V DDC data I/O. Pulled-up by external termination
	8	SDA_SOURCE	I/O	to 3.3 V. Connected to SDA_SINK through voltage-
				limiting integrated NMOS pass-gate.
				3.3 V DDC clock I/O. Pulled-up by external termination
	9	SCL_SOURCE	Input	to 3.3 V. Connected to SCL_SINK through voltage-
				limiting integrated NMOS pass-gate.
				Analog connection determined by vendor. Acceptable
				connections to this pin are:
	10	ANALOG2	Analog	- Resistor or capacitor to GND
				- Resistor or capacitor to 3.3 V
				- Short to 3.3 V or to GND
				- NC
	11	VCC33	Power	3.3 V ±10% DC supply
	12	GND	Power	Ground
				HDMI 1.3 compliant TMDS output.
	13	OUT_D4+	Output	OUT_D4+ makes a differential output signal with
				OUT_D4-.

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Pin configuration								STHDLS101
	Table 2.	Pin description (continued)
	Pin	Name	Type			Function
	number
				HDMI 1.3 compliant TMDS output.
	14	OUT_D4-	Output	OUT_D4makes a differential output signal with
				OUT_D4+.
	15	VCC33	Power	3.3 V±10% DC supply
				HDMI 1.3 compliant TMDS output.
	16	OUT_D3+	Output	OUT_D3+ makes a differential output signal with
				OUT_D3-.
				HDMI 1.3 compliant TMDS output.
	17	OUT_D3-	Output	OUT_D3makes a differential output signal with
				OUT_D3+.
	18	GND	Power	Ground
				HDMI 1.3 compliant TMDS output.
	19	OUT_D2+	Output	OUT_D2+ makes a differential output signal with
				OUT_D2-.
				HDMI 1.3 compliant TMDS output.
	20	OUT_D2-	Output	OUT_D2makes a differential output signal with
				OUT_D2+.
	21	VCC33	Power	3.3 V±10% DC supply
	22	OUT_D1+	Output	HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
				differential output signal with OUT_D1-.
	23	OUT_D1-	Output	HDMI 1.3 compliant TMDS output. OUT_D1makes a
				differential output signal with OUT_D1+.
	24	GND	Power	Ground
				Enable for level shifter path. 3.3 V tolerant low-voltage
				single-ended input. Internal pull-down enables the
				device when unconnected.
	25	OE_N	Input	OE_N		IN_D		OUT_D
						termination		Outputs
				1		High-Z		High-Z
				0		50Ω		Active
	26	VCC33	Power	3.3 V±10% DC supply
	27	GND	Power	Ground
				5 V DDC clock I/O. Pulled-up by external termination to
	28	SCL_SINK	Output	5 V. Connected to SCL_SOURCE through voltage-
				limiting integrated NMOS pass-gate.
				5V DDC data I/O. Pulled-up by external termination to
	29	SDA_SINK	I/O	5V. Connected to SDA_SOURCE through voltage-
				limiting integrated NMOS pass-gate.

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