ST STHDLS101 User Manual

Features

■ Converts low-swing alternating current (AC)

coupled differential input to high-definition
multimedia interface (HDMI) rev 1.3 compliant

■ HDMI level shifting operation up to 2.7 Gbps

per lane

■ Integrated 50 Ω termination resistors for

AC-coupled differential inputs

■ Input/output transition minimized differential

signaling (TMDS) enable/disable

■ Output slew rate control on TMDS outputs to

minimize electromagnetic interference (EMI)

■ Fail-safe outputs for backdrive protection

■ No re-timing or configuration required

■ Inter-pair output skew < 250 ps

■ Intra-pair output skew < 10 ps

■ Single power supply of 3.3 V

■ ESD protection: ±6 KV HBM on all I/O pins

■ Integrated display data channel (DDC) level

shifters. Pass-gate voltage limiters allow 3.3 V
termination on graphics and memory controller
hub (GMCH) pins and 5 V DDC termination on
HDMI connector pins

■ Hot-plug detect (HPD) signal level shifter from

HDMI/DVI connector

■ Integrated pull-down resistor on HPD_SINK

and OE_N inputs

Applications

■ Notebooks

■ PC motherboards and graphic cards

■ Dongles/cable adapters

Table 1. Device summary

STHDLS101

AC coupled HDMI level shifter

QFN-48

(7 x 7 mm)

Description

The STHDLS101 is a high-speed high-definition
multimedia interface (HDMI) level shifter that
converts low-swing AC coupled differential input
to HDMI 1.3 compliant open-drain current
steering RX-terminated differential output.
Through the existing PCI-E pins in the graphics
and memory controller hub (GMCH) of PCs or
notebook motherboards, the pixel clock provides
the required bandwidth (1.65 Gbps, 2.25 Gbps)
for the video supporting 720p, 1080i, 1080p with a
total of 36-bit resolution. The HDMI is multiplexed
onto the PCIe pins in the motherboard where the
AC coupled HDMI at 1.2 V is output by GMCH.
The AC coupled HDMI is then level shifter by this
device to 3.3 V DC coupled HDMI output. The
STHDLS101 supports up to 2.7 Gbps, which is
enough for 12 bits of color depth per channel, as
indicated in HDMI rev 1.3. The device operates
from a single 3.3 V supply and is available in a
48-pin QFN package.

Order code Package Packing

STHDLS101QTR QFN-48 Tape and reel

December 2008 Rev 4 1/25

www.st.com

25

Contents STHDLS101

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.1 Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.2 Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5 OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6 HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.2 Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/25

STHDLS101 Block diagram

1 Block diagram

Figure 1. STHDLS101 block diagram

3/25

System interface STHDLS101

2 System interface

Figure 2. System inferface

PCI-Express

SDVO

Graphics chipset

(GMCH) on the

motherboard

Figure 3. Cable adapter

HDMI

Level shifter

STHDLS101

HDMI output

connector

CS00374

$ONGLEOR

ADAPTER

CABLE

($-)$6)

34($,3

$0



!-6

4/25

STHDLS101 System interface

Figure 4. DP to HDMI/DVI cable adapter

HDMI/DVI

Transmitter

PC chipset

HPD

AC_TMDS

DDC

HPD_SOURCE

DP Connector

AC_TMDS

DDC

STHDLS101

HDMI/DVI Cable

Adaptor

HPD_SINK

DC TMDS

DDC

HDMI/DVI Connector

!-6

5/25

Pin configuration STHDLS101

3 Pin configuration

Figure 5. STHDLS101 pin configuration

FUNCTION4

GND

FUNCTION3

VCC33

DDC_EN

GND

HPD_SINK

SDA_SINK

SCL_SINK

GND

VCC33

OE_N

GND

IN_D1-

IN_D1+

VCC33

IN_D2-

IN_D2+

GND

IN_D3-

IN_D3+

VCC33

IN_D4-

IN_D4+

31

33

34

36

35

37

38

39

40

41

42

43

44

45

46

47

4

2

1

GND

33

VCC

3

FUNCTION1

FUNCTION2

48

32

QFN-48

5

6

GND

REXT

30

29

7

8

SOURCE

SDA_

HPD_SOURCE

27

28

9

RCE

SOU

SCL_

24

26

25

23

22

21

20

19

18

17

16

15

14

13

10

11

33

VCC

ANALOG2

GND

OUT_D1-

OUT_D1+

VCC33

OUT_D2-

OUT_D2+

GND

OUT_D3-

OUT_D3+

VCC33

OUT_D4-

OUT_D4+

12

GND

CS000118

6/25

STHDLS101 Pin configuration

3.1 Pin description

Table 2. Pin description

Pin

number

1GND PowerGround

2 VCC33 Power 3.3 V±10% DC supply

3 FUNCTION1

4 FUNCTION2

5GND PowerGround

6 REXT Analog

7 HPD_SOURCE Output

Name Type Function

Function pins are to enable vendor-specific features or

Vendor-specific

control or test

pins

Vendor-specific

control or test

pins

test modes.
For normal operation, these pins are tied to GND or

VCC33.
For consistent interoperability, GND is the preferred

default connection for these signals.

Function pins are to enable vendor-specific features or
test modes.

For normal operation, these pins are tied to GND or
VCC33.

For consistent interoperability, GND is the preferred
default connection for these signals.

Connection to external resistor. Resistor value
specified by device manufacturer.

Acceptable connections to this pin are:

- Resistor to GND

- Resistor to 3.3 V

- NC (direct connections to V
0 Ω resistor for layout compatibility

0 to 3.3 V (nominal) output signal. This is level-shifted
version of the HPD_SINK signal.

or GND are through a

CC

3.3 V DDC data I/O. Pulled-up by external termination

8 SDA_SOURCE I/O

9 SCL_SOURCE Input

10 ANALOG2 Analog

11 VCC33 Power 3.3 V ±10% DC supply

12 GND Power Ground

13 OUT_D4+ Output

to 3.3 V. Connected to SDA_SINK through voltage­limiting integrated NMOS pass-gate.

3.3 V DDC clock I/O. Pulled-up by external termination
to 3.3 V. Connected to SCL_SINK through voltage­limiting integrated NMOS pass-gate.

Analog connection determined by vendor. Acceptable
connections to this pin are:

- Resistor or capacitor to GND

- Resistor or capacitor to 3.3 V

- Short to 3.3 V or to GND

- NC

HDMI 1.3 compliant TMDS output.
OUT_D4+ makes a differential output signal with
OUT_D4-.

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Pin configuration STHDLS101

Table 2. Pin description (continued)

Pin

number

14 OUT_D4- Output

15 VCC33 Power 3.3 V±10% DC supply

16 OUT_D3+ Output

17 OUT_D3- Output

18 GND Power Ground

19 OUT_D2+ Output

20 OUT_D2- Output

21 VCC33 Power 3.3 V±10% DC supply

22 OUT_D1+ Output

Name Type Function

HDMI 1.3 compliant TMDS output.
OUT_D4- makes a differential output signal with
OUT_D4+.

HDMI 1.3 compliant TMDS output.
OUT_D3+ makes a differential output signal with
OUT_D3-.

HDMI 1.3 compliant TMDS output.
OUT_D3- makes a differential output signal with
OUT_D3+.

HDMI 1.3 compliant TMDS output.
OUT_D2+ makes a differential output signal with
OUT_D2-.

HDMI 1.3 compliant TMDS output.
OUT_D2- makes a differential output signal with
OUT_D2+.

HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-.

23 OUT_D1- Output

24 GND Power Ground

25 OE_N Input

26 VCC33 Power 3.3 V±10% DC supply

27 GND Power Ground

28 SCL_SINK Output

29 SDA_SINK I/O

HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+.

Enable for level shifter path. 3.3 V tolerant low-voltage
single-ended input. Internal pull-down enables the
device when unconnected.

OE_N

1 High-Z High-Z

050Ω Active

5 V DDC clock I/O. Pulled-up by external termination to
5 V. Connected to SCL_SOURCE through voltage­limiting integrated NMOS pass-gate.

5V DDC data I/O. Pulled-up by external termination to
5V. Connected to SDA_SOURCE through voltage­limiting integrated NMOS pass-gate.

IN_D

termination

OUT_D

Outputs

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