STG4158
7AFER
Low-voltage 0.6 Ω typ. single SPDT switch with break-before-make
feature and 15 kV ESD protection
Datasheet − production data
Features
■ Power-off and overvoltage protection
■ Wide operating voltage range:
V
(opr) = 1.65 to 4.5 V
CC
■ Low ON-resistance V
–R
■ Latch-up performance exceeds 300 mA
=0.85Ω (max.) at VCC=4.5V
ON
JESD 17
■ ESD performance tested on (D pin)
– 8 kV IEC-61000-4-2 ESD, contact
discharge
– 15 kV IEC-61000-4-2 ESD, air discharge
■ ESD performance test on all other pins
– 3 kV human body model
– 200 V machine model
(IEC61340-3-2 level M2)
– 1000 V charge device model
(JESD22 C101)
Description
The STG4158 is a high-speed CMOS low-voltage
single analog SPDT (single-pole dual throw)
switch or 2:1 multiplexer/demultiplexer switch
fabricated in silicon gate C
Designed to operate from 1.65 to 4.5 V, this
device is ideal for portable applications.
It offers low ON-resistance (0.6 Ω) at V
(typical T
compatible with 1.8 V, and provides control to the
switches.
= 25 °C). The SEL input threshold is
A
=0V:
IN
2
MOS technology.
=4.5V
CC
Flip Chip6
Wafer
The switch S1 is ON (connected to common port
D) when the SEL input is held high and OFF
(high-impedance state exists between the two
ports) when SEL is held low. The switch S2 is ON
(connected to common port D) when the SEL
input is held low and OFF (high-impedance state
exists between the two ports) when SEL is held
high.
The SEL input has an integrated weak pull-down
resistor to prevent the SEL signal from floating.
For low-power consumption, the SEL input must
be grounded.
The STG4158 features power-off and overvoltage
protection, enabling the device to be isolated
during voltage fault events.
Table 1. Device summary
Order code Package Packing
STG4158BJR Flip Chip6 Tape and reel
JSTG4158-CD1 Unsawn wafer
April 2012 Doc ID 14140 Rev 2 1/24
This is information on a product in full production.
www.st.com
1
Contents STG4158
Contents
1 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Die description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24 Doc ID 14140 Rev 2
STG4158 List of tables
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. AC electrical characteristics (C
Table 8. Analog switch characteristics (C
Table 9. Voltage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. Flip Chip6 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Pad information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
=35pF, RL=50Ω, tr=tf≤ 5 ns). . . . . . . . . . . . . . . . . . . 10
L
=5pF, RL=50Ω, TA= 25 °C) . . . . . . . . . . . . . . . . . . . 11
L
Doc ID 14140 Rev 2 3/24
List of figures STG4158
List of figures
Figure 1. Functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Pin connection (bump side view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Voltage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. ON-resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. OFF leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Channel-to-channel crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. OFF isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Break-before-make time delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Switching time and charge injection
(V
=0V, R
Figure 13. Turn-ON, turn-OFF delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Flip Chip6 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. Footprint recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Flip Chip6 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. Flip Chip6 tape specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Flip Chip6 reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. JTS4158-CD1 die plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
GEN
=0Ω, RL=1MΩ, CL= 100 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
GEN
4/24 Doc ID 14140 Rev 2
STG4158 Logic diagram
1 Logic diagram
Figure 1. Functional diagram
D
Figure 2. Input equivalent circuit
$
3%,
S1
S2
SEL
3
3
Table 2. Truth table
SEL Switch S1 Switch S2
HONOFF
LOFF
1. High impedance.
2
3%,
(1)
(1)
Doc ID 14140 Rev 2 5/24
ON
#36
Logic diagram STG4158
Figure 3. Pin connection (bump side view)
Table 3. Pin description
Flip Chip Symbol Name and function
1, 3 S1, S2 Independent channels
5 D Common channel
6 SEL Control
4V
2 GND Ground (0 V)
CC
Positive supply voltage
6/24 Doc ID 14140 Rev 2
STG4158 Maximum rating
2 Maximum rating
Stressing the device above the ratings listed in Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in Table 5: Recommended
operating conditions of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE program and other relevant quality documents.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
V
V
V
I
IKC
I
IK
I
OK
I
I
OP
or I
I
CC
P
T
stg
T
1. Derate above 70 °C by 18.5 mW/°C.
Table 5. Recommended operating conditions
Supply voltage -0.5 to 5.5 V
DC input voltage -0.5 to VCC +0.5 V
I
DC control input voltage -0.5 to 5.5 V
IC
DC output voltage -0.5 to VCC +0.5 V
O
DC input diode current on control pin (V
DC input diode current (V
<0 V) ±50 mA
SEL
<0V) -50 mA
SEL
DC output diode current ± 20 mA
DC output current ± 300 mA
O
DC output current peak (pulse at 1 ms, 10% duty cycle) ± 500 mA
DC VCC or ground current ± 100 mA
GND
Power dissipation at TA= 70 °C
D
(1)
500 mW
Storage temperature -65 to 150 °C
Lead temperature (10 sec.) 260 °C
L
Symbol Parameter Value Unit
V
CC
V
V
V
T
dt/dv
Supply voltage 1.65 to 4.5 V
Input voltage 0 to V
I
Control input voltage 0 to V
IC
Output voltage 0 to V
O
Operating temperature -40 to 85 °C
op
V
= 1.65 to 2.7 V 0 to 20
Input rise and fall time control
input
CC
V
= 3.0 to 4.5 V 0 to 10
CC
CC
CC
CC
V
V
V
ns/V
Doc ID 14140 Rev 2 7/24
Electrical characteristics STG4158
3 Electrical characteristics
Table 6. DC specifications
Value
Symbol Parameter V
1.65 – 1.95 0.9 0.9
2.25 – 2.7 0.9 0.9
IH
High-level
input voltage
V
1.65 – 1.95 0.6 0.6
V
IL
Low-level
input voltage
2.25 – 2.7 0.6 0.6
1.65 – 2.20
ON
ON
ONresistance
ONresistance
match
1.65 – 2.20
2.25 – 3.6 10 100
R
ΔR
between
channels
1.65 – 2.20
R
FLAT
ONresistance
flatness
(V) Test condition
CC
Min. Typ. Max. Min. Max.
3.0 – 4.3 1.0 1.0
4.5 1.1 1.1
3.0 – 4.3 0.7 0.7
4.5 0.7 0.7
2.0 3.0
= 0 V to V
V
S
CC
IS= 100 mA
3.7 – 4.5 0.6 0.85
40 400
V
= 0 V to V
S
CC
IS= 100 mA
3.7 – 4.5 10 100
1.2
= 0 V to V
V
S
CC
IS= 100 mA
3.7 – 4.5 0.2 0.4
UnitTA = 25 °C -40 to 85 °C
V
V
Ω2.25 – 3.6 0.9 1.3
mΩ
Ω2.25 – 3.6 0.3 0.6
SEL pull-
SEL
down
R
1.65 – 4.5 5000 kΩ
resistance
V
=0,
S
V
D=VCC
VS=VCC,
V
=0
D
V
= 0 to V
S
VD= open
I
OFF
I
ON
Sn OFF state
leakage
current
Sn ON state
leakage
current
1.65 – 4.5
1.65 – 4.5
8/24 Doc ID 14140 Rev 2
CC
-30 30 -300 300 nA
-20 20 -200 200 nA
STG4158 Electrical characteristics
Table 6. DC specifications (continued)
Value
Symbol Parameter V
1.65 – 4.5
D ON state
leakage
I
D
current
V
1.65 – 4.5
S ON state
leakage
I
S
current
V
Quiescent
CC
supply
current
1.65 – 4.5 V
I
1.65 – 4.5 V
SEL
SEL leakage
current
I
Quiescent
supply
I
CCLV
current lowvoltage
driving
(V) Test condition
CC
Min. Typ. Max. Min. Max.
V
= open
S
=0 to V
V
D
Floating V
0–0.5 V
>0.5 VD> VCC + 0.4 10 25 μA
CC
= 0 - 4.5 10 25 μA
D
= 0 - 4.5 10 25 μA
D
V
= 0 to V
S
CC
CC
VD= open
Floating V
0 – 0.5 V
>0.5 VS> VCC +0.4 5 15 μA
CC
=0 -4.5 5 15 μA
S
=0 -4.5 5 15 μA
S
2.5
V
4.5 9 20 μA
2.5 V
4.5 V
4.5 V
SEL=VCC
= GND 0.05 0.1 μA
SEL
=GND 0.1 1.0 μA
SEL
SEL=VCC
SEL=VCC
=1.45V 8 20 μA
SEL
-30 30 -300 300 nA
-30 30 -300 300 nA
5.6 10 μA
0.5 1.0 μA
1.0 2.0 μA
UnitTA = 25 °C -40 to 85 °C
Doc ID 14140 Rev 2 9/24
Electrical characteristics STG4158
Table 7. AC electrical characteristics (CL=35pF, RL=50Ω, tr=tf≤ 5ns)
Value
Symbol Parameter V
1.65 – 1.95 0.13
t
PLH
t
PHL
,
Propagation
delay
2.25 – 2.7 0.15
3.0 – 3.6 0.16
3.7 – 4.5 0.16
1.65 – 1.95
2.25 – 2.7 64 86
t
ON
Turn-on time
3.0 – 3.6 43 58
3.7 – 4.5 28 38
1.65 – 1.95
2.25 – 2.7 13 18
t
OFF
Turn-off time
3.0 – 3.6 13 18
3.7 – 4.5 13 18
1.65 – 1.95
t
D
Break-beforemake time
delay
2.25 – 2.7 10 56
3.0 – 3.6 5 31
3.7 – 4.5 5 25
(V) Test condition
CC
V
S=VCC
RL=50Ω
=30pF
C
L
V
S=VCC
RL=50Ω
=30pF
C
L
C
=35pF
L
=50Ω
R
L
V
S=VCC
UnitTA = 25 °C -40 to 85 °C
Min. Typ. Max. Min. Max.
ns
112 160
ns
14 20
ns
10 86
ns
/2
1.65 – 1.95
Charge
Q
injection
2.25 – 2.7 140
3.0 – 3.6 190
C
V
=1nF
L
GEN
=0V
70
pC
3.7– -4.5 230
10/24 Doc ID 14140 Rev 2
STG4158 Electrical characteristics
Table 8. Analog switch characteristics (CL=5pF, RL=50Ω, TA=25°C)
Value
Symbol Parameter V
OIRR
OFF-isolation
(1)
CC
1.65–4.5
Xtalk Crosstalk 1.65 – 4.5
THD
Total harmonic
distortion
2.3 – 4.5
-3 dB
BW
bandwidth
1.65–4.5 R
(switch ON)
(V) Test condition
=1V
V
S
RMS
f = 100 kHz
=1V
V
S
RMS
f=1MHz
V
=1V
S
RMS
f= 5MHz
=1V
V
S
RMS
f = 100 kHz
=1V
V
S
RMS
f=1MHz
V
=1V
S
RMS
f=5MHz
= 600 Ω
R
L
=50pF
C
L
V
S=VCC VPP
f=600Hz to
20 kHz
=50Ω 40 MHz
L
Min. Typ. Max. Min. Max.
-76
-55
-40
-81
-61
-48
0.015 %
UnitTA = 25 °C -40 to 85 °C
dB
dB
Control pin
SEL
input
C
1.8 – 4.5 V
L=VCC
capacitance
Sn
Sn port
capacitance
C
1.8 – 4.5 V
L=VCC
D port
C
D
capacitance
when switch is
1.8 – 4.5 V
L=VCC
enabled
1. OFF-isolation = 20 log10 (VD/VS), VD = output, VS = input to OFF switch.
Doc ID 14140 Rev 2 11/24
30
80
190
pF
Application information STG4158
4 Application information
Power-off and overvoltage protection
The STG4158 has two operation modes:
1. Normal operation mode
2. Isolation mode
In normal operation mode, the switch functions as a normal SPDT, with the SEL pin
that selects the switch to be either ON or OFF. Either S1 or S2 is connected to common
channel D.
In isolation mode, all the switches are OFF. S1 or S2 are isolated from common channel D.
The S1, S2, D ports have a 1 MΩ impedance to ground.
The operation modes are made possible by special detection circuitry that detects the
voltage level at D, S1 and S2 supplies. Depending on these voltage levels, the device goes
into isolation mode or normal operation mode accordingly.
Isolation mode is a feature of the device that is useful during fault conditions that occur in
the application environment.
Table 9. Voltage conditions
V
V
CC
Floating 0 – 4.5 V All switches OFF - S1, S2 and D are isolated from each other. Isolation
0 – 0.5 V 0 – 4.5 V All switches OFF - S1, S2 and D are isolated from each other. Isolation
V
>0.5 V
CC
1.65–4.5V 0–V
(voltage at common
port D, S1 or S2)
D,S
D, S>VCC
Voltage condition Mode
+ 0.4 All switches OFF - S1, S2 and D are isolated from each other. Isolation
CC
Either S1 or S2 is connected to D, depending on SEL input. Normal
Figure 4. Voltage conditions
The SEL input has an integrated weak pull-down resistor R
from floating. For lower power consumption, the SEL input must be grounded.
12/24 Doc ID 14140 Rev 2
to prevent the SEL signal
SEL
STG4158 Test circuits
5 Test circuits
Figure 5. ON-resistance
)
$3
6
6
##
63
'.$
Figure 6. Bandwidth
3
3
3
).
'.$
6
##
$
#36
$
6
/54
3
6
3
6
).
##
'.$
#36
Doc ID 14140 Rev 2 13/24
Test circuits STG4158
Figure 7. OFF leakage
6
##
)
3/&&
!
6
33
3
).
6
##
Figure 8. Channel-to-channel crosstalk
6
/54
3
'.$
6
##
)
$/&&
$
!
6
$
#36
$
3
6
3
6
##
).
'.$
14/24 Doc ID 14140 Rev 2
#36
STG4158 Test circuits
Figure 9. OFF isolation
6
##
'.$
6
3
Figure 10. Test circuit
05,3%
'%.%2!4/2
3
3
).
'.$
6
$54
##
6
/54
#36
2
4
1. CL = 5/35 pF or equivalent: (includes jig capacitance).
= 50 Ω or equivalent.
2. R
L
= Z
3. R
T
of pulse generator (typically 50 Ω).
OUT
Doc ID 14140 Rev 2 15/24
#
2
,
,
3#6
Test circuits STG4158
#3V
6
##
'.$
6
).
6
/54
T
/&&
T
/.
Figure 11. Break-before-make time delay
6
3
6
).
6
##
3
3
).
'.$
$
2
,
6
/54
#
,
#3V
Figure 12. Switching time and charge injection
(V
=0V, R
2
'%.
GEN
3
3
6
'%.
=0Ω, RL=1MΩ, CL= 100 pF)
GEN
6
##
$
2
,
6
/54
#
,
).
6
).
Figure 13. Turn-ON, turn-OFF delay time
6
).
3
3
).
6
##
'.$
'.$
$
2
,
6
/54
#
,
#36
#36
6
6
).
/54
6
##
'.$
T
/&&
T
/.
#36
16/24 Doc ID 14140 Rev 2
STG4158 Package mechanical data
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 14. Flip Chip6 package outline
1. The terminal pin 1 on the bumps side is identified by a distinguishing feature (for instance by a circular
“clear area” - typically 0.1 mm diameter). The terminal pin 1 on the backside of the product is identified by
a distinguishing feature (for instance by a circular “dot” - typically 0.5 mm diameter).
2. Drawing not to scale.
Doc ID 14140 Rev 2 17/24
Package mechanical data STG4158
Table 10. Flip Chip6 mechanical data
Dimensions (mm.)
Symbol
Min. Typ. Max.
A 0.545 0.6 0.655
A1 0.17 0.2 0.23
A2 0.375 0.4 0.425
b 0.23 0.255 0.28
D 0.813 0.828 0.843
D1 0.39 0.4 0.41
E 1.213 1.228 1.243
E1 0.79 0.8 0.81
e 0.36 0.4 0.44
f 0.204 0.214 0.224
ccc 0.05
Figure 15. Footprint recommendation
Grid placement area
Figure 16. Flip Chip6 marking
0.40
B
A
123
158
0.80
0.40
0.22
18/24 Doc ID 14140 Rev 2
STG4158 Package mechanical data
Figure 17. Flip Chip6 tape specification
1. All dimensions in mm.
Doc ID 14140 Rev 2 19/24
Package mechanical data STG4158
Figure 18. Flip Chip6 reel information
1. Material properties:
1) Antistatic (white or blue).
2) Conductive (black).
20/24 Doc ID 14140 Rev 2
STG4158 Die description
7 Die description
Product JSTG4158-CD1
● Wafer size: 203 mm (8 inches)
● Wafer thickness: 725 μm + 20 μm
● Die identification: UP98A.
Die layout
● Design die size (X x Y): 1128 x 728 μm
● Scribe line: 100 x 100 μm
● Stepping die size: 1228 x 828 μm
● Pad opening: 184 x 184 μm
● DI: die identification (at the position shown in Figure 19)
● Pads: pad contact (at the position shown in Figure 19 and Ta b le 1 1 ).
Figure 19. JSTG4158-CD1 die plot
Refer to Tab le 1 1 for the pad locations.
Doc ID 14140 Rev 2 21/24
Die description STG4158
Table 11. Pad information
Pad function X (μm) Y(μm)
S1 -400 200
GND 0 200
S2 400 200
V
CC
400 -200
D0-200
SEL -400 -200
Pad locations are measured relative to the die center (where X and Y are the horizontal and
vertical axis, respectively, measured in μm). Refer to Figure 19.
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STG4158 Revision history
8 Revision history
Table 12. Document revision history
Date Revision Changes
12-Nov-2007 1 Initial release
24-Apr-2012 2
Added wafer JSTG4158-CD1, Section 7: Die description, updated
Ta b le 1 , Section 2: Maximum rating, ECOPACK
Figure 18 and Disclaimer, minor text corrections throughout
document.
®
, Figure 17,
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STG4158
y
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