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STB7N52K3 - STD7N52K3
STF7N52K3 - STP7N52K3
N-channel 525 V, 0.84 Ω, 6.3 A, D2PAK, DPAK, TO-220FP, TO-220
SuperMESH3™ Power MOSFET
Preliminary Data
Features
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Type |
VDSS |
RDS(on) |
ID |
Pw |
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max |
3 |
3 |
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< 0.98 Ω |
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1 |
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STB7N52K3 |
525 V |
6.3 A |
90 W |
1 |
DPAK |
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STD7N52K3 |
525 V |
< 0.98 Ω |
6.3 A |
90 W |
D²PAK |
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STF7N52K3 |
525 V |
< 0.98 Ω |
6.3 A(1) |
25 W |
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STP7N52K3 |
525 V |
< 0.98 Ω |
6.3 A |
90 W |
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1. |
Limited by package |
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3 |
3 |
■ |
100% avalanche tested |
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2 |
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2 |
1 |
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1 |
TO-220FP |
■ Extremely high dv/dt capability |
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TO-220 |
■Gate charge minimized
■Very low intrinsic capacitances
■ |
Improved diode reverse recovery |
Figure 1. Internal schematic diagram |
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characteristics |
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■ |
Zener-protected |
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Application
■ Switching applications
Description
The new SuperMESH3™ series is obtained through the combination of a further fine tuning of ST's well established strip-based PowerMESH™ layout with a new optimization of the vertical structure. In addition to reducing on-resistance significantly versus previous generation, special attention has been taken to ensure a very good dv/dt capability and higher margin in breakdown voltage for the most demanding application.
Table 1. Device summary
Order codes |
Marking |
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Package |
Packaging |
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STB7N52K3 |
7N52K3 |
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D²PAK |
Tape and reel |
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STD7N52K3 |
7N52K3 |
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DPAK |
Tape and reel |
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STF7N52K3 |
7N52K3 |
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TO-220FP |
Tube |
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STP7N52K3 |
7N52K3 |
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TO-220 |
Tube |
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July 2008 |
Rev 1 |
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1/15 |
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to |
www.st.com |
change without notice. |
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Contents |
STB7N52K3 - STD7N52K3 - STF7N52K3 - STP7N52K3 |
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Contents
1 |
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 3 |
2 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
4 |
3 |
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
6 |
4 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
7 |
5 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
6 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
2/15
STB7N52K3 - STD7N52K3 - STF7N52K3 - STP7N52K3 |
Electrical ratings |
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1 Electrical ratings
Table 2. |
Absolute maximum ratings |
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Symbol |
Parameter |
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Value |
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Unit |
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TO-220 |
DPAK |
D²PAK |
TO-220FP |
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VDS |
Drain-source voltage (VGS = 0) |
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525 |
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V |
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VGS |
Gatesource voltage |
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± 30 |
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V |
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I |
Drain current (continuous) at T |
= 25 °C |
6.3 |
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6.3 (1) |
A |
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D |
C |
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I |
Drain current (continuous) at T |
= 100 °C |
4 |
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4(1) |
A |
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D |
C |
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IDM (2) |
Drain current (pulsed) |
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25 |
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25 (1) |
A |
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PTOT |
Total dissipation at TC = 25 °C |
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90 |
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25 |
W |
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Derating factor |
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0.72 |
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0.2 |
W/°C |
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VESD(G-S) |
Gate source ESD(HBM-C = 100 pF, |
2500 |
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V |
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R = 1.5 kΩ) |
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dv/dt (3) |
Peak diode recovery voltage slope |
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TBD |
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V/ns |
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Insulation withstand voltage (RMS) from all |
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VISO |
three leads to external heat sink |
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-- |
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2500 |
V |
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(t = 1 s; TC = 25 °C) |
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Tstg |
Storage temperature |
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-55 to 150 |
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°C |
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Tj |
Max. operating junction temperature |
150 |
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°C |
1.Limited by package
2.Pulse width limited by safe operating area
3.ISD ≤ 6.3 A, di/dt = TBD, VDD = 80% V(BR)DSS.
Table 3. |
Thermal data |
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Symbol |
Parameter |
TO-220 |
DPAK |
D²PAK |
TO-220FP |
Unit |
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Rthj-case |
Thermal resistance junction-case max |
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1.39 |
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5 |
°C/W |
Rthj-pcb |
Thermal resistance junction-pcb max |
-- |
50 |
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30 |
-- |
°C/W |
Rthj-amb |
Thermal resistance junction-ambient max |
62.5 |
-- |
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-- |
62.5 |
°C/W |
Tl |
Maximum lead temperature for soldering |
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300 |
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°C |
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purpose |
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Table 4. |
Avalanche characteristics |
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Symbol |
Parameter |
Max value |
Unit |
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IAR |
Avalanche current, repetitive or not-repetitive |
6.3 |
A |
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(pulse width limited by Tj max) |
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EAS |
Single pulse avalanche energy |
TBD |
mJ |
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(starting Tj = 25°C, ID = IAR, VDD = 50V) |
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3/15
Electrical characteristics |
STB7N52K3 - STD7N52K3 - STF7N52K3 - STP7N52K3 |
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2 Electrical characteristics
(TC = 25 °C unless otherwise specified) |
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Table 5. |
On /off states |
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Symbol |
Parameter |
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Test conditions |
Min. |
Typ. |
Max. |
Unit |
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V(BR)DSS |
Drain-source |
ID = 1 mA, VGS = 0 |
525 |
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V |
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breakdown voltage |
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IDSS |
Zero gate voltage |
VDS = Max rating |
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1 |
µA |
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drain current (VGS = 0) |
VDS = Max rating, TC=125 °C |
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50 |
µA |
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IGSS |
Gate-body leakage |
VGS = ± 20 V |
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± 10 |
µA |
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current (VDS = 0) |
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VGS(th) |
Gate threshold voltage |
VDS = VGS, ID = 50 µA |
3 |
3.75 |
4.5 |
V |
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R |
Static drain-source on |
V |
= 10 V, I |
D |
= 3.1 A |
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0.84 |
0.98 |
Ω |
DS(on |
resistance |
GS |
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Table 6. |
Dynamic |
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Symbol |
Parameter |
Test conditions |
Min. |
Typ. |
Max. |
Unit |
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gfs (1) |
Forward |
VDS = 15 V, ID = 3.1 A |
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TBD |
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S |
transconductance |
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Ciss |
Input capacitance |
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TBD |
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pF |
Output capacitance |
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Coss |
VDS = 50 V, f = 1 MHz, VGS = 0 |
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TBD |
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pF |
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Reverse transfer |
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Crss |
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TBD |
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pF |
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capacitance |
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(1) |
Equivalent output |
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COSS eq |
capacitance |
VGS = 0, VDS = 0 to 420 V |
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TBD |
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pF |
RG |
Intrinsic gate |
f = 1 MHz open drain |
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TBD |
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Ω |
resistance |
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Qg |
Total gate charge |
VDD = 420 V, ID = 6.3 A, |
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TBD |
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nC |
Qgs |
Gate-source charge |
VGS = 10 V |
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TBD |
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nC |
Qgd |
Gate-drain charge |
(see Figure 3) |
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TBD |
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nC |
1.Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
Table 7. |
Switching times |
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Symbol |
Parameter |
Test conditions |
Min. |
Typ. |
Max |
Unit |
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td(on) |
Turn-on delay time |
VDD = 262 V, ID = 3.1 A, |
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TBD |
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ns |
tr |
Rise time |
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TBD |
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ns |
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RG = 4.7 Ω, VGS = 10 V |
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td(off) |
Turn-off-delay time |
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TBD |
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ns |
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(see Figure 2) |
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tf |
Fall time |
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TBD |
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ns |
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4/15
STB7N52K3 - STD7N52K3 - STF7N52K3 - STP7N52K3 |
Electrical characteristics |
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Table 8. |
Source drain diode |
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Symbol |
Parameter |
Test conditions |
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Min. |
Typ. |
Max. |
Unit |
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ISD |
Source-drain current |
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6.3 |
A |
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(1) |
Source-drain current (pulsed) |
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25 |
A |
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ISDM |
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(2) |
Forward on voltage |
ISD = 6.3 A, VGS = 0 |
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1.6 |
V |
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VSD |
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trr |
Reverse recovery time |
ISD = 6.3 A, di/dt = 100 A/µs |
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TBD |
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ns |
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Qrr |
Reverse recovery charge |
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TBD |
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nC |
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VDD = 30 V (see Figure 7) |
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IRRM |
Reverse recovery current |
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TBD |
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A |
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trr |
Reverse recovery time |
ISD = 6.3 A, di/dt = 100 A/µs |
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TBD |
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ns |
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Qrr |
Reverse recovery charge |
VDD = 30 V, Tj = 150 °C |
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TBD |
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nC |
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IRRM |
Reverse recovery current |
(see Figure 7) |
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TBD |
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A |
1.Pulse width limited by safe operating area
2.Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Table 9. |
Gate-source Zener diode |
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Symbol |
Parameter |
Test conditions |
Min |
Typ |
Max |
Unit |
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(1) |
Gate-source breakdown |
Igs=± 1 mA (open drain) |
30 |
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V |
BVGSO |
voltage |
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1.The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components
5/15