ST STP6NK50Z, STF6NK50Z, STD6NK50Z User Manual

STF6NK50Z

STP6NK50Z - STF6NK50Z STD6NK50Z

N-CHANNEL 500V - 0.93Ω - 5.6A TO-220/TO-220FP/DPAK Zener-Protected SuperMESH™ MOSFET

TYPE	VDSS	RDS(on)	ID	Pw
STP6NK50Z	500 V	< 1.2 Ω	5.6 A	90 W
STF6NK50Z	500 V	< 1.2 Ω	5.6 A	25 W
STD6NK50Z	500 V	< 1.2 Ω	5.6 A	90 W

■TYPICAL RDS(on) = 0.93 Ω

■EXTREMELY HIGH dv/dt CAPABILITY

■100% AVALANCHE TESTED

■	GATE CHARGE MINIMIZED	TO-220	TO-220FP
■	VERY LOW INTRINSIC CAPACITANCES
■	VERY GOOD MANUFACTURING		3
	REPEATIBILITY
			1
			DPAK

3

2

1

DESCRIPTION

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products.

APPLICATIONS

■HIGH CURRENT, HIGH SPEED SWITCHING

■IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC

■LIGHTING

ORDER CODES

INTERNAL SCHEMATIC DIAGRAM

PART NUMBER	MARKING	PACKAGE	PACKAGING
STP6NK50Z	P6NK50Z	TO-220	TUBE
STF6NK50Z	F6NK50Z	TO-220FP	TUBE
STD6NK50ZT4	D6NK50Z	DPAK	TAPE & REEL

April 2004

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STP6NK50Z - STF6NK50Z - STD6NK50Z

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Value			Unit
		STP6NK50Z		STF6NK50Z
		STD6NK50Z
VDS	Drain-source Voltage (VGS = 0)	500			V
VDGR	Drain-gate Voltage (RGS = 20 kΩ )	500			V
VGS	Gatesource Voltage	± 30			V
ID	Drain Current (continuous) at TC = 25°C	5.6		5.6 (*)	A
ID	Drain Current (continuous) at TC = 100°C	3.5		3.5 (*)	A
IDM ( )	Drain Current (pulsed)	22.4		22.4 (*)	A
PTOT	Total Dissipation at TC = 25°C	90		25	W
	Derating Factor	0.72		0.2	W/°C
VESD(G-S)	Gate source ESD(HBM-C=100pF, R=1.5KΩ)	3000			V
dv/dt (1)	Peak Diode Recovery voltage slope	4.5			V/ns
VISO	Insulation Withstand Voltage (DC)	-		2500	V
Tj	Operating Junction Temperature	-55 to 150			°C
Tstg	Storage Temperature

( ) Pulse width limited by safe operating area

(1) ISD ≤ 5.6A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.

(*) Limited only by maximum temperature allowed

THERMAL DATA

		TO-220		TO-220FP
		DPAK
Rthj-case	Thermal Resistance Junction-case Max	1.38		5	°C/W
Rthj-amb	Thermal Resistance Junction-ambient Max	62.5			°C/W
Tl	Maximum Lead Temperature For Soldering Purpose	300			°C

AVALANCHE CHARACTERISTICS

Symbol	Parameter	Max Value	Unit
IAR	Avalanche Current, Repetitive or Not-Repetitive	5.6	A
	(pulse width limited by Tj max)
EAS	Single Pulse Avalanche Energy	180	mJ
	(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

GATE-SOURCE ZENER DIODE

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
BVGSO	Gate-Source Breakdown	Igs=± 1mA (Open Drain)	30			V
	Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.

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STP6NK50Z - STF6NK50Z - STD6NK50Z

ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
V(BR)DSS	Drain-source	ID = 1 mA, VGS = 0	500			V
	Breakdown Voltage
IDSS	Zero Gate Voltage	VDS = Max Rating			1	µA
	Drain Current (VGS = 0)	VDS = Max Rating, TC = 125 °C			50	µA
IGSS	Gate-body Leakage	VGS = ± 20V			±10	µA
	Current (VDS = 0)
VGS(th)	Gate Threshold Voltage	VDS = VGS, ID = 50µA	3	3.75	4.5	V
RDS(on)	Static Drain-source On	VGS = 10V, ID = 2.8 A		0.93	1.2	Ω
	Resistance

DYNAMIC

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
gfs (1)	Forward Transconductance	VDS = 8 V, ID = 2.8 A		4.3		S
Ciss	Input Capacitance	VDS = 25V, f = 1 MHz, VGS = 0		690		pF
Coss	Output Capacitance			100		pF
Crss	Reverse Transfer			20		pF
	Capacitance
Coss eq. (3)	Equivalent Output	VGS = 0V, VDS = 0V to 400V		52		pF
	Capacitance
td(on)	Turn-on Delay Time	VDD = 250 V, ID = 2.8 A		12		ns
tr	Rise Time	RG = 4.7Ω VGS = 10 V		23.5		ns
td(off)	Turn-off Delay Time	(Resistive Load see, Figure 3)		31		ns
tf	Fall Time			23		ns
Qg	Total Gate Charge	VDD = 400V, ID = 5.6 A,		24.6		nC
Qgs	Gate-Source Charge	VGS = 10V		4.9		nC
Qgd	Gate-Drain Charge			13.3		nC

SOURCE DRAIN DIODE

Symbol	Parameter	Test Conditions		Min.	Typ.	Max.	Unit
ISD	Source-drain Current					5.6	A
ISDM (2)	Source-drain Current (pulsed)					22.4	A
VSD (1)	Forward On Voltage	ISD = 5.6	A, VGS = 0			1.6	V
trr	Reverse Recovery Time	ISD = 5.6	A, di/dt = 100 A/µs		254		ns
Qrr	Reverse Recovery Charge	VDD = 48V, Tj = 25°C			1.2		µC
IRRM	Reverse Recovery Current	(see test circuit, Figure 5)			10		A
trr	Reverse Recovery Time	ISD = 5.6	A, di/dt = 100 A/µs		360		ns
Qrr	Reverse Recovery Charge	VDD = 48V, Tj = 150°C			1.9		µC
IRRM	Reverse Recovery Current	(see test circuit, Figure 5)			11		A

Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.

2.Pulse width limited by safe operating area.

3.Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.

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STP6NK50Z - STF6NK50Z - STD6NK50Z

Safe Operating Area for TO-220

Thermal Impedance for TO-220

Safe Operating Area for TO-220FP

Thermal Impedance for TO-220FP

Safe Operating Area for DPAK

Thermal Impedance for DPAK

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