ST STP5NK90Z, STF5NK90Z User Manual
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STP5NK90Z
STF5NK90Z
N-CHANNEL 900V - 2Ω - 4.5A TO-220/TO-220FP
Zener-Protected SuperMESH™MOSFET
Table 1: General Features
TYPE V
STP5NK90Z
STF5NK90Z
■ TYPICAL R
■ EXTREMELY HIGH dv /d t CAPABILITY
■ IMPROVED ESD CAPABILITY
■ 100% AVALANCHE RATED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
DSSRDS(on)
900 V
900 V
(on) = 2 Ω
DS
< 2.5 Ω
< 2.5 Ω
I
D
4.5 A
4.5 A (*)
Pw
125 W
30 W
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained thro ugh an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOSFET s including revolutionary MDmesh™ products.
Figure 1: Package
TO-220
TO-220FP
Figure 2: Internal Schematic Diagram
3
2
1
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL F OR OFF-LINE POWER SUP PLIE S,
ADAPTORS AND PFC
Table 2: Order Codes
SALES TYPE MARKING PACKAGE PACKAGING
STP5NK90Z P5NK90Z TO-220 TUBE
STF5NK90Z F5NK90Z TO-220FP TUBE
Rev. 3
1/12September 2005
STP5NK90Z - STF5NK90Z
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
STP5NK90Z STF5NK90Z
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
V
ESD(G-S)
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
V
ISO
T
j
T
stg
() Pulse width limited by safe operat i ng area
(1) I
≤4.5A, di/dt ≤200A/µs, VDD ≤ V
SD
(*) Limited only by maximum temperature allowed
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
900 V
900 V
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
()
Drain Current (pulsed) 18 18 (*) A
Total Dissipation at TC = 25°C
4.5 4.5 (*) A
2.8 2.8 (*) A
125 30 W
Derating Factor 1 0.24 W/°C
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 4000 V
Insulation Withstand Voltage (DC) - 2500 V
Operating Junction Temperature
Storage Temperature
, Tj ≤ T
(BR)DSS
JMAX.
-55 to 150
-55 to 150
°C
°C
Table 4: Thermal Data
TO-220 TO-220FP
Rthj-case Thermal Resistance Junction-case Max 1 4.2 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300 °C
Table 5: Avalanche Characteristics
Symbol Parameter Max Value Unit
I
AR
E
AS
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
4.5 A
230 mJ
Table 6: Gate-Source Zener Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain) 30 V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed t o enhance not only t he device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to p r otect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/12
STP5NK90Z - STF5NK90Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On /Off
Symbol Parameter Test Conditions Min . Typ. Max. Unit
V
(BR)DSS
Drain-source Breakdown
ID = 1 mA, VGS = 0 900 V
Voltage
I
I
V
GS(th)
R
DS(on
DSS
GSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leaka ge
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
V
= Max Rating, TC = 125°C
DS
V
= ± 20 V ± 10 µA
GS
V
= VGS, ID = 100 µA 3
DS
3.75
1
50
4.5 V
VGS = 10 V, ID = 2.25 A 2 2.5 Ω
Resistance
Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
(1) Forward Transconductance VDS = 15 V , ID = 2.25 A 4.8 S
fs
C
OSS eq
C
C
C
t
d(on)
t
d(off)
Q
Q
Q
iss
oss
rss
t
r
t
gs
gd
f
g
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3).Equivalent Outpu t
Capacitance
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 25 V, f = 1 MHz, VGS = 0 1160
V
DS
105
21.5
VGS = 0 V, VDS = 0 to 720 V 65.5 pF
= 450 V, ID = 2.2 A,
V
DD
RG = 4.7 Ω, V
GS
(see Figure 19)
= 10 V
27
7.2
52
19
= 720 V, ID = 4.4 A,
V
DD
VGS = 10 V
(see Figure 22)
41.5
6.9
21.9
58 nC
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
Table 9: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
(1)
V
SD
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
(1) Pulsed: Pulse du rat i on = 300 µs, du ty cycle 1.5 % .
(2) Pulse width limited by safe operating area.
(3) C
oss eq.
Source-drain Current
(2)
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
ISD = 4.5 A, VGS = 0
= 4.5 A, di/dt = 100 A/µs
I
SD
VDD = 35V
(see Figure 20)
= 4.5 A, di/dt = 100 A/µs
I
SD
V
= 35V, Tj = 150°C
DD
(see Figure 20)
518
3.2
12.2
712
4.66
13.1
when VDS increase s from 0 to 80% V
oss
4.5
18
1.6 V
A
A
ns
µC
A
ns
µC
A
DSS
3/12
.
STP5NK90Z - STF5NK90Z
Figure 3: Safe Operating Area For TO-220
Figure 4: Safe Operating Area For TO-220FP
Figure 6: Thermal Impedance For TO-220
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Output Characteristics
4/12
Figure 8: Transfer Characteristics
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