Features
■ Continuous current (typ): 3.6 A
■ N-channel on-resistance (typ): 53 mΩ
■ Enable/Fault functions
■ Output clamp voltage (typ):15 V
■ Undervoltage lockout
■ Short-circuit limit
■ Overload current limit
■ Controlled output voltage ramp
■ Thermal latch (typ): 165 °C
■ Uses tiny capacitors
■ Operating junction temp. - 40 °C to 125 °C
■ Available in DFN10 (3x3 mm) package
Applications
■ Hard disk drives
■ Solid state drives (SSD)
■ Hard disk and SSD arrays
■ Set-top boxes
■ DVD and Blu-ray disc drivers
Description
The STEF12 is an integrated electronic fuse
optimized for monitoring output current and input
voltage. Connected in series to a 12 V rail, it is
capable of protecting the electronic circuitry on its
output from overcurrent and overvoltage. The
device has a controlled delay and turn-on time.
When an overload condition occurs, the STEF12
limits the output current to a predefined safe
value. If the anomalous overload condition
STEF12
Electronic fuse for 12 V line
Datasheet − production data
DFN10 (3x3 mm)
persists it goes into an open state, disconnecting
the load from the power supply. If a continuous
short-circuit is present on the board, when power
is re-applied the E-fuse initially limits the output
current to a safe value and then again goes into
an open state. The device is equipped with a
thermal protection circuit. The intervention of the
thermal protection is signalled to the board
monitoring circuits through a signal on the Fault
pin. Unlike the mechanical fuses, which must be
physically replaced after a single event, the Efuse does not degrade in its performance after
short-circuit/thermal protection interventions and
it is reset either by recycling the supply voltage or
using the Enable pin. The companion chip for the
5 V power rails is also available with part number
STEF05.
Table 1. Device summary
Order code Package Packaging
STEF12PUR DFN10 (3x3 mm) Tape and reel
March 2012 Doc ID 019056 Rev 4 1/20
This is information on a product in full production.
www.st.com
20
Contents STEF12
Contents
1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.1 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.2 Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.3 Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.4 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.5 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 R limit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 C
5.4 Enable/Fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
dv/dt
6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20 Doc ID 019056 Rev 4
STEF12 Device block diagram
1 Device block diagram
Figure 1. STEF12 block diagram
AM09891v1
Doc ID 019056 Rev 4 3/20
Pin configuration STEF12
2 Pin configuration
Figure 2. Pin configuration (top view)
GND
dv/dt
V
En/fault
CC
I-Limit
N/C
AM09880v1
Table 2. Pin description
Pin n° Symbol Note
1 GND Ground pin
The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The
2dv/dt
3 En/Fault
internal capacitor allows a ramp-up time of around 1ms. An external capacitor can be
added to this pin to increase the ramp time. If an additional capacitor is not required, this
pin should be left open.
The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin
must be left floating, or it can be used to disable the output of the device by pulling it to
ground using an open drain or open collector device.
If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a
monitor circuit that the device is in thermal shutdown. It can be connected to another
device of this family to cause a simultaneous shutdown during thermal events.
Source
Source
Source
Source
Source
4 I-Limit
5 NC Not connected
6 to 10 V
11 V
4/20 Doc ID 019056 Rev 4
OUT
/Source
CC
A resistor between this pin and the Source pin sets the overload and short-circuit current
limit levels.
Connected to the source of the internal power MOSFET and to the output terminal of the
fuse
Exposed pad. Positive input voltage must be connected to VCC.
STEF12 Maximum ratings
3 Maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
/source (max 100ms) -0.3 to Vcc+0.3 V
V
OUT
Positive power supply voltage (max 100ms) -0.3 to 25
V
I-Limit (max 100ms) -0.3 to 25 V
En/Fault -0.3 to 7 V
dv/dt -0.3 to 7 V
Positive power supply voltage (steady state) -0.3 to 18
T
op
T
STG
T
LEAD
1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures
greater than the maximum ratings for extended periods of time.
Operating junction temperature range
Storage temperature range -65 to 150 °C
Lead temperature (soldering) 10 sec 260 °C
(1)
-40 to 125 °C
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4. Thermal data
Symbol Parameter Value Unit
R
R
thJA
thJC
Thermal resistance junction-ambient 52.7 °C/W
Thermal resistance junction-case 17.4 °C/W
Table 5. ESD performance
Symbol Parameter Test conditions Value Unit
HBM 1 kV
ESD ESD protection
Doc ID 019056 Rev 4 5/20
MM 200 V
CDM 500 V
Electrical characteristics STEF12
4 Electrical characteristics
VCC = 12 V, V
= 3.3 V, CI = 10 µF, CO = 47 µF, TJ = 25 °C (unless otherwise specified).
EN
Table 6. Electrical characteristics for STEF12
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Under/Overvoltage protection
V
Clamp
V
UVLO
V
Hyst
Power MOSFET
t
dly
R
DSon
V
OFF
I
Current limit
Output clamping voltage VCC = 18 V 13.8 15 16.2 V
Undervoltage lockout Turn-on, voltage rising 7.7 8.5 9.3 V
UVLO hysteresis 0.80 V
Delay time
On-resistance
Off state output voltage VCC = 18 V, V
Continuous current
D
Enabling of chip to I
with a 1 A resistive load
(1)
- 40 °C < TJ < 125 °C
GS
2
0.5in
pad, TA = 25 °C
Minimum copper, TA = 80 °C 1.7
= 100 mA
D
350 µs
35 53 70
(2)
= 0, RL = infinite 40 100 mV
(1)
3.6
82
mΩ
A
I
Short
I
Lim
Short-circuit current limit R
Overload current limit R
dv/dt circuit
dv/dt Output voltage ramp time
Enable/Fault
V
V
V
I(MAX)
V
I(INT)
I
Low level input voltage Output disabled 0.35 0.58 0.81 V
IL
Intermediate level input voltage Thermal fault, output disabled 0.82 1.4 1.95 V
High level input voltage Output enabled 1.96 2.64 3.3 V
IH
High state maximum voltage 3.4 4.3 5.4 V
Low level input current (sink) V
IL
High level leakage current for
I
I
external switch
Maximum fan-out for fault signal
Total device
I
Bias
Bias current
= 22 Ω 3.3 4.4 5.5 A
Limit
= 22 Ω 4.4 A
Limit
Enable to V
C
dv/dt
= 0 V -10 -30 µA
Enable
V
= 3.3 V 1 µA
Enable
= 11.7 V, No
OUT
0.5 0.9 2.6 ms
Total numbers of chips that can
be connected to this pin for
simultaneous shutdown
Device operational 1.5 2
Thermal shutdown 1
3Units
mA
6/20 Doc ID 019056 Rev 4
STEF12 Electrical characteristics
Table 6. Electrical characteristics for STEF12 (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
min
Minimum operating voltage 7.6 V
Thermal latch
TSD Shutdown temperature
1. Pulse test: Pulse width = 300 µs, Duty cycle = 2%
2. Guaranteed by design, but not tested in production
(1)
165 °C
Doc ID 019056 Rev 4 7/20
Typical application STEF12
5 Typical application
Figure 3. Application circuit
Figure 4. Typical HDD application circuit
5.1 Operating modes
5.1.1 Turn-on
When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling
the internal control circuitry.
After an initial delay time of typically 350 µs, the output voltage is supplied with a slope
defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the
total time from the Enable signal going high and the output voltage reaching the nominal
value is around 1 ms (refer to
8/20 Doc ID 019056 Rev 4
Figure 5, 15
)
AM09869v1
STEF12 Typical application
5.1.2 Normal operating condition
The STEF12 E-fuse behaves like a mechanical fuse, buffering the circuitry on its output with
the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET
R
.
DSOn
5.1.3 Output voltage clamp
This internal protection circuit clamps the output voltage to a maximum safe value, typically
15 V, if the input voltage exceeds this threshold.
5.1.4 Current limiting
When an overload event occurs, the current limiting circuit reduces the conductivity of the
power MOSFET, in order to clamp the output current at the value selected externally by
means of the limiting resistor R
Limit
(
Figure 3
).
5.1.5 Thermal shutdown
If the device temperature exceeds the thermal latch threshold, typically 165 °C, the thermal
shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault
pin of the device is automatically set at an intermediate voltage, in order to signal the
overtemperature event. In this condition the E-fuse can be reset either by cycling the supply
voltage or by pulling down the EN pin below the V
threshold and then releasing it.
il
5.2 R limit calculation
As shown in
monitor the output current and limit it at the level set by the user.
The R
following theoretical formula, together with the graph in
Equation 1
5.3 C
Connecting a capacitor between the C
output voltage ramp-up time.
Given the desired time interval Δt during which the output voltage goes from zero to its
maximum value, the capacitance to be added on the C
following theoretical formula:
Equation 2
dv/dt
Figure 3
value for achieving the requested current limitation can be estimated by using the
Limit
, the device uses an internal N-channel sense FET with a fixed ratio, to
calculation
RLimit
C
dvdt
Figure 13: Current limit vs. RLimit
95
--------------=
Short
I
pin and GND allows the modification of the
dv/dt
pin can be calculated using the
dv/dt
24 109–×Δt30x10
–=
12–
.
Where C
is expressed in Farads and the time in seconds.
dv/dt
Doc ID 019056 Rev 4 9/20
Typical application STEF12
The addition of an external C
between the Enable signal going high and the start of the V
influences also the initial delay time, defined as the time
dv/dt
OUT
slope (
Figure 5).
The contribution of the external capacitor to this time interval can be estimated by using the
following theoretical formula:
Equation 3
delay time 350 106–11.3 106×+× C
Figure 5. Delay time and V
12
10
delay
time
8
V
6
4
2
ramp-up time
OUT
ramp-up
time
×=
dvdt
AM09882v1
En/Fault
VOUT
0
5.4 Enable/Fault pin
The Enable/Fault pin has the dual function of controlling the output of the device and, at the
same time, of providing information about the device status to the application.
When it is used as a standard Enable pin, it should be connected to an external open-drain
or open-collector device. In this case, when it is pulled at low logic level, it turns the output of
the E-Fuse off.
If this pin is left floating, since it has internal pull-up circuitry, the output of the E-Fuse is kept
ON, in normal operating conditions.
In case of thermal fault, the pin is pulled to an intermediate state (
be provided to a monitor circuit, informing it that a thermal shutdown has occurred, or it can
be directly connected to the Enable/Fault pins of other STEFxx devices on the same
application in order to achieve a simultaneous enable/disable feature.
When a thermal fault occurs, the device can be reset either by cycling the supply voltage or
by pulling down the Enable pin below the V
Time
Figure 6
threshold and then releasing it.
il
). This signal can
10/20 Doc ID 019056 Rev 4
STEF12 Typical application
Figure 6. Enable/Fault pin status
5
Normal operating condition
4
3
2
EN/Fault voltage [V]
1
Thermal fault condition
Off/Reset
0
time
AM09871v1
Doc ID 019056 Rev 4 11/20
Typical performance characteristics STEF12
6 Typical performance characteristics
The following plots are referred to the typical application circuit and, unless otherwise noted,
= 25 °C.
at T
A
Figure 7. Clamping voltage vs. temperature Figure 8. UVLO voltage vs. temperature
16.5
16
15.5
15
Output Voltage (V)
14.5
14
13.5
V
= 18 V
CC
-40 -25 0 25 55 85 125 150
Temperature °C
AM09883v1
9.5
9.3
9.1
8.9
8.7
8.5
8.3
UVLO V oltage (V)
8.1
7.9
7.7
7.5
-40 -25 0 25 5 5 85125150
VCC= from 0 to 12 V, R
Temperature °C
LIMIT
= 15 Ω
AM09884v1
Figure 9. UVLO hysteresis vs. temperature Figure 10. Off-state voltage vs. temperature
1.4
1.2
VCCfrom 12 to 0 V, R
1
0.8
0.6
UVLO Hy steresys (V)
0.4
0.2
-40 -25 0 25 55 85125150
Temperature °C
Figure 11. Bias current (device operational) Figure 12. ON resistance vs. temperature
3
2.5
VCC= 12 V, R
2
1.5
Current (mA)
1
0.5
LIMIT
LIMIT
= 15 Ω
= 15 Ω
AM09885v1
AM09887v1
250
V
= 18 V, V
CC
200
150
100
Output Voltage (mV)
50
0
-40 -25 0 25 55 85 125 150
90
80
70
60
ON (mΩ)
50
DS
R
40
30
V
CC
= 12 V, R
= 0, RL = infi nite
GS
Temperature °C
= 15 Ω, I
LIMIT
LOAD
= 1 A
AM09886v1
AM09888v1
0
-40 -25 0 25 55 85 125 150
Temperature °C
20
12/20 Doc ID 019056 Rev 4
-40 -25 0 2 5 55 85 125
Temperature °C
STEF12 Typical performance characteristics
Figure 13. Current limit vs. R
9.00
8.00
7.00
6.00
5.00
4.00
3.00
Limit & Short Current (A)
2.00
1.00
0.00
01020304050607080
Figure 15. V
External Sensing Resistor (Ω)
ramp-up vs. Enable Figure 16. V
OUT
Limit
V
= 12 V, T = 25 °C
CC
ILIM
ISHORT
AM09889v1
Figure 14. Thermal latch delay vs. power
800
T=25 °C
80
8
Thermal Action Time (ms)
0.8
0102030405060
clamping
OUT
Power (W)
T=55 °C
T=85 °C
AM09890v1
V
= 12 V, C
CC
C
dv/dt,
Figure 17. Line transient Figure 18. Startup into output short-circuit
V
= from 12 to 18 V R
CC
= 100 µs
= 10 µF, C
IN
T = 25°C
OUT
LIMIT
= 10 µF, R
= 22 Ω; I
LIMIT
= 500 mA, T
OUT
= 22 Ω, No
RISE
V
CC
V
CC
= 18 V, C
= 12 V, R
= 10 µF, R
IN
= 22 Ω, V
LIMIT
= 22 Ω, No C
LIMIT
= Connected to GND
OUT
dv/dt
,T = 25°C
Doc ID 019056 Rev 4 13/20
Typical performance characteristics STEF12
Figure 19. Thermal latch from 2 A load to
short-circuit
Figure 20. Startup into output short-circuit
(fast rise)
V
= 12 V, R
CC
LIMIT
= 22 Ω, V
= Connected to GND
OUT
14/20 Doc ID 019056 Rev 4
STEF12 Package mechanical data
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK
specifications, grade definitions and product status are available at:
ECOPACK
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
www.st.com
.
Table 7. DFN10L (3x3 mm.) mechanical data
Dim.
Min. Typ. Max.
A 0.80 0.90 1.00
A1 0.02 0.05
A2 0.55 0.65 0.80
A3 0.20
b 0.18 0.25 0.30
D 2.85 3.00 3.15
D2 2.20 2.70
E 2.85 3.00 3.15
E2 1.40 1.75
e0.50
L 0.30 0.40 0.50
mm.
ddd 0.08
Doc ID 019056 Rev 4 15/20
Package mechanical data STEF12
Figure 21. DFN10L package outline
16/20 Doc ID 019056 Rev 4
7426335_G
STEF12 Package mechanical data
Tape & reel QFNxx/DFNxx (3x3) mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A180 7.087
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N60 2.362
T 14.4 0.567
Ao 3.3 0.130
Bo 3.3 0.130
Ko 1.1 0.043
Po 4 0.157
P 8 0.315
Doc ID 019056 Rev 4 17/20
Package mechanical data STEF12
Figure 22. DFN10L footprint - recommended data (dimensions in mm.)
7426335_G
18/20 Doc ID 019056 Rev 4
STEF12 Revision history
8 Revision history
Table 8. Document revision history
Date Revision Changes
15-Jul-2011 1 Initial release.
08-Aug-2011 2 Modified definition for Top in
14-Dec-2011 3 Removed V
06-Mar-2012 4
Updated: package mechanical data
Figure 22 on page 18
and
dv/dt
and I
rows from dv/dt circuit
dv/dt
Table 3: Absolute maximum ratings
Table 6 on page 6
Table 7 on page 15, Figure 21 on page 16
.
.
.
Doc ID 019056 Rev 4 19/20
STEF12
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20/20 Doc ID 019056 Rev 4
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