ST STE45NK80ZD User Manual

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STE45NK80ZD
N-CHANNEL 800V - 0.11Ω - 45 A ISOTOP
Super FREDMesh™ MOSFET
Table 1: Ge neral Features
TYPE V
STE45NK80ZD 800 V < 0.13 45 A 600 W
TYPICAL R
100% AVALANCHE TESTED
GATE CHARGE MINIMIZED
VERY LOW INTRINSIC CAPACITANCES
VERY GOOD MANUFACTURING
DSS
(on) = 0.11
DS
R
DS(on)
I
Pw
D
REPEATIBILITY
DESCRIPTION
The SuperFREDMesh™ series is obtained through an extreme optimization of ST’s well es­tablished strip-based PowerMESH™ layout. In ad­dition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MD­mesh™ products.
APPLICATIONS
HIGH CURRENT, HIGH SPEED SWITCHING
IDEAL FOR WELDING EQUIPMENT
Figure 1: Package
ISOTOP
Figure 2: Internal Schematic Diagram
Table 2: Order Codes
SALES TYPE MARKING PACKAGE PACKAGING
STE45NK80ZD E45NK80ZD ISOTOP TUBE
Rev. 6
1/10April 2005
STE45NK80ZD
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
DM
P
TOT
P
TOT
V
ESD(G-S)
dv/dt (1) Peak Diode Recovery voltage slope 8 V/ns
V
ISO
T
j
Tstg
(*) Pulse width li mited by safe o perating area
45A, di/dt 500 A/µs, VDD V
(1) I
SD
Table 4: Thermal Data
Rthj-case Thermal Resistance Junction-case Max 0.2 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 40 °C/W
Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ)
800 V
800 V Gate- source Voltage ± 30 V Drain Current (continuous) at TC = 25°C (Steady State)
Drain Current (continuous) at TC = 100°C
(*)
Drain Current (pulsed) 180 A
45 28
Total Dissipation at TC = 25°C (Steady State) 600 Derating Factor
5W/°C
Gate source ESD(HBM-C=100pF, R=1.5kΩ) 7KV
Insulation Withstand Voltage (AC-RMS) from All Four
2500 V
Terminals to External Heatsink Operating Junction Temperature
Storage Temperature
(BR)DSS.
- 65 to 150 °C
A A
W
Table 5: Avalanche Characteristics
Symbol Parameter Max. Value Unit
I
AR
E
AS
Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T
max)
j
Single Pulse Avalanche Energy (starting T
= 25 °C, ID = IAR, VDD = 35 V)
j
45 A
1.2 J
Table 6: Gate-Source Zener Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain) 30 V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have sp ecifically been desig ned to enhance not only the dev ice’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an ef ficient and cost-effective intervention t o protec t t he d ev ice’s i ntegrity. T hese integrated Zener diodes thus avoid the usage of external components.
2/10
STE45NK80ZD
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On/Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
ID = 1 mA, VGS = 0 800 V
Breakdown Voltage
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Zero Gate Voltage Drain Current (V
GS
= 0)
Gate-body Leakage Current (V
DS
= 0) Gate Threshold Voltage Static Drain-source On
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ± 20V ±10 µA
GS
V
= VGS, ID = 150µA
DS
2.5 3.75 4.5 V
10
100
VGS = 10V, ID = 22.5 A 0.11 0.13
Resistance
Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS = 15V, ID= 22.5 A 35 S
g
fs
C
oss eq.
C
C
C
t
d(on)
t
d(off)
Q Q Q
iss
oss
rss
t
r
t
gs gd
f
Input Capacitance Output Capacitance Reverse Transfer Capacitance
(3) Equivalent Output
Capacitance Turn-on Delay Time
Rise Time Turn-off Delay Time Fall Time
Total Gate Charge
g
Gate-Source Charge Gate-Drain Charge
= 25V, f = 1 MHz, VGS = 0 26000
V
DS
1620
260
VGS = 0V, VDS = 0V to 720V 700 pF
= 400 V, ID = 20 A
V
DD
R
=4.7Ω ,VGS = 10 V
G
(see Figure 17)
105 128 350 174
= 400 V, ID = 40 A,
V V
DD GS
= 10V
558 121
781 nC
307
µA µA
pF pF pF
ns ns ns ns
nC nC
Table 9: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
(1)
V
SD
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
(1) Pul sed: Pulse duration = 300 µs, du t y c ycle 1. 5 %. (2) Pulse wi dt h l i m i ted by safe operating area . (3) C
oss eq.
Source-drain Current
(2)
Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time
Reverse Recovery Charge Reverse Recovery Current
Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
ISD = 45 A, VGS = 0
= 40 A, di/dt = 100A/µs
I
SD
= 50 V, Tj = 25°C
V
DD
(see Figure 18)
= 40 A, di/dt = 100A/µs
I
SD
V
= 50 V, Tj = 150°C
DD
(see Figure 18)
375
4.65
24.8 568
9.66
34
when VDS increases from 0 to 80% V
oss
45
180
1.6 V
A A
ns
µC
A
ns
µC
A
DSS
3/10
.
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