ST STE2007 User Manual

查询STE2007DIE2供应商

STE2007

96 x 68 Single Chip LCD Controller/Driver

Features

■ 68 x 96 bits Display Data RAM

■ 33,49, 65 and 68 Lines Mode

■ Row by Row Scrolling

■ Interfaces

– 3-lines Serial Interface (read and write)

C (read and write)

–I – 4-Line Serial (read and write)

■ Partial Display Mode (33,25,17,9 Lines Mode)

■ Fully Integrated Oscillator requires no external

components

■ CMOS Compatible Inputs

■ Programmable ID-Number

■ Programmable Bias Ratio

■ Programmable Columns Organization

■ Fully Integrated Configurable LCD bias voltage

generator with: – Selectable multiplication factor (3x, 4X and

5X) – Effective sensing for High Precision Output – Eight selectable temperature compensation

coefficients

■ Designed for chip-on-glass (COG) applications

■ Low Power Consumption, suitable for battery

operated systems

■ Interfaces Supply Voltage range from 1.6 to

3.6V

■ High Voltage Generator Supply Voltage range

from 2.4 to 3.6V

■ Display Supply Voltage range from 3 to 13.2V

= 25°C)

amb

Description

The STE2007 is a low power LCD driver, capable to drive 96 columns and up to 68 lines, designed for monochrome displays.

The STE2007 includes fully integrated bias voltage generator (up to 5x multiplication factor), and internal oscillator, thus reducing to minimum the number of external components required and the current consumption.

The STE2007 features the three standard serial interfaces (3 and 4 lines serial, I

C interface).

Order codes

Type Ordering Number

Bumped Dice on Waffle Pack STE2007DIE2

Rev 1

November 2005 1/62

www.st.com

STE2007

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Driver Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 CPU Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Display Driver Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 MCU Tx Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4.1 Driver TxData Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 3-lines 9 bit Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.1 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1.2 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 4-Line SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.1 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.2 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3.1 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.2 Starting the Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.3 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.4 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 Reading Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4.1 IIdentification byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Display Data RAM (DDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 DDRAM and Page/column address circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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STE2007

5.2 Line address circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3 Partial Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3.1 33 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.2 25 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.3 17 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.4 9 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.4 Command Parameters Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . 38

6 Instruction Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.1 Initialization (Power ON Sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.2 Display Data Writing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.3 Power OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7 Power ON/Power OFF timing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.1 Display ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.2 Display normal/reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.3 Display all points ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4 Page address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.5 Column address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.6 Display start line address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.7 Segment driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.8 Common driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.9 Display data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.10 Data reading from driver (Driver TxData–mode) . . . . . . . . . . . . . . . . . . . . . . 46

8.11 Power Control Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.12 VLCD set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.12.1 V0R - Voltage Range Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.12.2 VOP Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.12.3 Electronic volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.13 Power saver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.15 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.16 Image Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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STE2007

8.17 Bias Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.18 Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.19 Charge Pump Multiplication Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.20 Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.21 Icon Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.22 N- Line Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.23 Number of Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9 Chip Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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STE2007 1 Introduction

1 Introduction

In this document is specified LCD driver for Black&White full graphic displays with a resolution of 96x68, 96x65, 96x49, and 96x33 (ColumnsXRows).

Abbreviations

LCD Liquid Crystal Display

COG Chip On Glass –technology

MCU Micro Controller Unit

DDRAM Display Data Random Access Memory

MSB Most Significant Bit

LSB Least Significant Bit

T.B.D. To Be Defined

Table 1. General Driver Parameters

Driver assembly technology

Chip On Glass (COG)

Memory Size

(Columns x Rows)

96x68

DDRAM capacity:

6528 bits

Mux

1:68 1:65 1:49 1:33

Frame frequency (Hz)

65 70 75 80

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1 Introduction STE2007

Figure 1. Chip Mechanical Drawing

R66

STE2007

45µm

(0,0)

BUMP SIDE

72µm

! /

VSS_AUX

R67 R65

6/62

STE2007 2 Driver Pin Description

2 Driver Pin Description

2.1 CPU Interface Pins

Table 2. CPU Interface Logic

PIN Signal Type Description Note

!RES I Reset Input

When Low the

!CS I Chip Select Input

SDOUT 0 Serial Data Output

SDAIN I

SCLK I

SDA_OUT 0

SA1 I

SA0 I

!D/C I 4 Line SPI Data/Command Selector

Serial Data Input /I Serial Clock Input/I

C Bus Data Out

C Slave Address

C Interface Data Input

C Interface Clock

communication port is enabled

Must be connected to SDAIN at Module Level

Must be left floating

when I2C Interface is not is use

Cannot be left floating

Must be connected to VSSAUX at Module Level when 4-Line SPI is not in USE

2.2 Power Supply Pins

Table 3. Power Supply Pins

PIN Signal Type Description Note

VSS Power Analog & Digital Grounds

VSS_LCD Power Drivers Analog Ground

VSS_CP Power Booster Ground

VDDI Power Digital Power

VDD Power Analog Supply VDD_CP Power Booster Power Supply VSSAUX Power Auxiliar Vss Output

Table 4. High Voltage Pins

PIN Signal Type Description Note

LCD

LCD_SENSE

High

Voltage

High

Voltage

Booster Output

Booster Sense Input

Cext = 0.1-1µF Connected to Vss

Must be connected to Vlcd at module level

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2 Driver Pin Description STE2007

Table 4. High Voltage Pins (continued)

PIN Signal Type Description Note

COM0 to

COM67

COMS

SEG0 to

SEG95

High

Voltage

High

Voltage

High

Voltage

2.3 Configuration Pins

Table 5. Configuration Pin Description

PIN Signal Type Config Description Note

OSCIN I

SEL0 -SEL1 I

LCD Row Driver Output

LCD Column Driver Output

VSS/VSSAUX Internal Oscillator Stopped

VDDI Internal Oscillator Active

SEL1 SEL0 Interface

VSS/VSSAUX VSS//VSSAUX

VSS/VSSAUX VDD1 SPI 4-Lines 8 bit

VDD1 VSS/VSSAUX Serial 3-Lines 9 bit

VDD1 VDD1 Not Used

Unused lines must be left floating

2.4 Test Pins

Table 6. Test Pin Description

PIN Signal Type Description Note

T2 I Test Input. Enable Test Mode.

T1 I Test Input. Enable Test Mode.

T0 I Test Input.

T3 O Test Output.

IDA I

VSS/VSSAUX IDA=”0”

VDDI IDA=”1”

VSS/VSSAUX IDB=”0”

IDB I

VDDI IDB=”1”

Must Be connected to VSS in Normal Working Mode

Must Be OPEN in Normal Working Mode

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STE2007 2 Driver Pin Description

Table 6. Test Pin Description (continued)

PIN Signal Type Description Note

T4 O Test Output.

T5 O Test Output.

T6 O Test Output.

VREF_B

UFF

O Analog Test Output Must be left floating

Must Be OPEN in Normal Working Mode

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3 Display Driver Electrical Characteristics STE2007

3 Display Driver Electrical Characteristics

3.1 Absolute maximum ratings

Table 7. Absolute maximum ratings

Symbol Parameter Value Unit

DDI

LCD

out

tot

stg

All pins vs

VDDI (*) ESD Maximum Withstanding Voltage Range

All other

pins / pin

Supply Voltage Range - 0.5 to + 5 V

LCD Supply Voltage Range - 0.5 to + 14.0 V

Supply Current - 50 to +50 mA

Digital Inputs Voltage

-0.5 to V

DDI

DC Input Current - 10 to + 10 mA

DC Output Current - 10 to + 10 mA

Total Power Dissipation (Tj = 85°C)

300 mW

Power Dissipation per Output 30 mW

Operating Junction Temperature -40 to + 85 °C

Storage Temperature - 65 to 150 °C

±1750 V

Test Condition: CDF-AEC-Q100-002- “Human Body Model”

Acceptance Criteria: “Normal Performance”

±2000 V

+ 0.5

combination

Note: (*) ESD tests have been performed with VSS, VSS_LCD and VSS_CP shorted together

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STE2007 3 Display Driver Electrical Characteristics

3.2 DC Characteristics

Table 8. DC characteristics

Symbol Parameter Test Condition Min. Typ. Max. Unit

DD,VDDCP

DDI

LCD

LCD_SENSE

LCD

I(V

)

DDI

I(VDD+V

DDCP

)

Logic Inputs

Logic Outputs

Power Supply Voltage Operating Voltage 2.4 3.6 V

Power Supply Voltage(Logic) I/O supply Voltage 1.6 3.6 V

Booster Output 13.5 V

Booster Sense Input 13.5 V

LCD Supply Voltage Accuracy

Logic Supply Current

LCD=10V; VDD=2.6V; T

V 25°C; No display Load;

=0Hz

SCLK

Power Saver Mode ON (Interfaces quiescent)

Power Saver Mode OFF (Interfaces quiescent)

amb

-2 2 %

13µA

620µA

Write Mode 120 250 µA

=10V;Booster= 5X;

LCD

=0Hz; VDD=2.4V

Analog Supply Current

Logic High level input voltage

Logic Low level input voltage Vss

SCLK

Refresh Rate=75Hz; no display load;T

amb

= 25°C

0.7V

90 180 µA

0.3V

DDI

Logic High level input current 1 µA

Logic Low level input current -1 µA

0.8V

Logic High level output voltage

Logic Low level output voltage

= -500µA; VDDI=1.6V

OUT

= 500µA; VDDI=1.6V

OUT

Vss

0.2V

DDI

DDl

Note: 1 T

= -40 to 85°C, unless otherwise specified.

amb

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3 Display Driver Electrical Characteristics STE2007

3.3 AC Characteristics

Table 9. AC Operation - Internal Oscillator

Symbol Parameter Test Condition Min. Typ. Max. Unit

VDDI= 1.6; VDD= 2.9V

FRAME

Frame Frequency Default

Rafresh Rate = 75Hz Tamb = -20°C to +70°C

68 75 82 Hz

3.4 MCU Tx Data Mode

Table 10. AC Characteristics for Serial interface

Description Signal Symbol Notes Min. Typ. Max. Unit

tcss 60 ns

Chip Select !CS

Input Serial Data Interface SDAIN

Output Serial Data interface SDAOUT

Serial clock input SCLK

tcsh 100 ns

tchw 50 ns

tsds Data setup time 100 ns tsdh Data hold time 100 125 ns

tac Access Time 0 100 ns

tod

Output Disable Time

25 100 ns

tscyc Serial clock cycle 250 ns

tshw

tslw

Serial clock H pulse width

Serial clock L pulse width

100 ns

Note: 1 The input signal rise and fall times must be within 10ns.

2 Every timing is specified on the basis of 30% and 70% of VDDI.

= -40 to 85°C, unless otherwise specified.

amb

Figure 2. MCU TxData timing

tchw

!CS

SCLK

SDA/MCU TxData

tcss tcsh

tslw

tscyc

tsdhtsds

tchw

tshw

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STE2007 3 Display Driver Electrical Characteristics

Table 11. Input Signals Change Time

Signal Symbol Parameter Minimum

Inputs tr,tf 10 ns / to 30% & 70% levels

Typical/

Nominal

Maximum Unit / Notes

3.4.1 Driver TxData Mode

Table 12. Timings based on 4 MHz SCLK Speed

Item Symbol Condition Rating Units

Min. Max.

Data hold time T1 Note 1 100 125 ns Access time T2 – 10 100 ns

Output disable time T3 – 25 100 ns Data setup time T4 – 100 – ns !CS pulse width high T5 – 250 ns

Note: 1 Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is Always 3-8ns

before SCLK pulse falling edge

2 The input signal rise and fall times must be within 10ns.

3 Every timing is specified on the basis of 30% and 70% of VDDI.

= -40 to 85°C, unless otherwise specified.

amb

Table 13. Timings based on 1 MHz SCLK Speed

Item Symbol Condition Rating Units

Min. Max.

Data hold time *) T1 – 100 125 ns Access time T2 – 10 450 ns Output disable time T3 – 25 450 ns Data setup time T4 – 100 – ns 1CS pulse width high T5 – 250 ns

Note: 1 The input signal rise and fall times must be within 10ns.

2 Every timing is specified on the basis of 30% and 70% of VDDI.

= -40 to 85°C, unless otherwise specified.

amb

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3 Display Driver Electrical Characteristics STE2007

Figure 3. Driver TxData Mode AC timing characteristics

Timing BTiming A

SCLK

MCU TxData

MCU Data direction

Driver TxData

Timing A

SCLK

MCU TxData

Driver TxData

Driver SDA direction

!CS

Timing B

SCLK

MCU TxData

Command

Tx TxRx

Hi±Z

Hi±Z Status

in out

Hi±Z

T1 T2

T3 T4

Command

Hi±Z

D/C

Driver TxData

out inDriver SDA direction

!CS

1/2 SCLK

3.4.2 Reset Timing

Table 14. Reset Timing

Description Signal Symbol Min. Max. Unit

Reset time !RES trs 2500

Reset rejection (for noise spike) !RES trj 1000

Note: 1 The input signal rise and fall times must be within 10ns.

2 Every timing is specified on the basis of 30% and 70% of VDDI.

= -40 to 85°C, unless otherwise specified.

amb

nsReset low pulse width (for valid reset) !RES trw 2500

14/62

STE2007 3 Display Driver Electrical Characteristics

Figure 4.

!RES

Internal circuit status

trj

trw

During reset

trs

Normal operation

15/62

4 INTERFACE STE2007

4 INTERFACE

4.1 3-lines 9 bit Serial Interface

STE2007 3-lines 9 bits serial interface is a bidirectional link between the display driver and the host processor.

It consists of three lines:

– SDAIN/SDAOUT Serial Data

– SCLK Serial Clock

– !CS Peripheral enable: - Active Low- Enables and Disables the serial interface

The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of !RES, the serial interface is ready to receive data after the internal reset time. Serial data must be input to SDA in the sequence D/!C, D7 to D0. STE2007 read data on SCLK rising edge. The first bit of serial data D/!C is data/command flag. When D/!C =”1” D7 to D0 bits are display RAM data or Command Parameters. When D/!C=”0” D7 to D0 bits identify a command

4.1.1 MCU TxData Mode (Write Mode)

STE2007 is always a slave device on the communication bus and receive the communication clock on the SCLK pin from the master. Information are exchanged word-wide. Every word is composed by 9 bit. The first bit is named D/!C and indicates whether the following byte is a command (D/!C =0) or a Display Data Byte (D/!C =1).

During data transfer, the data line is sampled by the receiver unit on the SCLK rising edge.

The data/command received is transferred to DDRAM or Executed on the first falling edge after the latching rising edge or on the !CS rising edge.

If !CS stays low after the last bit of a command/data byte, the serial interface expects the D/!C bit of the next data byte on the next SCLK positive edge.

A reset pulse on !RES pin interrupts any transmission.

Figure 5.

!CS

SDA

SCLK

D/C D7 D6 D5 D4 D3 D2 D1 D0 D/C

123456789

4.1.1.1 Data/Command Transfer break

If the Host processor generates an break condition (!CS Line HIGH before having received Bit D0) while transferring a Data byte to the Frame Memory or a Command identifier or a command parameter, the not complete received byte is discarded, the communication is interrupted and the interface is forced in reset state.

D7 D6 D5 D4

1110 12 13 14

When !CS line becomes low again to start a new communication session STE2007 is ready to receive the same byte interrupted re-transmitted or a new command identifier.

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STE2007 4 INTERFACE

Figure 6. 3-lines SPI Data Transfer break condition

Break

!CS

SCL

SDA

D7 D6 D5 D4 D3 D7 D6 D5 D4

COMMAND/PARAMETER COMMAND/PARAMETER

4.1.1.2 Data/Command Transfer pause

It is possible while transferring Frame Memory Data, Commands or Command Parameters to insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS is forced high after a whole byte received, the received byte is processed. Then STE2007 is forced in a wait state ready to restart processing incoming data from the point where the communication has been paused

If a new command identifier is transferred after a pause condition the previous communication session is definitively closed.

Four are the possible conditions:

– Command-Pause-Command

– Command-Pause-Parameter

– Parameter-Pause-Command

– Parameter-Pause-Parameter

D/!C

LR0204

Figure 7. 3-lines SPI Data Transfer Pause

Pause

!CS

SCL

SDA

D3 D2 D1 D0 D7 D6 D5 D4 D3

COMMAND/PARAMETER COMMAND/PARAMETER

4.1.2 Driver TxData Mode (Read Mode)

The Driver TxData–mode is a method to check the electrical interconnection between LCD driver and baseband, to identify the driver and for VDD Intercfonnection electrical self testing.

D/!C

D2 D1 D0

LR020

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4 INTERFACE STE2007

Self Testing of the electrical contacts is based on the monitoring of VLCD. The improper electrical contact on VDD can be noted from a too low level of VLCD.

The serial interface Driver TxData–mode is controlled by three input signals.

The serial data output (SDAOUT/Driver TxData) and serial clock input (SCLK) are enabled when !CS is low after having received one Reading Command.

To access Driver TxData–mode a Reading command must be sent to STE2007 driver. The first bit (D/C) is low to indicates next 8–bits are for command. The data is read to the driver on the rising edge of SCLK (see section ”MCU TxData–mode”). After last command bit (bit 0) is read SDAOUT becomes active (Low impedance) and MCU is able to read data from driver.

SDAOUT is forced in high impedence when !CS line is forced high or after the eight SCLK rising edges from the last SCLK rising edge of teh reading command transfer (Figure 8).

After sending out all 8 bits the driver release automatically the bus and go back to the MCU TxData–mode. MCU Txdata line changes from high–z to active low or high in the falling edge of 8th SCLK pulse. !CS must be set high and low again before !D/C writing can continue.

If !CS is forced high during the Driver TxDAta-mode, the Driver Tx data session is aborted and SDAOUT is forced in high impedance Mode.

SDAOUT and SDAIN line can be short circuited in normal working conditions.

Figure 8. AC timing characteristics

Timing BTiming A

SCLK

MCU TxData

MCU Data direction

Driver TxData

Command

Tx TxRx

Hi±Z

Hi±Z Status

Hi±Z

Command

Hi±Z

Timing A

SCLK

MCU TxData

Driver TxData

Driver SDA direction

!CS

Timing B

SCLK

MCU TxData

Driver TxData

!CS

T1 T2

in out

T3 T4

out inDriver SDA direction

1/2 SCLK

D/C

1/2 SCLK

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STE2007 4 INTERFACE

Figure 9. Timing chart for start and stop of data reading from driver

Self Test command writing Reading of status D/C writing

SCLK

MCU TxData

Driver TxData

!CS

MCU TxData begins

D/C='0' 7

4.2 4-Line SPI

STE2007 4-lines serial interface is a bidirectional link between the display driver and the host processor.

It consists of four lines:

– SDA Serial Data

– SCL Serial Clock

– !CS Peripheral enable: - Active Low- Enables and Disables the serial interface

– Mode selection (D/!C).

28912

...

High Z

...

Driver TxData begins

...

High Z

...

MCU TxData begins

D/C

The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of !RES, the serial interface is ready to receive data after the internal reset time.

4.2.1 MCU TxData Mode (Write Mode)

STE2007 is always a slave device on the communication bus and receive the communication clock on the SCL pin from the master. Information are exchanged byte-wide. During data transfer, the data line is sampled by the receiver unit on the SCL rising edge.

D/!C line status set whether the byte is a command (D/!C =0) or a data (D/!C =1); D/!C line is read on the eighth SCL clock pulse during every byte transfer.

If !CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next data byte on the next SCL positive edge.

If !CS line is forced high in the middle of a data transfer, not complete Data bytes and Commands bytes are discarded.

A reset pulse on !RES pin interrupts any transmission.

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