STE2004S
102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER
1 FEATURES
■ 102 x 65 bits Display Data RAM
■ Programmable MUX rate
■ Programmable Frame Rate
■ X,Y Programmable Carriage Return
■ Dual Partial Display Mode
■ Row by Row Scrolling
■ N-line Inversion
■ Automatic data RAM Blanking procedure
■ Selectable Input Interface:
• I2C Bus Fast and Hs-mode (read and write)
• 68000 & 8080 Parallel Interfaces (read and write)
• 3-lines and 4-lines SPI Interface (read and write)
• 3-lines 9 bit Serial Interface (read and write)
■ Fully Integrated Oscillator requires no external
components
■ CMOS Compatible Inputs
■ Fully Integrated Configurable LCD bias voltage
generator with:
• Selectable
• Effective sensing for High Precision Output
• Eight selectable temperature compensation
coefficients
■ Designed for chip-on-glass (COG) applications.
multiplication factor (up to 5X)
■ Low Power Consumption, suitable for battery
operated systems
■ Logic Supply Voltage range from 1.7 to 3.6V
■ High Voltage Generator Supply Voltage range
from 1.75 to 4.5V
■ Display Supply Voltage range from 4.5 to 14.5V
■ Backward Compatibility with STE2001/2/4
2 DESCRIPTION
The STE2004S is a low power CMOS LCD controller driver. Designed to drive a 65 rows by 102
columns graphic display, it provides all necessary
functions in a single chip, including on-chip LCD
supply and bias voltages generators, resulting in a
minimum of externals components and in a very
low power consumption.
STE2004S features six standard interfaces (3lines Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel, 8080 parallel & I
the host micro-controller.
Table 1. Order Codes
Part Numbers Type
STE2004S DIE2
2
C) for ease of interfacing with
Bumped Dice on Waffle Pack
Figure 1. Block Diagram
OSC_IN
OSC_OUT
FR_IN
FR_OUT
VSENSE SLAVE
VLCD
VLCDSENSE
VSSAUX
VDD1,2
V
SS
September 2005
RES
OSC
MASTER
SLAVE SYNC
BIAS VOLTAGE
GENERATOR
HIGH VOLTAGE
GENERATOR
RESET
I2C BUS
SAO SDIN/SDA_IN SDA_OUTSCLK/SCL
DATA
REGISTER
9 Bit SERIAL
GENERATOR
TIMING
CLOCK
INSTRUCTION
REGISTER
3 & 4 Line SPI
CO to C101 R0 to R64
COLUMN
DRIVERS
DATA
LATCHES
65 x 102
DRIVERS
REGISTER
SCROLL
RAM
DISPLAY
CONTROL
LOGIC
Parallel 8080
DB0
to
DB7
Parallel 68K
ROW
SHIFT
LOGIC
TEST
D/C CSSA1 SDOUT E/WR R/W- RD
TEST_MODE
TEST_VREF
ICON_MODE
EXT
SEL 3
SEL 2
SEL 1
LR0047
Rev. 1
1/66
STE2004S
Table 2.
PIN DESCRIPTION
N° Pad Type Function
R0 to R64 1-6
O LCD Row Driver Output
109-141
C0 to C101 6-107 O LCD Column Driver Output
V
SS 192-203 GND Ground pads.
DD1 156-163 Supply IC Positive Power Supply
V
DD2 164-171 Supply Internal Generator Supply Voltages.
V
LCD 205-209 Supply Voltage Multiplier Output
V
V
LCDSENSE
V
SENSE_SLAVE
V
SSAUX
204 Supply
Voltage Multiplier Regulation Input. V
145 Supply Voltage reference for SLAVE CHARGE PUMP
190-177-
O Ground Reference for Pins Configuration
147
V
DD1AUX
SEL1,2,3 152
142 O VDD1 Reference for Pins Configuration
153
154
I Interface Mode Selection
SEL3 SEL2 SEL1 Interface
GND / VSSAUX GND / VSSAUX GND / VSSAUX
- CANNOT BE LEFT FLOATING
GND / VSSAUX GND / VSSAUX VDD1
GND / VSSAUX VDD1 GND / VSSAUX
GND / VSSAUX VDD1 VDD1
VDD1 GND / VSSAUX GND / VSSAUX
VDD1 GND / VSSAUX VDD1
Sensing for Output Voltage Fine Tuning
LCDOUT
SPI 4-Lines 8 bit
SPI 3-Lines 8 bit
Serial 3-Lines 9 bit
Parallel 8080-series
Parallel 68000-series
I2C
EXT_SET 151 I Extended Instruction Set Selection
- CANNOT BE LEFT FLOATING
EXT PAD CONFIG INSTRUCTION SET SELECTED
GND or VSSAUX BASIC
VDD1 EXTENDED
ICON_MODE
155 I Extended Instruction Set Selection
- CANNOT BE LEFT FLOATING
ICON MODE PAD CONFIG ICON MODE STATUS
GND or VSSAUX DISBLED
VDD1 ENABLED
SDOUT 180 O Serial & SPI Data Output - IF UNUSED MUST BE LEFT FLOATING
SDIN - SDAIN 179 I SDIN - Serial & SPI Interface Data Input - CANNOT BE LEFT FLOATING
I
SDAIN - I
2
C Bus Data In - CANNOT BE LEFT FLOATING
SCLK - SCL 181 I SCLK - Serial & SPI Interface Clock - CANNOT BE LEFT FLOATING
I
SDA_OUT 178 O
SA0 149 I
SA1 148 I
2
C bus Clock - CANNOT BE LEFT FLOATING
SCL - I
2
C Bus Data Out IF UNUSED MUST BE LEFT FLOATING
I
2
C Slave Address BIT 0 - CANNOT BE LEFT FLOATING
I
2
C Slave Address BIT 1- CANNOT BE LEFT FLOATING
I
DB0 to DB7 182-189 I/O Parallel Interface 8 Bit Data Bus - CANNOT BE LEFT FLOATING
- RD 175 I R/W - 68000 Series Parallel Interface Read & Write Control Input
R/W
- CANNOT BE LEFT FLOATING
IRD
- 8080 Series Parallel Interface Read enable Clock Input
- CANNOT BE LEFT FLOATING
E / WR
176 I E - 68000 Series Parallel Interface Read & Write Clock Input
- CANNOT BE LEFT FLOATING
2/66
STE2004S
Table 2.
TEST_MODE 191 I Test Pad - 50 kohm internal Pull-down MUST BE CONNECTED TO VSS/VSSAUX
TEST_VREF 146 O Test Pad - MUST BE LEFT FLOATING
OSCOUT 210 O Internal/External Oscillator Out - IF UNUSED MUST BE LEFT FLOATING
PIN DESCRIPTION
N° Pad Type Function
E / WR 176 I WR - 8080 Series Parallel Interface - Write enable clock input
RES
D/C
CS
OSCIN 144 I
FR_OUT 211 O Master Slave Frame Inversion Synchronization.
FR_IN 143 I Master Slave Frame Inversion Synchronization.
M/S 100 I Master/
172 I Reset Input. Active Low.
174 I Interface Data/Command Selector- CANNOT BE LEFT FLOATING
173 I Serial & Parallel Interfaces ENABLE. When Low the Incoming Data are Clocked In.
(continued)
- CANNOT BE LEFT FLOATING
CANNOT BE LEFT FLOATING
Oscillator Input:
OSC_IN Configuration
High Internal Oscillator Enabled
Low Internal Oscillator Disabled
External Oscillator Internal Oscillator Disabled
IF UNUSED MUST BE LEFT FLOATING
CANNOT BE LEFT FLOATING
Slave Configuration Bit:- CANNOT BE LEFT FLOATING
M/S PIN OSC_OUT FR_OUT FR_IN Charge Pump
High ENABLED Enabled Disabled AuxVsense Disabled
Low ENABLED Enabled Enabled Charge Pump in Slave Mode or Ext
Power
3/66
STE2004S
Figure 2. Chip Mechanical Drawing
ROW 5
ROW 0
COL 0
COL 50
COL 51
ROW 6
MARK_1
MARK_3
STE2004S
(0,0)
X
Y
MARK_4
ROW 27
ROW28
ROW31
FR_OUT
OSC_OUT
VLCD
VLCDSENSE
VSS
TEST_MODE
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK - SCL
SDOUT
SDIN - SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
4/66
COL 101
ROW 32
ROW 37
MARK_2
ROW 38
ROW 59
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
ROW64/ICON
ROW63
ROW60
LR0048
Figure 3. Improved ALTH & PLESKO Driving Method
V
LCD
V
2
V
3
ROW 0
R0 (t)
V
4
V
5
V
SS
V
LCD
V
2
V
3
ROW 1
R1 (t)
V
4
V
5
V
SS
V
LCD
V
2
V
3
COL 0
C0 (t)
V
4
V
5
V
SS
V
LCD
V
2
V
3
COL 1
C1 (t)
V
4
V
5
V
SS
V
- V
LCD
SS
V3 - V
SS
STE2004S
∆V1(t)
∆V
(t)
2
V
V
state1
state2
V
- V
LCD
(t)
V3 - V
V
- V
LCD
V3 - V
V
- V
LCD
(t)
V3 - V
(t) = C1(t) - R0(t)
∆V
1
(t) = C1(t) - R1(t)
∆V
2
2
0V
SS
SS
SS
2
0V
SS
0 1 2 3 4 5 6 7 8 9 64
.......
FRAME n FRAME n + 1
0 1 2 3 4 5 6 7 8 9 64
.....
.......
.....
V
4 - V5
0V
V
SS - V5
V4 - V
VSS - V
V
4 - V5
0V
V
SS - V5
V4 - V
VSS - V
D00IN1154
LCD
LCD
LCD
LCD
5/66
STE2004S
3 CIRCUIT DESCRIPTION
3.1 Supplies Voltages and Grounds
is supply voltages to the internal voltage generator (see below). If the internal voltage generator is
V
DD2
not used, this should be connected to V
could be different form V
DD2
.
3.2 Internal Supply Voltage Generator
The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display
supply voltage generation. The multiplying factor can be programmed to be: Auto, X5, X4, X3, X2, using
the ’set CP Multiplication’ Command. If Auto is set, the multiplying factor is automatically selected to have
the lowest current consumption in every condition. This make possible to have an input voltage that changes over time and a constant V
CDSENSE
pad. For this voltage, eight different temperature coefficients (TC, rate of change with
voltage. The output voltage (V
LCD
temperature) can be programmed using TC1 & TC0 or T2, T1 and T0 bits. This will ensure no contrast
degradation over the LCD operating range.
An external supply could be connected to V
such event the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset condition) and the Charge pump (CP[0;0]) set to 5x or Auto Mode.
V
DD1
DD2
pad. V
2VLCD⋅
------------------------- 200mV+≥
n4+()
to supply the LCD without using the internal generator. In
LCD
supplies the rest of the IC. V
DD1
) is tightly controlled through the V
LCD
supply voltage
DD1
L-
3.3 Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock for the Display System. When used the OSC pad must be connected to V
pad. An external oscillator could be
DD1
used and fed into the OSC pin.If an external oscillator is used, it must be always present when STE2004S
is not in power down mode. An oscillator out is provided on the OSCOUT Pad to cascade two or more
drivers.
3.4 Master/Slave Mode
STE2004S support the Master Slave working Mode for Both Control Logic and Charge Pump. This function allows to drive matrix such as 204x65 or 102x130 using two synchronized STE2004S and the internal
Charge Pump of both device.
If M/S
is connected to VDD1, the driver is configured to work in Master Mode. When STE2004S is in Master Mode the Vsense_Slave Pin is disabled and is possible to control the VLCD value using Vop Bits. The
Master Time Generator outputs on FR_OUT and on OSC_OUT the relevant timing references.
If M/S
is connected to GND, the driver is configured to work in Slave Mode. When STE2004S is in Slave
Mode, the VLCD configuration set by Vop registers and the thermal compensation slope set by TC register
are neglected. The VLCD Value generated is equal to the Voltage value present on Vsense_Slave Pin so
the slave configuration can follow the master configuration. The only recognized configuration is Vop=0
that forces the Charge Pump to be in off state whatever is the value of Vsense_aux.
To Synchronize the Master & Slave timing circuits, the slave driver FR_IN pad must be connected to Master Driver FR_OUT pad and Slave Driver OSC_IN pad must be connected to the master driver OSC_OUT
Pad (Fig. 4). This connection ensure a synchronization at both Frame level (R0 on the master is driven
together with the Slave R0 driver) and at Oscillator Level (same Frame frequency on the master and on
the slave). If the Synchronization at Frame level is not required, FR_IN pin must be connected toVDD1 or
to VDD1_aux (Fig. 5).
During Power Up Procesure, Master device must be forced to exit from power down before the slave device. To enter in PowerDown Mode, Slave Device must be forced in Power Down state before Master Device.
6/66
Figure 4. Master Slave Logic Connection with frame Synchronization
0
0
STE2004S
STE2004S
VDD1AUX
OSCOUT
FROUT OSCINFRINOSCIN FRIN
STE2004S
OSCOUT FROUT
LR0219
Figure 5. Master Slave Logic Connection without frame Synchronization
STE2004S
VDD1AUX
OSCOUT
FROUTOSCIN FRIN
STE2004S
OSCIN
VDD1AUX
FRIN
OSCOUT FROUT
LR022
3.5 Bias Levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated.
The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are
established to be (Fig. 6):
V
LCD
n3+
-------------
,
n4+
V
LCD
n2+
-------------
,
n4+
V
LCD
-------------
,
n4+
2
V
LCD
-------------
,
n4+
1
V
LCD,VSS
Figure 6. Bias level Generator
V
R
R
nR
R
R
LCD
n + 3
n + 4
n + 2
n + 4
n + 4
n + 4
V
2
1
SS
·V
LCD
·V
LCD
·V
LCD
·V
LCD
D00IN115
thus providing an 1/(n+4) ratio, with n calculated from:
nm3–=
For m = 65, n = 5 and an 1/9 ratio is set.
For m = 49, n =4 and an 1/8 ratio is set.
The STE2004S provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:
7/66
STE2004S
Table 3.
BS2 BS1 BS0 n
0007
0016
0105
0114
1003
1012
1101
1110
The following table Bias Level for m = 65 and m = 49 are provided:
Table 4.
Symbol m = 65 (1/9) m = 49 (1/8)
V1 V
V2 8/9*V
V3 7/9*V
V4 2/9*V V
V5 1/9 *V
V6 V
LCD
LCD
LCD
LCD
LCD
SS
V
7/8*V
6/8*V
2/8*V
1/8*V
V
LCD
LCD
LCD
LCD
LCD
SS
3.6 LCD Voltage Generation
The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to
the following formula:
V
(T=To) = V
LCD
o = (Ai+VOP · B) (i=0,1,2)
LCD
with the following values:
Symbol Value Unit Note
Ao 2.95 V PRS = [0;0]
A1 6.83 V PRS = [0;1]
A2 10.71 V PRS = [1;0]
B 0.0303 V
To 2 7 ° C
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits
are set to zero the internal voltage generator is switched off.
The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Multiplexing Rate. A general expression for this is:
1m+
------------------------------------
21
V
LCD(to)
⋅=
V
1
⎛⎞
---------–
⋅
⎝⎠
m
= 6.85 · V
th
th
For MUX Rate m = 65 the ideal V
LCD
is:
V
LCD
than:
6.85 VthAi–⋅()
V
op
-----------------------------------------=
0.03
8/66
STE2004S
3.7 Temperature Coefficients
As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's
the need to vary the LCD Voltage with temperature. STE2004S provides the possibility to change the
VLCD in a linear fashion against temperature with eight different Temperature Coefficient selectable
through T2, T1 and T0 bits. Only four of them are available through basic instruction set.
Table 5.
NAME TC1 TC0 Value Unit
TC0 0 0
TC2 0 1
TC3 1 0
TC6 1 1
-0.7 · 10
-1.05· 10
-2.1 · 10
-0.0· 10
-3
-3
-3
-3
Table 6.
NAME T2 T1 T0 Value Unit
TC0 0 0 0
TC1 0 0 1
TC2 0 1 0
TC3 0 1 1
TC4 1 0 0
TC5 1 0 1
TC6 1 1 0
TC7 1 1 1
-0.35 · 10
-0.7 · 10
-1.05· 10
-1.4 · 10
-1.75· 10
-2.1 · 10
-0.0· 10
-2.3· 10
-3
-3
-3
-3
-3
-3
-3
-3
Figure 7.
1/ °C
1/°C
1/°C
1/°C
1/ °C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
LCD
V
1
A
00h 01h 02h 03h 04h 05h …. 7Fh 00h 01h 02h7Ch 7Dh 7Eh 03h 04h 7Dh 7Eh 7Fh05h …. 7Ch
Finally, the V
B
1
0
A
+ B
A
PRS = [0;0] PRS = [0;1]
voltage at a given (T) temperature can be calculated as:
LCD
V
LCD
(T) = V
o · [1 + (T-To) · TC]
LCD
2
A
00h 01h 02h 03h 04h
PRS = [1;0]
05h 7Ch
….
7Dh 7Eh 7Fh
O
V
9/66
STE2004S
3.8 Display Data RAM
The STE2004S, provides an 102X65 bits Static RAM to store Display data. This is organized into 9 (Bank0
to Bank8) banks with 102 Bytes. One of these Banks can be used for Icons. RAM access is accomplished
in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X101 (Horizontal)
and Y0 to Y8 (Vertical).
When writing to RAM, four addressing mode are provided:
• Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the mem-
ory map. The X pointer is increased after each byte written. After the last column address (X=X-Carriage), Y address pointer is set to jump to the following bank and X restarts from X=0. (Fig. 8)
• Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory
map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage),
X address pointer is set to jump to next column and Y restarts from Y=0 (Fig. 9).
• Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the
memory map. The X pointer is increased after each byte written. After the last column address (X=XCarriage), Y address pointer is set to jump to the next bank and X restarts from X=0 (fig. 10).
• Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the mem-
ory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), the X pointer is set to jump to next column and Y restarts from Y=0 (fig. 11).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jump to the
cell with address (X;Y) = (0;0) (Fig. 12,13,14 & 15).
Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.16) or on the bottom (D0=1, Fig.
17).
The STE2004S provides also means to alter the normal output addressing. A mirroring of the Display
along the X axis is enabled setting to a logic one MY bit.This function doesn't affect the content of the
memory map. It is only related to the memory read process.
When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled.
When ICON MODE=0 the Icon Row is like an other graphic line and is mirrored and scrolled.
Three are the multiplex ratio available when the partial display mode is disabled (MUX 33, MUX 49 and
MUX 65). Only a subset of writable rows are output on Row drivers in MUX 33,49 & 65 Mode.
When Y-Carriage<MUX/8, if Mux 49 is selected only the first 49 memory rows are visualized; if Mux 33 is
selected only the first 33 memory rows are visualized. The unused output row & column drivers must be
left floating.
When Y-Carriage<=MUX/8 the icon Bank is located to BANK 8 in MUX 65 Mode, to BANK6 in MUX 49
Mode and to BANK 4 in MUX 33 Mode.
In Mux 33 & 49 Mode, when Y-Carriage>MUX/8 lines only 33, 49 lines are visualized.
It is possible to select which lines of DDRAM are connected on the output drivers using the scrolling function (Range: 0-Y-Carriage*8). When Y-Carriage>MUX/8 lines, the icon row is moved in DDRAM to the
first row of the Bank correspondant to Y-CARRIAGE Return value, being always connected on the same
output Driver.
When MY=0, the icon Row is output on R64 in mux 65 mode, on R56 in MUX 49 and on R48 in MUX33.
When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever is the MUX Rate.
10/66
STE2004S
2
Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)1
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
0123 9899100101
LR0049
Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)
0123 9899100101
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
01
LR0050
Figure 10. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)
1
1
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
32109899100101
LR0051
Figure 11. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)1
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
1. X Carriage=101; Y-Carriage = 8
10329899100101
LR005
11/66
STE2004S
3
4
6
Figure 12. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=0)
BANK 0
0123
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
X CARR
98 99 100 101
LR005
Figure 13. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=0)
0123
X CARR
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
98 99 100 101
LR005
Figure 14. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=1)
X CARR
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
1239899100101
0
LR0055
Figure 15. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=1)
X CARR
BANK 0
9899100101
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
0
123
LR005
12/66
Figure 16. Data RAM Byte organization with D0 = 0
7
8
MSB
0
1 2 3 98 99 100 101
LSB
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
Figure 17. Data RAM Byte organization with D0 = 1
LSB
0123 9899100101
MSB
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
STE2004S
LR005
LR005
13/66
STE2004S
Figure 18. Memory Rows vs. Row Drivers Mapping ICON_MODE=1 and MUX 65
Y-CARRIAGE
Y Address
D2 D1 D0
D3
0
0
0
0
0
0
0
0
1
X address
D
a
t
a
D0
D1
D2
D3
0
0
0
D4
D5
D6
D7
D0
D1
D2
D3
0
1
0
D4
D5
D6
D7
D0
D1
D2
D3
1
0
0
D4
D5
D6
D7
D0
D1
D2
D3
1
1
0
D4
D5
D6
D7
D0
D1
D2
D3
0
0
1
D4
D5
D6
D7
D0
D1
D2
D3
0
1
1
D4
D5
D6
D7
D0
D1
D2
D3
1
0
1
D4
D5
D6
D7
D0
D1
D2
D3
1
1
1
D4
D5
D6
D7
0
0
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
61H 65H62H 63H 64H
60H
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Scrolling Pointer
ROW Output
Normal
Reverse
direction
direction
R0
R63
R1
R62
R2
R61
R3
R60
R4
R59
R5
R58
R6
R57
R7
R56
R8
R55
R9
R54
R10
R53
R11
R52
R12
R51
R13
R50
R14
R49
R15
R48
R16
R47
R17
R46
R18
R45
R19
R44
R20
R43
R21
R42
R22
R41
R23
R40
R24
R39
R25
R38
R26
R37
R27
R36
R28
R35
R29
R34
R30
R33
R31
R32
R32
R31
R33
R30
R34
R29
R35
R28
R36
R27
R37
R26
R38
R25
R39
R24
R40
R23
R41
R22
R42
R21
R43
R20
R44
R19
R45
R18
R46
R17
R47
R16
R48
R15
R49
R14
R50
R13
R51
R12
R52
R11
R53
R10
R54
R9
R55
R8
R56
R7
R57
R6
R58
R5
R59
R4
R60
R3
R61
R2
R62
R1
R63
R0
R64 R64
lr0268
14/66
COL
Output
Normal
Direction
Reverse
Direction
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
101
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
Figure 19. Memory Rows vs. Row Drivers Mapping ICON_MODE=0 and MUX 65
STE2004S
Y-CARRIAGE
Y Address
D2 D1 D0
D3
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
X address
D
a
t
a
D0
D1
D2
D3
0
0
D4
D5
D6
D7
D0
D1
D2
D3
0
1
D4
D5
D6
D7
D0
D1
D2
D3
1
0
D4
D5
D6
D7
D0
D1
D2
D3
1
1
D4
D5
D6
D7
D0
D1
D2
D3
0
0
D4
D5
D6
D7
D0
D1
D2
D3
0
1
D4
D5
D6
D7
D0
D1
D2
D3
1
0
D4
D5
D6
D7
D0
D1
D2
D3
1
1
D4
D5
D6
D7
0
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
61H 65H62H 63H 64H
60H
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
Scrolling Pointer
ROW Output
Normal
direction
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
Reverse
direction
R64
R63
R62
R61
R60
R59
R58
R57
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
COL
Output
Normal
Direction
Reverse
Direction
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
101
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
lr0269
15/66
STE2004S
Figure 20. Memory Rows vs. Row Drivers Mapping ICON_MODE=1,
D2 D1 D0
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
D
a
t
a
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
60H
61H 65H62H 63H 64H
Line
Address
Y-CARRIAGE
Y Address
D3
0
0
0
0
0
0
0
0
1
X address
Y-Carriage<=6
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
Scrolling Pointer
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
and MUX 49
ROW Output
Normal
Reverse
direction
direction
R0
R55
R1
R54
R2
R53
R3
R52
R4
R51
R5
R50
R6
R49
R7
R48
R8
R47
R9
R46
R10
R45
R11
R44
R12
R43
R13
R42
R14
R41
R15
R40
R16
R39
R17
R38
R18
R37
R19
R36
R20
R35
R21
R34
R22
R33
R23
R32
R23
R32
R22
R33
R21
R34
R20
R35
R19
R36
R18
R37
R17
R38
R16
R39
R15
R40
R14
R41
R13
R42
R12
R43
R11
R44
R10
R45
R9
R46
R8
R47
R7
R48
R6
R49
R5
R50
R4
R51
R3
R52
R2
R53
R1
R54
R0
R55
R56
R56
16/66
COL
Output
Normal
Direction
Reverse
Direction
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
101
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
lr0270
STE2004S
Figure 21. Memory Rows vs. Row Drivers Mapping ICON_MODE=0,
D2 D1 D0
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
D
a
t
a
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
61H 65H62H 63H 64H
60H
Y-CARRIAGE
Y Address
D3
0
0
0
0
0
0
0
0
1
X address
Y-Carriage<=6
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
Scrolling Pointer
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
and MUX 49
ROW Output
Normal
Reverse
direction
direction
R0
R56
R1
R55
R2
R54
R3
R53
R4
R52
R5
R51
R6
R50
R7
R49
R8
R48
R9
R47
R10
R46
R11
R45
R12
R44
R13
R43
R14
R42
R15
R41
R16
R40
R17
R39
R18
R38
R19
R37
R20
R36
R21
R35
R22
R34
R23
R33
R32
R32
R23
R33
R22
R34
R21
R35
R20
R36
R19
R37
R18
R38
R17
R39
R16
R40
R15
R41
R14
R42
R13
R43
R12
R44
R11
R45
R10
R46
R9
R47
R8
R48
R7
R49
R6
R50
R5
R51
R4
R52
R3
R53
R2
R54
R1
R55
R0
R56
COL
Output
Normal
Direction
Reverse
Direction
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
101
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
lr0271
17/66
STE2004S
Figure 22.
Y-CARRIAGE
Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=7, Scrolling Pointer>07h and MUX 49
Y Address
D2 D1 D0
D3
0
0
0
0
0
0
0
0
1
X address
D
a
t
a
D0
D1
D2
D3
0
0
0
D4
D5
D6
D7
D0
D1
D2
D3
0
1
0
D4
D5
D6
D7
D0
D1
D2
D3
1
0
0
D4
D5
D6
D7
D0
D1
D2
D3
1
1
0
D4
D5
D6
D7
D0
D1
D2
D3
0
0
1
D4
D5
D6
D7
D0
D1
D2
D3
0
1
1
D4
D5
D6
D7
D0
D1
D2
D3
1
0
1
D4
D5
D6
D7
D0
D1
D2
D3
1
1
1
D4
D5
D6
D7
0
0
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
60H
61H 65H62H 63H 64H
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Scrolling Pointer
ROW Output
Normal
direction
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Reverse
direction
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
18/66
COL
Output
Normal
Direction
Reverse
Direction
101
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
lr0275
STE2004S
Figure 23.
Y-CARRIAGE
Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=7, Scrolling Pointer>07h and MUX 49
Y Address
D2 D1 D0
D3
0
0
0
0
0
0
0
0
1
X address
D
a
t
a
D0
D1
D2
D3
0
0
0
D4
D5
D6
D7
D0
D1
D2
D3
0
1
0
D4
D5
D6
D7
D0
D1
D2
D3
1
0
0
D4
D5
D6
D7
D0
D1
D2
D3
1
1
0
D4
D5
D6
D7
D0
D1
D2
D3
0
0
1
D4
D5
D6
D7
D0
D1
D2
D3
0
1
1
D4
D5
D6
D7
D0
D1
D2
D3
1
0
1
D4
D5
D6
D7
D0
D1
D2
D3
1
1
1
D4
D5
D6
D7
0
0
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
61H 65H62H 63H 64H
60H
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Scrolling Pointer
ROW Output
Normal
direction
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Reverse
direction
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
R56
COL
Output
Normal
Direction
Reverse
Direction
101
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
lr0276
19/66
STE2004S
Figure 24.
Y-CARRIAGE
Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=8, Scrolling Pointer<10h and MUX 49
Y Address
D2 D1 D0
D3
0
0
0
0
0
0
0
0
1
X address
D
a
t
a
D0
D1
D2
D3
0
0
0
D4
D5
D6
D7
D0
D1
D2
D3
0
1
0
D4
D5
D6
D7
D0
D1
D2
D3
1
0
0
D4
D5
D6
D7
D0
D1
D2
D3
1
1
0
D4
D5
D6
D7
D0
D1
D2
D3
0
0
1
D4
D5
D6
D7
D0
D1
D2
D3
0
1
1
D4
D5
D6
D7
D0
D1
D2
D3
1
0
1
D4
D5
D6
D7
D0
D1
D2
D3
1
1
1
D4
D5
D6
D7
0
0
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
60H
61H 65H62H 63H 64H
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Scrolling Pointer
ROW Output
Normal
direction
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Reverse
direction
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
R56
20/66
COL
Output
Normal
Direction
Reverse
Direction
101
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
LR0273
STE2004S
Figure 25.
Y-CARRIAGE
Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=8, Scrolling Pointer<10h and MUX 49
Y Address
D2 D1 D0
D3
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
X address
D
a
t
a
D0
D1
D2
D3
0
0
D4
D5
D6
D7
D0
D1
D2
D3
0
1
D4
D5
D6
D7
D0
D1
D2
D3
1
0
D4
D5
D6
D7
D0
D1
D2
D3
1
1
D4
D5
D6
D7
D0
D1
D2
D3
0
0
D4
D5
D6
D7
D0
D1
D2
D3
0
1
D4
D5
D6
D7
D0
D1
D2
D3
1
0
D4
D5
D6
D7
D0
D1
D2
D3
1
1
D4
D5
D6
D7
0
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
60H
61H 65H62H 63H 64H
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Scrolling Pointer
ROW Output
Normal
direction
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
Reverse
direction
R56
R55
R54
R53
R52
R51
R50
R49
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
COL
Output
Normal
Direction
Reverse
Direction
101
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
LR0274
21/66
STE2004S
Figure 26.
Y-CARRIAGE
Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=4 and MUX33
D2 D1 D0
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
D
a
t
a
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
D0
D1
D2
D3
0
D4
D5
D6
D7
D0
D1
D2
D3
1
D4
D5
D6
D7
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
61H 65H62H 63H 64H
60H
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Scrolling Pointer
Y Address
D3
0
0
0
0
0
0
0
0
1
X address
ROW Output
Normal
direction
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
Reverse
direction
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
R48
22/66
COL
Output
Normal
Direction
Reverse
Direction
101
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
LR0272
STE2004S
Figure 27.
Y-CARRIAGE
Memory Rows vs. Row Drivers Mapping ICON_MODE=0,
Y Address
D2 D1 D0
D3
0
0
0
0
0
0
0
0
1
X address
D
a
t
a
D0
D1
D2
D3
0
0
0
D4
D5
D6
D7
D0
D1
D2
D3
0
1
0
D4
D5
D6
D7
D0
D1
D2
D3
1
0
0
D4
D5
D6
D7
D0
D1
D2
D3
1
1
0
D4
D5
D6
D7
D0
D1
D2
D3
0
0
1
D4
D5
D6
D7
D0
D1
D2
D3
0
1
1
D4
D5
D6
D7
D0
D1
D2
D3
1
0
1
D4
D5
D6
D7
D0
D1
D2
D3
1
1
1
D4
D5
D6
D7
0
0
0
D0
00H
02H 06H03H 04H 05H
01H
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
5FH
61H 65H62H 63H 64H
60H
Y-Carriage<=4
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
and MUX 33
Scrolling Pointer
ROW Output
Normal
direction
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
Reverse
direction
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
R38
R37
R36
R35
R34
R33
R32
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
COL
Output
Normal
Direction
Reverse
Direction
101
C
C
O
L
C
O
L
100 99
C
O
O
L
L
C
C
O
O
L
L
98 979695
C
O
L
0
C
O
L
C
C
C
O
O
O
L
L
L
C
C
C
O
O
O
L
L
L
C
C
O
O
L
L
C
C
O
O
L
L
5
6
C
C
C
C
O
O
L
L
C
C
O
O
L
L
4
C
O
O
O
L
L
L
1011 2 3 4 5 6 1009998979695
C
C
C
O
O
O
L
L
L
0
123
LR0272
23/66
STE2004S
Figure 28. Row Drivers vs. LCD Panel Interconnection in MUX65 Mode
ICON
MUX 65
COLUMN DRIVERS
ROW DRIVERS
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
STE2004S
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R10
R11
R12
R13
R14
R15
R16
ROW DRIVERS
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
Figure 29. Row Drivers vs. LCD Panel Interconnection in MUX49 Mode
ICON
MUX 49
COLUMN DRIVERS
LR0109
24/66
ROW DRIVERS
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
STE2004S
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R10
R11
R12
ROW DRIVERS
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
LR0108
Figure 30. Row Drivers vs. LCD Panel Interconnection in MUX33 Mode
ICON
MUX 33
COLUMN DRIVERS
STE2004S
ROW DRIVERS
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
STE2004S
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
ROW DRIVERS
R 8
R 9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
LR0107
4 BUS INTERFACES
To provide the widest flexibility and ease of use the STE2004S features Six different methods for interfacing the host Controller. To select the desired interface the SEL1, SEL2 and SEL3 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused
interfaces must be connected to GND.
All interfaces are working while the STE2004S is in Power Down.
Table 7.
SEL3 SEL2 SEL1 Interface Note
000
2
C
I
0 0 1 SPI 4 lines 8 bit Read and Write
0 1 0 SPI 3 lines 8 bit Read and Write
0 1 1 Serial 3 lines 9 bit Read and Write
1 0 0 Parallel 8080-series Read and Write
1 0 1 Parallel 68000-series Read and Write
Read and Write; Fast and
High Speed Mode
2
4.1 I
C Interface
2
C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock)
The I
and High Speed Mode (3.4MHz).
This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for
data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a
positive supply voltage via an active or passive pull-up.
25/66
STE2004S
The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, de-
fine the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High,
defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the High period of the clock signal. The data on the line may be changed during
the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of
data bytes transferred between the start and the stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with the ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device that gets the
signals is called "receiver". The device that controls the message is called "master". The devices that are
controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock
pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also,
a master receiver must generate an acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the
acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver
must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the
master to generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass
(COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system
SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin
Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2004S will not be
able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in
a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required,
it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee
a valid LOW level.
To be compliant with the I
quence "S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without detecting the master code.
2
C-bus Hs-mode specification the STE2004S is able to detect the special se-
26/66
Figure 31. Bit transfer and START,STOP conditions definition
9
0
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
STE2004S
START
CONDITION
Figure 32. Acknowledgment on the
SCLK FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
START
I2C-bus
1
MSB LSB
CHANGE OF
DATA ALLOWED
289
STOP
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGEMENT
LR006
LR007
4.1.1 Communication Protocol
The STE2004S is an I
2
C slave. The access to the device is bi-directional since data write and status read
are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits (01111). The
two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or
to a logic 1.
To start the communication between the bus master and the slave LCD driver, the master must initiate a
START condition. Following this, the master sends an 8-bit byte, on the SDA bus line (Most significant bit
first). This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/W
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I
).
2
C-bus
transfer.
4.1.1.1 Writing Mode.
If the R/W bit is set to logic 0 the STE2004S is set to be a receiver. After the slaves acknowledge one or
more command word follows to define the status of the device.
A command word is composed by three bytes. The first is a control byte which defines the Co and D/C
values, the second and third are data bytes. The Co bit is the command MSB and defines if after this command will follow two data bytes and an other command word or if will follow a stream of data (Co = 1 Command word, Co = 0 Stream of data). The D/C
= 1 RAM Data, D/C = 0 Command).
(D/C
If Co =1 and D/C
= 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the
bit defines whether the data byte is a command or RAM data
following data byte will be stored in the data RAM at the location specified by the data pointer.
Every byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C
is set to a logic 1 the incoming data bytes are stored inside the STE2004S
Display RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every byte written and in the end points to the last RAM location written.
Every byte must be acknowledged by all addressed units.
4.1.1.2 Reading Mode.
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit
27/66
STE2004S
during the last write access, is set to a logic 0, the byte read is the status byte.
Figure 33. Communication Protocol
WRITE MODE
DRIVER ACK
S
SS011110A0A
SLAVE ADDRESS
READ MODE
SS011110A1A
A
1
R/W
DRIVER ACK MASTER ACK
S
A
1
Co
DRIVER ACK
A1 DC Control Byte DATA Byte
COMMAND WORD CONTROL BYTE MSB........LSB
P
DRIVER ACK DRIVER ACK DRIVER ACK
ADC Control ByteA 0 DATA Byte A P
Co LAST N> 0 BYTE
S
S
011110AR/
A
1
W
CoD
000 A
C
H
[1]H[0]HE
R/W
DRIVER
SLAVE ADDRESS
CONTROL BYTE
LR0008
4.2 SERIAL INTERFACES
STE2004S can feature three different serial synchronized interfaces with the host controller. It is possible to select a 3-lines SPI, a 4-lines SPI or 3-line 9 bits Serial Interface.
4.2.1 4-lines SPI interface
STE2004S 4-lines serial interface is a bidirectional link between the display driver and the application supervisor.
It consists of four lines: one/two for data signals (SDIN, SOUT), one for clock signals (SCLK), one for the peripheral enable (CS
The serial interface is active only if the CS
consumption is zero. While CS
) and one for mode selection (SD/C).
line is set to a logic 0. When CS line is high the serial peripheral power
pin is high the serial interface is kept in reset.
The STE2004S is always a slave on the bus and receive the communication clock on the SCLK pin from the
master.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.
SD/C
line status indicates whether the byte is a command (SD/C =0) or a data (SD/C =1); SD/C line is read on
the eighth SCLK clock pulse during every byte transfer.
stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte
If CS
at the next SCLK positive edge.
A reset pulse on RES
pin interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared.
If CS
is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SDOUT can be read the driver I
allows to read I
2
C slave address or Status byte is reported in Fig. 34 & 35. SDOUT is in High impedance in
2
C slave address or the status byte. The Command sequence that
steady state and during data write.
It is possible to short circuit SDOUT and SDIN and read I2C address or status Byte without any additional lines.
28/66
Figure 34. 4-lines serial bus protocol - one byte transmission
CS
D/C
SCLK
STE2004S
SDIN
MSB LSB
Figure 35. 4-lines serial bus protocol - several byte transmission
CS
D/C
SCLK
SDIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
Figure 36. 4-lines serial bus protocol - I2C Address or Status Byte Read
CS
SCLK
Don't
Don't
Don't
Don't
Don't
SDIN
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Care
Care
Care
Care
Care
Don't
Care
Don't
Care
Don't
Care
LR0071
LR0072
SDOUT
High-Z
High-Z
Command Write
DB7 DB6 DB5 DB4 DB3 DB2
ID Number
DB7 DB6 DB5 DB4 DB3 DB2
STATUS BYTE
DATA Read
DB1 DB0
DB1 DB0
High-Z
High-Z
LR00076
29/66
STE2004S
Figure 37. 4-lines SPI Reading Sequence
READING SEQUENCE
Write a "00000000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 8 pulses on SCLK and
Read the ID Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
1
.
LR0078
4.2.2 3-lines SPI Interface
The STE2004S 3-lines serial Interface is a bidirectional link between the display driver and the application
supervisor.
It consists of three lines: one/two for data signals (SDIN,SDOUT), one for clock signals (SCLK) and one
for peripheral enable (CS
).
If the R/W bit is set to logic 0 the STE2004S is set to be a receiver. One or more command word follows
to define the status of the device.
A command word is composed by two bytes. The first is a control byte which defines Co, D/C
, R/W H[1;0]
and HE values, the second is a data byte (fig 39). The Co bit is the command MSB and defines if after this
command will follow one data byte and an other command word or if will follow a stream of Commands or
a Steam of DDRAM Data (Co = 1 Command word, Co = 0 Stream of data). The D/C
the data byte is a command or DDRAM data (D/C
= 1 RAM Data, D/C = 0 Command). The H[1;0] bits
bit defines whether
define the instruction Set Page if HE bit =1. If HE bit is set to 0 H[1;0] values are neglected and it is possible
to update the instruction set page number using only the related instruction in the instruction Set.
If Co =1 and D/C
= 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the
following data byte will be stored in the data RAM at the location specified by the data pointer.
After the last control byte, if D/C
is set to a logic 1 the incoming data bytes are stored inside the STE2004S
Display Data RAM starting at the address specified by the data pointer. The data pointer is automatically
updated after every byte written and in the end points to the last RAM location written.
Throughout SDOUT can be read the driver I
that allows to read I
If the R bit is set to logic 0 and D/C=0, the I
C=0, the the I
2
C slave address or the Status byte is reported in Fig. 39 & 40.
2
C slave address is read
SDOUT is in High impedance in steady state and during data write.
It is possible to short circuit SDOUT and SDIN and read I
2
C slave address or the status Byte. The Command sequence
2
C slave address is read; If the R bit is set to logic 1 and D/
2
C address or status byte without any additional
line.
30/66
Figure 38. 3-lines serial interface protocol in Writing Mode
WRITE MODE
Control Byte
1
Co
COMMAND WORD CONTROL BYTE MSB........LSB
DATA Byte
Control Byte
Control Byte0 DATA Byte
Co LAST N> 0 BYTE
R
CoD
C
H
00
/
E
W
CONTROL BYTE
STE2004S
H
H
[0]
[1]
0 DATA Byte
0
DATA Byte
TRANSFERRED
ONLY COMMANDS
LAST N> 0 BYTE
CONTROL BYTE MSB........LSB
Control Byte
1
0 DATA Byte
DATA Byte
TRANSFERRED
ONLY DDRAM DATA
LAST N> 0 BYTE
CONTROL BYTE MSB........LSB
Figure 39. 3-lines SPI interface protocol in Reading Mode
CS
SCLK
Don't
SDIN
SDOUT
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Co=1 D/C=0
"Command"
R/W=1
"Read"
High-Z
High-Z
Command Write
Don't
Care
Care
DB7 DB6 DB5 DB4 DB3 DB2
DB7 DB6 DB5 DB4 DB3 DB2
Don't
Don't
Care
Care
ID-Number
STATUS BYTE
DATA Read
DATA Byte = Command if D/C=0
DATA Byte = DDRAM Data if D/C=1
LR0002
Don't
Don't
Don't
Care
Care
Don't
Care
Care
DB1 DB0
DB1 DB0
High-Z
High-Z
LR0077
31/66
STE2004S
Figure 40. 3-lines SPI Reading Sequence
READING SEQUENCE
Set Co bit =1, D/C Bit =0 R/W Bit =1
SDOUT Buffer become active (Low Impedence)
Read the
SDOUT Buffer Configured in High Impedence
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
or the Status Byte On SDOUT
END OF READING SEQUENCE
Source 8 pulses on SCLK and
ID-Number
1
.
LR0079
4.2.3 3-lines 9 bits Serial Interface
The STE2004S 3-lines serial Interface is a bidirectional link between the display driver and the application
supervisor.
It consists of three lines: one/two for data signals (SDIN, SDOUT), one for clock signals (SCLK) and one
for peripheral enable (CS
The serial interface is active only if the CS
power consumption is zero. While CS
).
line is set to a logic 0. When CS line is high the serial peripheral
pin is high the serial interface is kept in reset.
The STE2004S is always a slave on the bus and receive the communication clock on the SCLK pin from
the master.
Information are exchanged word-wide. The word is composed by 9 bit. The first bit is named SD/C
indicates whether the following byte is a command (SD/C
=0) or Data Byte (SD/C =1). During data trans-
and
fer, the data line is sampled on the positive SCLK edge.
If CS
stays low after the last bit of a command/data byte, the serial interface expects the SD/C Bit of the
next word at the next SCLK positive edge.
A reset pulse on RES
pin interrupts the transmission. No data is written into the data RAM and all the internal registers are cleared.
If CS
is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SDOUT can be read only the driver I
quence that allows to read I
2
C slave address or Status byte is reported in Fig. 43 & 44. SDOUT is in High
impedance in steady state and during data write.
It is possible to short circuit SDOUT and SDIN and read I
2
C slave address or the status byte. The Command se-
2
C address or status byte without any additional
line.
32/66
Figure 41. 3-lines serial bus protocol - one byte transmission
4
CS
SCLK
STE2004S
SDIN
MSBSD/C
Figure 42. 3-lines serial bus protocol - several byte transmission
CS
SCLK
SDIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0D/C
D/C DB7 DB6D/C
Figure 43. 3-lines serial interface protocol in Reading Mode
CS
SCLK
Don't
Don't
SDIN
SDOUT
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SD/C
DB7SD/C
High-Z
High-Z
Don't
Care
Care
DB7 DB6 DB5 DB4 DB3 DB2
DB7 DB6 DB5 DB4 DB3 DB2
Don't
Care
Care
ID-Number
STATUS BYTE
Don't
Care
Don't
Care
LSB
Don't
Don't
Care
Care
DB1 DB0
DB1 DB0
LR0073
LR007
High-Z
High-Z
Command Write
Figure 44. 3-lines Serial Reading Sequence
READING SEQUENCE
Write a "00000000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 9 pulses on SCLK and
Read the ID Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
DATA Read
1
.
LR0075
LR0080
33/66
STE2004S
4.3 Parallel Interface
The STE2004S selectable parallel Interfaces are 68000-series and 8080-series. They are both an 8-bits
bi-directional link between the display driver and the application supervisor.
Throughout both parallel interfaces can be read the I
4.3.1 68000-series parallel interface
is low after the positive edge of RES, the 68000 parallel interface is ready to receive or transmit data.
If CS
While CS
pin is high the 68000 Parallel interface is kept in reset.
4.3.1.1 Write Mode
If R/W line is set to 0 Data are latched on E falling edge.
4.3.1.2 Read Mode
When R/W line is set to 1, data are output on D0-D7 bus on E rising edge. Data Bus is set in high impedance mode when E is set to logic 0.
Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus.
Figure 45. 68000-series Parallel interface protocol - one byte transmission
CS
2
C driver slave address or the Status Byte.
R/W
D/C
E
D0
to
D7
LR0004
Figure 46. 68000-series Parallel interface bus protocol - Several bytes transmission
CS
R/W
D/C
E
34/66
D0
to
D7
LR0081
Figure 47. 68000-series Parallel interface protocol in Reading Mode
2
3
CS
D/C
R/W
E
D0
to
D7
LR008
Figure 48. 68000-series Parallel interface protocol in Reading Mode (Several Bytes)
CS
D/C
R/W
E
STE2004S
D0
to
D7
Note 1) Data Bus is configured in high impedence mode after evry RD rising edge
2) Always the same data is output on D0-D7
LR0046
4.3.2 8080-series parallel interface
If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or transmit data.
While CS
pin is high the 8080 Parallel interface is kept in reset.
4.3.2.1 Write Mode
Data are latched on WR rising edge.
4.3.2.2 Read Mode
Data are output on D0-D7 bus on RD rising edge. Data Bus is set in high impedance mode when RD is set to
logic 1.
Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus.
Figure 49. 8080-series parallel bus protocol - one byte transmission
CS
D/C
RD
WR
D0
to
D7
LR008
35/66
STE2004S
4
5
Figure 50. 8080-series parallel bus protocol - several bytes transmission
CS
D/C
RD
WR
D0
to
D7
Figure 51. 8080-series Parallel interface protocol in Reading Mode
CS
LR008
D/C
RD
WR
D0
to
D7
LR008
Figure 52. 8080-series Parallel interface protocol in Reading Mode (Several Bytes)
CS
D/C
RD
WR
D0
to
D7
Note 1) Data Bus is configured in high impedence mode after every RD rising edge
2) Always the same data is output on D0-D7
LR0045
36/66
STE2004S
5 INSTRUCTION SET
Two different instructions formats are provided:
- With D/C
- With D/C
Two different instruction set are embedded: the STE2001-like instruction set and the extended instruction
set. To select the STE2001-like instruction set the EXT pad has to be connected to a logic LOW (connect
to GND). To select the he extended instruction the EXT pad has to be connected to a logic HIGH (connect
to VDD1).
The instructions have the syntax summarized in Table 1 (basic-set) and Table 2 (extended set)
set to LOW : commands are sent to the Control circuitry.
set to HIGH : the Data RAM is addressed.
5.1 Reset (RES
)
At power-on, all internal registers are configured with the default value. The RAM content is not defined.
A Reset pulse on RES pad (active low) re-initialize the internal registers content (see Tables 3,4,5,&6).
Every on-going communication with the host controller is interrupted, applying a reset pulse. After the
power-on, the Software Reset instruction can be used to re-load the reset configuration into the internal
registers.
The Default configurations is:
- Horizontal addressing (V = 0)
- Normal instruction set (H[1:0] = 0)
- Normal display (MX = MY = 0)
- Display blank (E = D = 0)
- Address counter X[6: 0] = 0 and Y[4: 0] = 0
- Temperature coefficient (TC[1: 0] = 0)
- Frame Rate (FR[1:0]=”75Hz”)
- Power Down (PD = 1)
- Dual Partial Display Disabled (PE=0)
- V
=0
OP
- Y-CARRIAGE=8
- X-CARRIAGE=101
- Bias system (BS[2: 0] = 0)
- Multiplexing Ratio (M[1:0]=0 - MUX 65)
A MEMORY BLANK instruction can be executed to clear the DDRAM content.
5.2 P
ower Down (PD = 1)
When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and V
are OFF (V
LCDOUT
output is discharged to VSS, and then is possible to disconnect V
LCDOUT
generator
LCD
). The internal
Oscillator is in off state. An external clock can be provided. The RAM contents is not cleared.
5.3 Memory Blanking Procedure
This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly generated in memory when starting up the device. This instruction substitutes (102X8) single "write" instructions. It is possible to program "Memory Blanking Procedure" only under the following conditions:
- PD bit = 0
No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock).
The start of Memory blanking procedure will be between one and two fclock cycles from the last active
edge (E fallig edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL
rising edge for the I
2
C interface).
5.4 Checker Board Procedure
This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended to developers,
who can now simply obtain complex module test configuration by means of a single instruction. It is possible to program "Checker Board Procedure" only under the following conditions:
- PD bit = 0
37/66
STE2004S
No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock).
The start of Checker-board procedure will be between one and two fclock cycles from the last active edge
(E falling edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL
rising edge for the I
5.5 Scrolling Function
The STE2004S can scroll the graphics display in units of raster-rows. The scrolling function is achieved
changing the correspondence between the rows of the logical memory map and the output row drivers.
The scroll function doesn't affect the data ram content. It is only related to the visualization process. The
information output on the drivers is related to the row reading sequence (the 1st row read is output on R0,
the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every scrolling command the offset between the memory address and the
memory scanning pointer is increased or decreased by one. The offset range changes in accordance with
MUX Rate. After 64th/65th scrolling commands in MUX 65 mode, or after the 48th/49th scrolling commands in mux 49 mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the
memory address and the memory scanning pointer is again zero (Cyclic Scrolling).
A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the memory address and the memory scanning pointer
If ICON MODE =1, the Icon Row is not scrolled. If ICON MODE=0 the last row is like a general purpose
row and it is scrolled as other lines.
I
f the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top
down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled
from bottom-up.
2
C interface).
Table 8.
MUX RATE ICON MODE DESCRIPTION ICON Row Driver with MY=0
MUX 33 1 ICON ROW NOT SCROOLED
MUX 33 0 33 LINE GRAPHIC MATRIX
MUX 49 1 ICON ROW NOT SCROOLED
MUX 49 0 49 LINE GRAPHIC MATRIX
MUX 65 1 ICON ROW NOT SCROOLED
MUX 65 0 65 LINE GRAPHIC MATRIX
R48
R48
R56
R56
R64
R64
5.6 Dual Partial Display
If the PE Bit is set to a logic one the dual partial display mode is enabled.
Eight partial display modes are available. The offset of the two partial display zones is row by row programmable. The Icon row is accessed last in each partial display frame.
Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0], BS[2:0], CP[2:0].).
This allows switching from normal mode to partial display mode only with one instruction. The HV generator is automatically re configured using the parameters related to the enabled mode. The parameters of
the two sets of registers with the same function are located in the same position of the instruction set. The
registers related to the normal mode are accessible when normal mode (PE=0) is selected, the others are
accessible when the partial display mode is enabled (PE=1). To Setup PRS[1:0], Vop[6:0], BS[2:0],
CP[2:0] values the instruction flow proposed in Fig. 54 must be followed. To setup Partial Display Sectors
Start Address and Partial Display Mode no particular instruction flow has to be followed.
38/66
Figure 53. Dual Partial Display Enabling Instruction Flow
ENABLE DUAL PARTIAL DISPLAY
STE2004S
SET 1st Sector Start Address
SET 2nd Sector Start Address
SET PE=1
END OF ENABLING DUAL PARTIAL DISPLAY
OPTIONAL1
Figure 54. Dual Partial Display Mode configuration or Duty Change
SETUP PARTIAL DISPLAY CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Partial Display Mode (PE=1)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]
for Partial Display Operation
SET Partial Display Configuration (PDC[2:0])
SET 1st Sector Start Address
SET 2nd Sector Start Address
OPTIONAL
SET Driver in Normal Mode (PE=0)
END OF PARTIAL DISPLAY CONFIG.
Table 9. Partial Display Configurations
PDC2PDC1PDC
0
0 0 0 0 8 + Icon Row
0 0 1 8 0 + Icon Row
0 1 0 8 8 + Icon Row
0 1 1 0 16 + Icon Row 000
1 0 0 16 0 + Icon Row
1 0 1 8 16 + Icon Row
1 1 0 16 8 + Icon Row
1 1 1 16 16 + Icon Row
SECTION 1 SECTION2 RESET STATE
39/66
STE2004S
6ID-NUMBER
The STE2004S allows to program a Driver Identification Number (ID-Number). This make possible to easily manage on one platform more than one LCD module with different configuration parameters.
Four are the device ID-Numbers programmable: 00111100, 00111101, 0011110 & 0011111. All have in
common the first 6 bits (001111). The two least significant bit could be set connecting the SA0 and SA1
inputs to a VSS or VDD1.
The driver ID-number can be read through all communication interfaces. The way to read-out the ID-Number changes according the interface selected. The readout protocol for each interface is described in the
Bus interfaces paragraph.
Table 10. STE2001/2-like instruction Set
Instruction D/CR/
H=0 or H=1
Read Commnad0000000000
Function Set 0 0 0 0 1 MX MY PD V H[0] Power Down Management; Entry
Status Byte 0 1 PD
ID Code 0 1 0
Write Data 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Writes data to RAM
H=0
Memory Blank 0000000001Starts Memory Blank Procedure
Scroll 000000001DIR
Range Setting
V
LCD
Display Control 0000001D0E Select Display Configuration
Set CP Factor 0000010S2S1S0 Charge Pump Multiplication
Set RAM Y 0 0 0 1 0 0 Y3 Y2 Y1 Y0 Set Horizontal (Y) RAM Address
Set RAM X 0 0 1 X6X5X4X3X2X1X0 Set Vertical (X) RAM Address
H=1
Checker Board 0000000001Starts Checker Board Procedure
Duty 000000001
TC Select 00000001TC1TC0
Data Order 0000001DO
Bias Ratios 0000010BS2BS1BS0 Set desired Bias Ratios
Reserved 0 0 01XXXXXX Not to be used
Set V
OP
W
B7 B6 B5 B4 B3 B2 B1 B0
BSY 0
01
000000010
001
OP6 OP5 OP4 OP3 OP2 OP1 OP0
DEMXMYDO
111ID1ID0
00
Description
Read I2C Address or Status Byte
(with 3-Lines Serial & 4-lines SPI only)
Mode;
2
C interface only)
(I
Scrolls by one Row UP or DOWN
PRS
V
programming range selection
LDC
[0]
factor
MUX
Selects Duty factor
Set Temperature Coefficient for V
VOP register Write instruction
LDC
40/66
Table 11. Extended Instruction Set
Instruction D/C
Read Command0000000000
Status Byte 0 1 PD
ID Code 0 1 0
Write Data 1 0 D7 D6 D5 D4 D3 D2 D1 D0
Memory Blank 0000000001
Scroll 000000001DIR
V
Range Setting
LCD
Display Control 0000001D0E
Set CP Factor 0000010S2S1S0
Set RAM Y 000100Y3Y2Y1Y0
Set RAM X 0 0 1 X6X5X4X3X2X1X0
Checker Board 0000000001
TC Select 00000001TC1TC0
Data Order 0000001DO00
Bias Ratios 0000010BS2BS1BS0
Read Mode,
Set V
OP
Driver Control
Display Control
Partial Mode 0000010
R/W
B7 B6 B5 B4 B3 B2 B1 B0
H Independent Instructions
00001MXMYPDH[1]H[0]
BSY 0
01
DEMXMYDO
111ID1ID0
H=[0;0] RAM Commands
00000001
PRS
PRS
[1]
H=[0;1]
000000001V Vertical Addressing Mode
000100R000
001
OP6 OP5 OP4 OP3 OP2 OP1 OP0 VOP register Write instruction
H=[1;0]
0000000001 Software RESET
000000001PE
00000001FR1FR0
00000010M[1] M[0]
PDC2PDC1PDC
0001
001
PDY5PDY4PDY3PDY2PDY1PDY
PDY6PDY5PDY4PDY3PDY2PDY1PDY
H=[1;1]
0000000001 Scrolling Pointer Reset
000000001
00000001XX
0000001T2T1T0
000001
000100
001
XC-6 XC-5 XC-4 XC-3 XC-2 XC-1 XC-0
NW3NW2NW1NW0
YC-3 YC-2 YC-1 YC-0
Description
Read I2C Address or Status Byte
(with 3-Lines Serial & 4-lines SPI only)
Page selector, Power Down
Management; Entry Mode
Writes data to RAM
Starts Memory Blank Procedure
Scrolls by one Row UP or DOWN
V
programming range selection
LDC
[0]
Select Display Configuration
Charge Pump Multiplication factor
Set Horizontal (Y) RAM Address
Set Vertical (X) RAM Address
Starts Checker Board Procedure
Set Temperature Coefficient for V
MSB Position
Set desired Bias Ratios
Partial Enable
Frame rate Control
Mux Ratio
Partial Display Config
0
0
0
X
1st Sector Start Address
2nd Sector Star t Address
Not Used
Not Used
Set Temperature Coefficient for V
N-Line Inversion
Y-CARRIAGE RETURN
X CARRIAGE RETURN
STE2004S
LDC
LDC
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STE2004S
Table 12. Explanations of Table 3 & 4 symbols
BIT 0 1
DIR Scroll by one down Scroll by one up
H[0] Select page 0 Select page 1 0
PD Device fully working Device in power down 1
V Horizontal addressing Vertical addressing 0
MX Normal X axis addressing X axis address is mirrored. 0
MY Image is displayed not vertically mirrored Image is displayed vertically mirrored 0
DO MSB on TOP MSB on BOTTOM 0
PE Partial Display disabled Partial Display enabled 0
MUX MUx 65 Mode MUX 33 Mode 0
R Read ID-Number / I2C Address Read Status Byte 0
Table 13. PAGE SELECTION
H[1] H[0] DESCRIPTION RESET STATE
00Page 0
01Page 1 Page 0
10Page 2
11Page 3
RESET
STATE
Table 14. DISPLAY MODE
D E DESCRIPTION RESET STATE
0 0 display blank
0 1 all display segments on E=0
1 0 normal mode D=0
1 1 inverse video mode
Table 15. FRAME RATE CONTROL
FR[1] FR[0] DESCRIPTION RESET STATE
00 65Hz
0 1 70Hz 75Hz
10 75Hz
11 80Hz
Table 16. VLCD RANGE SELECTION
PRS[1] PRS[0] DESCRIPTION RESET STATE
0 0 2.94
0 1 6.78
10 10.62
11 10.62
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Table 17. MULTIPLEXING RATIO
M[1] M[0] DESCRIPTION RESET STATE
00 49
0 1 65 01
10 33
1 1 Not Allowed
Table 18. TEMPERATURE COEFFICIENT
T2 T1 T0 DESCRIPTION RESET STATE
0 0 0 VLCD temperature Coefficient 0
0 0 1 VLCD temperature Coefficient 1
0 1 0 VLCD temperature Coefficient 2
0 1 1 VLCD temperature Coefficient 3 000
1 0 0 VLCD temperature Coefficient 4
1 0 1 VLCD temperature Coefficient 5
1 1 0 VLCD temperature Coefficient 6
1 1 1 VLCD temperature Coefficient 7
Table 19.
TC1 TC0 DESCRIPTION RESET STATE
0 0 VLCD temperature Coefficient 0
0 1 VLCD temperature Coefficient 2 00
0 1 VLCD temperature Coefficient 3
1 1 VLCD temperature Coefficient 6
STE2004S
Table 20. CHARGE PUMP MULTIPLICATION FACTOR
CP2 CP1 CP0 DESCRIPTION RESET STATE
000
0 0 1 Multiplication Factor X3
0 1 0 Multiplication Factor X4
0 1 1 Multiplication Factor X5 000
100 NOT USED
101 NOT USED
110 NOT USED
111 AUTOMATIC
Multiplication Factor
X2
43/66
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Table 21. BIAS RATIO
BS2 BS1 BS0 DESCRIPTION RESET STATE
0 0 0 Bias Ratio equal to 7
0 0 1 Bias Ratio equal to 6
0 1 0 Bias Ratio equal to 5
0 1 1 Bias Ratio equal to 4 000
1 0 0 Bias Ratio equal to 3
1 0 1 Bias Ratio equal to 2
1 1 0 Bias Ratio equal to 1
1 1 1 Bias Ratio equal to 0
Table 22. Y CARRIAGE RETURN REGISTER
Y-C[3] Y-C[2] Y-C[1] Y-C[0] DESCRIPTION RESET STATE
0 0 0 0 Y-CARRIAGE =0
0 0 0 1 Y-CARRIAGE =1
0 0 1 0 Y-CARRIAGE =2
0 0 1 1 Y-CARRIAGE =3 1000
0 1 0 0 Y-CARRIAGE =4
....
0 1 1 0 Y-CARRIAGE =6
0 1 1 1 Y-CARRIAGE =7
1 0 0 0 Y-CARRIAGE =8
Table 23. PARTIAL DISPLAY CONFIGURATION
PD2 PD1 PD0 SECTION 1 SECTION2 RESET STATE
0 0 0 0 8 + Icon Row
0 0 1 8 0 + Icon Row
0 1 0 8 8 + Icon Row
0 1 1 0 16 + Icon Row 000
1 0 0 16 0 + Icon Row
1 0 1 8 16 + Icon Row
1 1 0 16 8 + Icon Row
1 1 1 16 16 + Icon Row
Table 24. N-LINE INVERSION
NW3 NW2 NW1 NW0 DESCRIPTION RESET STATE
0000 0-Line Inversion
0001 2-Line Inversion
0010 3-Line Inversion
0 0 1 1 4-Line Inversion 0000
:::: :
1110 15-Line Inversion
1111 16-Line Inversion
(Frame Inversion)
44/66
Figure 55. I2C Interface Interconnection in Master/ Slave Mode
5
6
STE2004S
STE2004S
RES
RES
SCL SDAOUT
SCL SDA
SDAIN
STE2004S
RES
SDAINSCL SDAOUT
LR0214
NOTE:
MASTER and SLAVE I2C AADDRESS
MUST BE DIFFERENT
Figure 56. I3-lines SPI & 3-lines Serial Interfaces Interconnection in Master Slave Mode
STE2004S
SCLK SDIN
CS
RES
SCLK SLAVE
MASTER
RES
CS
SDOUT
SD
CS
STE2004S
CSRES
SDOUTSCLK SDIN
LR021
Figure 57. 4-lines SPI Interface Interconnection in Master Slave Mode
STE2004S
D/CCSRES
RES
MASTER
CS
D/C
SCLK SDIN
SCLK SLAVE
SDOUT
SD
CS
STE2004S
D/C CSRES
SDOUTSCLK SDIN
LR021
45/66
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7
0
Figure 58. 8080-series & 68000-series Interface Interconnection in Master Slave Mode
STE2004S
E-WR
E-WRRW-RDD/C
D7-D0
D7-D0
8 LINES
CS
RW-RD
MASTER
CS
D/CCS
RES
RES SLAVE
STE2004S
D/C
RES
Figure 59. Host Processor Interconnection with I2C Interface
VSS
TEST_MODE
VSSAUX
D0
D1
STE2004S
D2
D3
D4
D5
D6
D7
SCLK -SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON VDD1 / VSSAUX
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
ANALOG VDD
DIGITAL VDD
VSSAUX
VDD1 / VSSAUX
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
E-WR
D7-D0
8 LINES
LR021
RW-RD
CS
µP
LR011
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Figure 60. Host Processor Interconnection with 4-line SPI Interface
2
VSS
TEST_MODE
VSSAUX
D0
D1
STE2004S
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON VDD1 / VSSAUX
SEL1
SEL2
SEL3
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
ANALOG VDD
DIGITAL VDD
VDD1
VSSAUX
VDD1 / VSSAUX EXT_SET
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
STE2004S
µP
LR0111
Figure 61. Host Processor Interconnection with 3-line SPI Interface
VSS
TEST_MODE
VSSAUX
D0
D1
STE2004S
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON VDD1 / VSSAUX
SEL1
SEL2
SEL3
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
ANALOG VDD
DIGITAL VDD
VSSAUX
VDD1
VSSAUX
VDD1 / VSSAUX EXT_SET
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
µP
LR011
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STE2004S
3
4
Figure 62. Host Processor Interconnection with 3-line Serial Interface
VSS
STE2004S
TEST_MODE
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON VDD1 / VSSAUX
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
ANALOG VDD
DIGITAL VDD
VDD1
VDD1
VSSAUX
VDD1 / VSSAUX
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
µP
LR011
Figure 63. Host Processor Interconnection with 8080-series Parallel Interface
VSS
STE2004S
VSENSE_SLAVE
TEST_MODE
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON VDD1 / VSSAUX
SEL1
SEL2
SEL3
M/S
SA0
SA1
VSSAUX
TEST VREF
OSC_IN
FR_IN
VDD1_AUX
ANALOG VDD
DIGITAL VDD
VSSAUX
VSSAUX
VDD1
VDD1 / VSSAUX EXT_SET
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
µP
LR011
48/66
Figure 64. Host Processor Interconnection with 6800
5
VSS
TEST_MODE
VSSAUX
D0
D1
STE2004S
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON VDD1 / VSSAUX
SEL1
SEL2
SEL3
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
ANALOG VDD
DIGITAL VDD
VDD1
VSSAUX
VDD1
VDD1 / VSSAUX EXT_SET
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
STE2004S
µP
LR011
49/66
STE2004S
Figure 65.
Application Schematic using the Internal LCD Voltage Generator and two separate supplies
I/O
V
DD2
V
DD1
1µF1µF
V
SS
1µF
VDD2
VDD1
VSS
VLCDSENSE
VLCD
32
102
33
65 x 102
DISPLAY
Figure 66. Application Schematic using the Internal LCD Voltage Generator and a single supply
I/O
V
1µF
V
1µF
DD
SS
VDD2
VDD1
VSS
VLCDSENSE
VLCD
32
102
33
65 x 102
DISPLAY
50/66
Figure 67. Power-ON timing diagram
8
VDD2
VDD1
RES
CS
SCLK
SDIN
D/C
E
R/W
D0 - D7
HOST
STE2004S
T
vdd
T
logic(res)Tw(res)
D0 - D7
Hi-Z
DRIVER
SCL- SDAIN
SDOUT -
Hi-Z
SDA OUT
OSCIN, FR_IN
(HOST)
OSC OUT, FR_OUT
(DRIVER)
BOOSTER
OFF
RESET
Acceptance
Time
POWER ON
INTERNAL
RESET
LR020
51/66
STE2004S
7
Figure 68. Power-OFF timing diagram
VDD2
VDD1
RES
CLK-SCL
SDIN-SDAIN
D/C
E
CS
TVDD
R/W
D0 - D7
HOST
D0 - D7
DRIVER
SDOUT
SDA-OUT
OSCIN
(HOST)
OSC OUT
FR_OUT
(DRIVER)
FR_IN
RESET
TABLE
LOADED
Hi-Z
Hi-Z
LR020
52/66
Figure 69. Initialization with built-in Booster
8
SETUP NORMAL DISPLAY MODE CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Normal Display Mode (PE=0)
STE2004S
SET Operative Voltage for Normal Display Operation
( Vop[6:0] - PRS[1;0])
SET Bias Raio for Normal Display Operation
(BS[2:0])
SET Temperature Compensation for
Normal Display Operation (T[2:0] or TC[1:0])
SET Multiplexing Rate
M[1:0)
SET Charge Pump for
Normal Display Operation (CP[1:0])
Switch "ON" Booster and Display Control Logic
(PD=0)
END OF NORMAL DISPLAY MODE CONFIG.
LR021
53/66
STE2004S
Figure 70. DATA RAM to display Mapping
DISPLAY DATA RAM
bank
0
bank
1
bank
2
bank
3
bank
7
bank
8
GLASS
TOP VIEW
DISPLAY DATA RAM = "1"
DISPLAY DATA RAM = "0"
LCD
ICOR ROW
Table 25. Test Pin Configuration
Test Pin Pin Configuration
TEST_VREF OPEN
TEST_MODE GND
54/66
D00IN1155
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Table 26. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DD1
V
DD2
V
LCD
I
SS
V
I
in
I
out
P
tot
P
T
T
stg
Table 27. ELECTRICAL CHARACTERISTICS
DC OPERATION
(V
= 1.7 to 3.6 V; V
DD1
Symbol Parameter Test Condition Min. Typ. Max. Unit
Supply Voltages
V
DD1
V
DD2
V
LCD
I(V
DD1
I(V
DD2
I(V
DD1,2
I(V
LDCIN
Logic Outputs
V
0H
V
OL
Supply Voltage Range - 0.5 to + 5 V
Supply Voltage Range - 0.5 to + 7 V
LCD Supply Voltage Range - 0.5 to + 15 V
Supply Current - 50 to +50 mA
Input Voltage (all input pads) -0.5 to V
i
+ 0.5 V
DD1
DC Input Current - 10 to + 10 mA
DC Output Current - 10 to + 10 mA
Total Power Dissipation (Tj = 85°C) 300 mW
Power Dissipation per Output 30 mW
o
Operating Junction Temperature -40 to + 85 °C
j
Storage Temperature - 65 to 150 °C
= 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
DD2
Supply Voltage Note 9 1.7 3.6 V
Supply Voltage LCD Voltage Internally
1.75 4.5 V
generated
LCD Supply Voltage LCD Voltage Supplied externally 4.5 14.5 V
LCD Supply Voltage Internally generated; note 1 4.5 14.5 V
) Supply Current V
f
sclk
DD1
= 2.8V; V
= 0;T
amb
= 10V;
LCD
= 25°C;
15 20 40 µA
Parallel Port; note 3,8.
Supply Current Write Mode V
f
sclk
DD2
= 2.8V; V
= 1Mhz;T
LCD
= 25°C;
amb
= 10V;
100 200 µA
OSC_IN=GND; Note8.
) Voltage Generator Supply
Current
with VOP = 0 and PRS = [0:0]
with external V
V
= 2.8V; V
DD2
f
=0; T
sclk
LCD
= 10V;
LCD
= 25°C; no display
amb
60 150 µA
load; 5x charge pump; note
2,3,6,
) Total Supply Current V
= 2.8V; V
DD2
charge pump; f
T
= 25°C; no display load;
amb
LCD
sclk
= 0;
= 10V; 5x
80 190 µA
note 2, 3, 6
Power down Mode with internal
315µA
or External VLCD. Note 4
) External LCD Supply Voltage
Current
High logic Level Output Voltage IOH=-500µA
Low logic Level Output Voltage IOL=+500µA
VDD =2.8V; V
display load; f
T
= 25°C; note 3.
amb
=10V;no
LCD
= 0;
sclk
0.8V
DD1
V
SS
0.2V
V
DD2
5 µA
25 µA
V
DD1
DD1
V
V
V
55/66
STE2004S
DC OPERATION
(V
= 1.7 to 3.6 V; V
DD1
(continued)
= 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
DD2
Symbol Parameter Test Condition Min. Typ. Max. Unit
Logic Inputs
V
V
I
Logic LOW voltage level
IL
Logic HIGH Voltage Level 0.7
IH
Input Current Vin = V
in
SS1
or V
DD1
V
V
DD1
SS
V
V
0.3
DD1
DD2
-1 1 µA
Logic Inputs/Outputs
V
V
Logic LOW voltage level V
IL
Logic HIGH Voltage Level 0.7
IH
V
SS
DD1
V
0.3
V
DD1
0.5
DD1
+
Column and Row Driver
R
R
V
V
ROW Output Resistance 3K 5K kohm
row
Column Output resistance 5K 10K kohm
col
Column Bias voltage accuracy No load -50 +50 mV
col
Row Bias voltage accuracy -50 +50 mV
row
LCD Supply Voltage
V
LCD
LCD Supply Voltage accuracy;
Internally generated
VDD = 2.8V; V
fsclk=0; T
amb
= 10V;
LCD
=25 C; no display
-2 +2 %
load;note 2, 3, 6 & 7, VOP=69h,
PRS=2Hex
TC0 Temperature coefficient -0.0·
-3
10
TC1 -0.35 ·
-3
10
TC2 -0.7 ·
-3
10
TC3 -1.05·
-3
10
TC4 -1.4 ·
-3
10
TC5 -1.75·
-3
10
TC6 -2.1 ·
-3
10
TC7 -2.3·
-3
10
Notes: 1. The maximum possible V
2. Internal clock
3. When f
4. Power-down mode. During power-down all static currents are switched-off.
5. If external V
6. Tolerance depends on the temperature; (typically zero at T
ature range limit.
7. For TC0 to TC7
8. Data Byte Writing Mode
9. VDD1<=VDD2
= 0 there is no interface clock.
sclk
, the display load current is not transmitted to I
LCD
voltage that can be generated is dependent on voltage, temperature and (display) load.
LCD
DD
= 27°C), maximum tolerance values are measured at the temper-
amb
V
V
V
V
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
56/66
STE2004S
9
AC OPERATION
(VDD1 =
Figure 71. RESET timing diagram
1.7 to 3.6 V;
VDD2 =
1.75
to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INTERNAL OSCILLATOR
F
OSC
Internal Oscillator frequency VDD = 2.8V;
61 72 83 kHz
Tamb = -20 to +70 °C
F
F
FRAME
T
w(RES)
EXT
External Oscillator frequency 20 100 kHz
Frame frequency fosc or fext = 72 kHz; note 1 75 Hz
RES LOW pulse width 5 µs
Reset Pulse Rejection 1 µs
T
LOGIC
(RES)
T
VDD
Internal Logic Reset Time 5 µs
VDD1 vs. VDD2 Delay 0 µs
VDD2
VDD1
RES
INPUTS
I/O
(HOST)
I/O
(DRIVER)
INTERFACE
OUTPUT
OSCIN
FR_IN
(HOST)
OSC OUT
FR_OUT
(DRIVER)
Tw(res)
Hi-Z
Hi-Z
RESET
TABLE
LOADED
Tlogic(res)
LR020
57/66
STE2004S
AC OPERATION
(continued)
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
2
I
C BUS INTERFACE (See note 4, 7)
F
T
SU;STA
SCL
SCL Clock Frequency Fast Mode DC 400 kHz
DC 3.4 MHz
DC 1.7 MHz
Set-up time (repeated) START
High Speed Mode; Cb=100pF
(max);note 6;V
DD1=2
High Speed Mode; Cb=400pF
(max);note 6; V
Fast Mode; note 6; V
DD1=2
DD1=1.7V 400 KHz
Note 2,3, Cb = 100pF 160 ns
Condition
T
HD;STA
Hold Time (repeated) START
Note 2,3, Cb = 100pF 160 ns
Condition
T
LOW
T
HIGH
T
SU;DAT
T
HD;DAT
T
r;CL
T
r;CL1
Low Period of SCLH Clock Note 2,3, Cb = 100pF 160 ns
HIGH Period of SCLH Clock Note 2,3, Cb = 100pF 160 ns
Data set-up Time Note 2,3, Cb = 100pF 60 ns
Data Hold Time Note 2,3, Cb = 100pF 10 ns
Rise Time of SCLH Signal Note 2,3, Cb = 100pF 10 ns
Rise Time of SCLH Signal after
Note 2,3, Cb = 100pF 10 ns
a repeated START condition and
aftyer an Acknowledge bit
T
f;CL
T
r;DA
T
f;DA
T
r;DA
T
f;DA
T
SU;STO
Cb
Fall time of SCLH signal Note 2,3, Cb = 100pF 10 ns
Rise time of SCLH signal Note 2,3, Cb = 100pF 10 ns
Fall time of SDAH signal Note 2,3, Cb = 100pF 10 80 ns
Rise Time of SDAH signal Note 2,3, Cb = 400pF 20 ns
Fall Time of SDAH signal Note 2,3, Cb = 400pF 20 160 ns
Setup Time for STOP condition Note 2,3, Cb = 100pF 160 ns
Capacitive Load for SDAH and
100 400 pF
SCLH
Cb
Capacitive Load for SDAH
400 pF
+SDA line and SCLH +SCL Line
Figure 72.
SDAH
SCLH
58/66
I2C-bus timings
Sr
t
fDA
t
SU;STA
= MCS current source pull-up
= Rp resistor pull-up
t
HD;STA
t
t
rCL
t
rDA
HD;DAT
t
t
fCL
HIGH
t
LOW
t
SU;DAT
t
rCL1
(1) (1)
t
t
LOW
HIGH
t
rCL1
Sr P
LR0093
STE2004S
ELECTRICAL CHARACTERISTICS
(continued)
AC OPERATION
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
PARALLEL INTERFACE
T
T
T
CHW
T
T
T
EWHW
T
EWLW
T
EWHR
T
EWLR
T
SU(A)
T
T
T
T
T
CYC
CLW
CLR
CHR
H(A)
SU1
SU2
System Cycle Time V
= 1.7V; Read & Write 125 ns
DD1
Control Low Pulse Width (WR) 20 ns
Control High Pulse Width (WR) 75 ns
Control Low Pulse Width (RD) 40 ns
Control High Pulse Width (RD) 55 ns
Enable High Pulse Width (Write) 60 ns
Enable Low Pulse Width (Write) 60 ns
Enable High Pulse Width (Read) 60 ns
Enable Low Pulse Width (Read) 60 ns
Address Set-up Time 10 ns
Address Hold Time 10 ns
Data Set-Up Time 30 ns
Data Hold Time 30 ns
H1
Read Access Time 40 ns
Output Disable Time 0 30 ns
H2
Figure 73. 68000-series Parallel interface timing
D/C
R/W
CS
E
D0 to D7
(Write)
D0 to D7
(Read)
t
SU(A)
Figure 74. 8080-series parallel Interface timing
D/C
t
SU(A)
CS
WR, RD
D0 to D7
(Write)
D0 to D7
(Read)
t
t
EWHR
SU2
t
t
H(A)
t
CYC
,
t
EWHW
t
EWLR
,
t
EWLW
t
SU1
t
CLR
, t
CLW
t
SU1
SU2
t
H1
t
H2
t
H (A)
t
CYC
t
CHR
, t
CHW
t
H1
t
H2
59/66
STE2004S
AC OPERATION
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SERIAL INTERFACE
F
SCLK
T
CYC
T
PWH1
T
PWL1
T
S2
T
H2
T
PWH2
T
S3
T
H3
T
S4
T
H4
T
S5
T
H5
T
H6
Clock Frequency V
= 1.7V; 8 MHz
DD1
Clock Cycle SCLK 125 ns
SCLK pulse width HIGH 60 ns
SCLK Pulse width LOW 60 ns
CS setup time V
= 1.7V 40 ns
DD1
CS hold time 50 ns
CS minimum high time 50 ns
SD/C setup time 30 ns
SD/C hold time 30 ns
SDIN setup time 30 ns
SDIN hold time 40 ns
SDOUT Access Time 30 ns
SDOUT Disable Time vs. SCLK 0 20 ns
SDOUT Disable Time vs. CS 0 20 ns
Figure 75. Serial interface Timing
t
S2
CS
t
H3
t
t
S4
H4
t
H5
Notes: 1.
F
frame
f
osc
----------=
960
D/C
SCLK
SDIN
SOUT
t
S3
t
PWL1tWH1
t
S5
2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V
an input voltage swing of V
3. Cb is the capacitive load for each bus line.
to V
SS
DD
4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
5. C
6. Trise and Tfall (30%-70%) -10ns
7. I
is the filtering CApacitor on VLCD
VLCD
2
C bus AC Characteristics are tested by correlation
t
H2
t
CYC
t
PWH2
t
S2
t
H6
LR0096
and VIH with
IL
60/66
STE2004S
Table 28. Pad Coordinates
NAME PAD X (µm) Y(µm)
R5 1 -2632.5 -532.8
R4 2 -2587.5 -532.8
R3 3 -2542.5 -532.8
R2 4 -2497.5 -532.8
R1 5 -2452.5 -532.8
R0 6 -2407.5 -532.8
C0 7 -2362.5 -532.8
C1 8 -2317.5 -532.8
C2 9 -2272.5 -532.8
C3 10 -2227.5 -532.8
C4 11 -2182.5 -532.8
C5 12 -2137.5 -532.8
C6 13 -2092.5 -532.8
C7 14 -2047.5 -532.8
Table 28. Pad Coordinates (continued)
NAME PAD X (µm) Y(µm)
C25 32 -1237.5 -532.8
C26 33 -1192.5 -532.8
C27 34 -1147.5 -532.8
C28 35 -1102.5 -532.8
C29 36 -1057.5 -532.8
C30 37 -1012.5 -532.8
C31 38 -967.5 -532.8
C32 39 -922.5 -532.8
C33 40 -877.5 -532.8
C34 41 -832.5 -532.8
C35 42 -787.5 -532.8
C36 43 -742.5 -532.8
C37 44 -697.5 -532.8
C38 45 -652.5 -532.8
C8 15 -2002.5 -532.8
C9 16 -1957.5 -532.8
C10 17 -1912.5 -532.8
C11 18 -1867.5 -532.8
C12 19 -1822.5 -532.8
C13 20 -1777.5 -532.8
C14 21 -1732.5 -532.8
C15 22 -1687.5 -532.8
C16 23 -1642.5 -532.8
C17 24 -1597.5 -532.8
C18 25 -1552.5 -532.8
C19 26 -1507.5 -532.8
C20 27 -1462.5 -532.8
C21 28 -1417.5 -532.8
C22 29 -1372.5 -532.8
C23 30 -1327.5 -532.8
C39 46 -607.5 -532.8
C40 47 -562.5 -532.8
C41 48 -517.5 -532.8
C42 49 -472.5 -532.8
C43 50 -427.5 -532.8
C44 51 -382.5 -532.8
C45 52 -337.5 -532.8
C46 53 -292.5 -532.8
C47 54 -247.5 -532.8
C48 55 -202.5 -532.8
C49 56 -157.5 -532.8
C50 57 -112.5 -532.8
C51 58 112.5 -532.8
C52 59 157.5 -532.8
C53 60 202.5 -532.8
C54 61 247.5 -532.8
C24 31 -1282.5 -532.8
C55 62 292.5 -532.8
61/66
STE2004S
Table 28. Pad Coordinates (continued)
NAME PAD X (µm) Y(µm)
C56 63 337.5 -532.8
C57 64 382.5 -532.8
C58 65 427.5 -532.8
C59 66 472.5 -532.8
C60 67 517.5 -532.8
C61 68 562.5 -532.8
C62 69 607.5 -532.8
C63 70 652.5 -532.8
C64 71 697.5 -532.8
C65 72 742.5 -532.8
C66 73 787.5 -532.8
C67 74 832.5 -532.8
C68 75 877.5 -532.8
C69 76 922.5 -532.8
Table 28. Pad Coordinates (continued)
NAME PAD X (µm) Y(µm)
C87 94 1732.5 -532.8
C88 95 1777.5 -532.8
C89 96 1822.5 -532.8
C90 97 1867.5 -532.8
C91 98 1912.5 -532.8
C92 99 1957.5 -532.8
C93 100 2002.5 -532.8
C94 101 2047.5 -532.8
C95 102 2092.5 -532.8
C96 103 2137.5 -532.8
C97 104 2182.5 -532.8
C98 105 2227.5 -532.8
C99 106 2272.5 -532.8
C100 107 2317.5 -532.8
C70 77 967.5 -532.8
C71 78 1012.5 -532.8
C72 79 1057.5 -532.8
C73 80 1102.5 -532.8
C74 81 1147.5 -532.8
C75 82 1192.5 -532.8
C76 83 1237.5 -532.8
C77 84 1282.5 -532.8
C78 85 1327.5 -532.8
C79 86 1372.5 -532.8
C80 87 1417.5 -532.8
C81 88 1462.5 -532.8
C82 89 1507.5 -532.8
C83 90 1552.5 -532.8
C84 91 1597.5 -532.8
C85 92 1642.5 -532.8
C101 108 2362.5 -532.8
R32 109 2407.5 -532.8
R33 110 2452.5 -532.8
R34 111 2497.5 -532.8
R35 112 2542.5 -532.8
R36 113 2587.5 -532.8
R37 114 2632.5 -532.8
R38 115 2773.8 -472.5
R39 116 2773.8 -427.5
R40 117 2773.8 -382.5
R41 118 2773.8 -337.5
R42 119 2773.8 -292.5
R43 120 2773.8 -247.5
R44 121 2773.8 -202.5
R45 122 2773.8 -157.5
R46 123 2773.8 -112.5
C86 93 1687.5 -532.8
62/66
R47 124 2773.8 -67.5
STE2004S
Table 28. Pad Coordinates (continued)
NAME PAD X (µm) Y(µm)
R48 125 2773.8 -22.5
R49 126 2773.8 22.5
R50 127 2773.8 67.5
R51 128 2773.8 112.5
R52 129 2773.8 157.5
R53 130 2773.8 202.5
R54 131 2773.8 247.5
R55 132 2773.8 292.5
R56 133 2773.8 337.5
R57 134 2773.8 382.5
R58 135 2773.8 427.5
R59 136 2773.8 472.5
R60 137 2632.5 532.8
R61 138 2587.5 532.8
Table 28. Pad Coordinates (continued)
NAME PAD X (µm) Y(µm)
VDD1 156 1327.5 532.8
VDD1 157 1282.5 532.8
VDD1 158 1237.5 532.8
VDD1 159 1192.5 532.8
VDD1 160 1147.5 532.8
VDD1 161 1102.5 532.8
VDD1 162 1057.5 532.8
VDD1 163 1012.5 532.8
VDD2 164 967.5 532.8
VDD2 165 922.5 532.8
VDD2 166 877.5 532.8
VDD2 167 832.5 532.8
VDD2 168 787.5 532.8
VDD2 169 742.5 532.8
R62 139 2542.5 532.8
R63 140 2497.5 532.8
R64/ICON 141 2452.5 532.8
VDD1 AUX 142 2227.5 532.8
FR IN 143 2182.5 532.8
OSC IN 144 2137.5 532.8
Vsns_Slave 145 2092.5 532.8
TEST_VREF
VSSAUX 147 1732.5 532.8
SA1 148 1687.5 532.8
SA0 149 1642.5 532.8
M/S 150 1597.5 532.8
EXT_SET 151 1552.5 532.8
SEL3 152 1507.5 532.8
SEL2 153 1462.5 532.8
SEL1 154 1417.5 532.8
146 1777.5 532.8
VDD2 170 697.5 532.8
VDD2 171 652.5 532.8
_RES 172 337.5 532.8
-CS 173 247.5 532.8
D/C 174 157.5 532.8
RW-RD 175 67.5 532.8
E-WR 176 -22.5 532.8
VSSAUX 177 -67.5 532.8
SDA_OUT 178 -157.5 532.8
SDIN_SDAIN
SDOUT 180 -247.5 532.8
SCLK_SCL 181 -337.5 532.8
D7 182 -382.5 532.8
D6 183 -427.5 532.8
D5 184 -472.5 532.8
D4 185 -517.5 532.8
179 -202.5 532.8
ICON 155 1372.5 532.8
D3 186 -562.5 532.8
63/66
STE2004S
Table 28. Pad Coordinates (continued)
NAME PAD X (µm) Y(µm)
D2 187 -607.5 532.8
D1 188 -652.5 532.8
D0 189 -697.5 532.8
VSSAUX 190 -742.5 532.8
TEST_MODE
VSS 192 -1147.5 532.8
VSS 193 -1192.5 532.8
VSS 194 -1237.5 532.8
VSS 195 -1282.5 532.8
VSS 196 -1327.5 532.8
VSS 197 -1372.5 532.8
VSS 198 -1417.5 532.8
VSS 199 -1462.5 532.8
VSS 200 -1507.5 532.8
191 -1102.5 532.8
Table 28. Pad Coordinates (continued)
NAME PAD X (µm) Y(µm)
R26 217 -2773.8 427.5
R25 218 -2773.8 382.5
R24 219 -2773.8 337.5
R23 220 -2773.8 292.5
R22 221 -2773.8 247.5
R21 222 -2773.8 202.5
R20 223 -2773.8 157.5
R19 224 -2773.8 112.5
R18 225 -2773.8 67.5
R17 226 -2773.8 22.5
R16 227 -2773.8 -22.5
R15 228 -2773.8 -67.5
R14 229 -2773.8 -112.5
R13 230 -2773.8 -157.5
VSS 201 -1552.5 532.8
VSS 202 -1597.5 532.8
VSS 203 -1642.5 532.8
VLCD_SNS 204 -1867.5 532.8
VLCD 205 -1912.5 532.8
VLCD 206 -1957.5 532.8
VLCD 207 -2002.5 532.8
VLCD 208 -2047.5 532.8
VLCD 209 -2092.5 532.8
OSC_OUT 210 -2227.5 532.8
FR_OUT 211 -2272.5 532.8
R31 212 -2497.5 532.8
R30 213 -2542.5 532.8
R29 214 -2587.5 532.8
R28 215 -2632.5 532.8
R27 216 -2773.8 472.5
R12 231 -2773.8 -202.5
R11 232 -2773.8 -247.5
R10 233 -2773.8 -292.5
R9 234 -2773.8 -337.5
R8 235 -2773.8 -382.5
R7 236 -2773.8 -427.5
R6 237 -2773.8 -472.5
Table 29. Alignment marks coordinates
MARKS X Y
mark1 -2780.55 -539.55
mark2 2780.55 -539.55
mark3 -2160.0 539.55
mark4 484.89 539.55
64/66
Figure 76. Alignment marks dimensions Table 30. Bumps
Bump
Number
STE2004S
Dimensions
35 µm
85 µm
Table 32. Revision History
Date Revision Description of Changes
September 2005 1 First Issue
Bumps Size
Pad Size
Pad Pitch
Spacing between
Bumps
28µmX97µmX17.5µm
35µm X 104µm
45µ
m
17µm
Table 31. Die Mechanical Dimensions
Die Size (X x Y) 5.815mm x 1.333m
Wafers Thickness 500µm
m
65/66
STE2004S
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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66/66
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