ST STE2004S User Manual

STE2004S

102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER

1 FEATURES

■102 x 65 bits Display Data RAM

■Programmable MUX rate

■Programmable Frame Rate

■X,Y Programmable Carriage Return

■Dual Partial Display Mode

■Row by Row Scrolling

■N-line Inversion

■Automatic data RAM Blanking procedure

■Selectable Input Interface:

•I2C Bus Fast and Hs-mode (read and write)

•68000 & 8080 Parallel Interfaces (read and write)

•3-lines and 4-lines SPI Interface (read and write)

•3-lines 9 bit Serial Interface (read and write)

■Fully Integrated Oscillator requires no external components

■CMOS Compatible Inputs

■Fully Integrated Configurable LCD bias voltage generator with:

•Selectable multiplication factor (up to 5X)

•Effective sensing for High Precision Output

•Eight selectable temperature compensation coefficients

■Designed for chip-on-glass (COG) applications.

Figure 1. Block Diagram

■Low Power Consumption, suitable for battery operated systems

■Logic Supply Voltage range from 1.7 to 3.6V

■High Voltage Generator Supply Voltage range from 1.75 to 4.5V

■Display Supply Voltage range from 4.5 to 14.5V

■Backward Compatibility with STE2001/2/4

2 DESCRIPTION

The STE2004S is a low power CMOS LCD controller driver. Designed to drive a 65 rows by 102 columns graphic display, it provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption.

STE2004S features six standard interfaces (3- lines Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel, 8080 parallel & I2C) for ease of interfacing with the host micro-controller.

Table 1. Order Codes

Part Numbers	Type
STE2004S DIE2	Bumped Dice on Waffle Pack

				CO to C101			R0 to R64
OSC_IN	OSC		TIMING
OSC_OUT		GENERATOR
				COLUMN				ROW
FR_IN	MASTER			DRIVERS			DRIVERS
FR_OUT	SLAVE SYNC			CLOCK
	BIAS VOLTAGE			DATA			SHIFT
	GENERATOR
				LATCHES			REGISTER
VSENSE SLAVE	HIGH VOLTAGE
VLCD
	GENERATOR
				65 x 102
VLCDSENSE							SCROLL
				RAM			LOGIC
RES	RESET
								TEST		TEST_MODE
VSSAUX										TEST_VREF
VDD1,2		DATA		INSTRUCTION		DISPLAY				ICON_MODE
						CONTROL
		REGISTER		REGISTER						EXT
VSS						LOGIC
										SEL 3
	I2C BUS	9 Bit SERIAL		3 & 4 Line SPI	Parallel 8080		Parallel 68K			SEL 2
										SEL 1
	SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0					E/WR R/W- RD		D/C	CS	LR0047
					to
					DB7

	Rev. 1
September 2005	1/66

STE2004S

Table 2. PIN DESCRIPTION

N°

Pad

Type

Function

R0 to R64

1-6

O

LCD Row Driver Output

109-141

C0 to C101

6-107

O

LCD Column Driver Output

VSS

192-203

GND

Ground pads.

VDD1

156-163

Supply

IC Positive Power Supply

VDD2

164-171

Supply

Internal Generator Supply Voltages.

VLCD

205-209

Supply

Voltage Multiplier Output

VLCDSENSE

204

Supply

Voltage Multiplier Regulation Input. VLCDOUT Sensing for Output Voltage Fine Tuning

VSENSE_SLAVE

145

Supply

Voltage reference for SLAVE CHARGE PUMP

VSSAUX

190-177-

O

Ground Reference for Pins Configuration

147

VDD1AUX

142

O

VDD1 Reference for Pins Configuration

SEL1,2,3

152

I

Interface Mode Selection - CANNOT BE LEFT FLOATING

153

SEL3

SEL2

SEL1

Interface

154

GND / VSSAUX

GND / VSSAUX

GND / VSSAUX

I2C

GND / VSSAUX

GND / VSSAUX

VDD1

SPI 4-Lines 8 bit

GND / VSSAUX

VDD1

GND / VSSAUX

SPI 3-Lines 8 bit

GND / VSSAUX

VDD1

VDD1

Serial 3-Lines 9 bit

VDD1

GND / VSSAUX

GND / VSSAUX

Parallel 8080-series

VDD1

GND / VSSAUX

VDD1

Parallel 68000-series

EXT_SET

151

I

Extended Instruction Set Selection - CANNOT BE LEFT FLOATING

EXT PAD CONFIG

INSTRUCTION SET SELECTED

GND or VSSAUX

BASIC

VDD1

EXTENDED

ICON_MODE

155

I

Extended Instruction Set Selection - CANNOT BE LEFT FLOATING

ICON MODE PAD CONFIG

ICON MODE STATUS

GND or VSSAUX

DISBLED

VDD1

ENABLED

SDOUT

180

O

Serial & SPI Data Output - IF UNUSED MUST BE LEFT FLOATING

SDIN - SDAIN

179

I

SDIN - Serial & SPI Interface Data Input - CANNOT BE LEFT FLOATING

I

SDAIN - I2C Bus Data In - CANNOT BE LEFT FLOATING

SCLK - SCL

181

I

SCLK - Serial & SPI Interface Clock - CANNOT BE LEFT FLOATING

I

SCL - I2C bus Clock - CANNOT BE LEFT FLOATING

SDA_OUT

178

O

I2C Bus Data Out IF UNUSED MUST BE LEFT FLOATING

SA0

149

I

I2C Slave Address BIT 0 - CANNOT BE LEFT FLOATING

SA1

148

I

I2C Slave Address BIT 1- CANNOT BE LEFT FLOATING

DB0 to DB7

182-189

I/O

Parallel Interface 8 Bit Data Bus - CANNOT BE LEFT FLOATING

R/W

- RD

175

I

R/W - 68000 Series Parallel Interface Read & Write Control Input

- CANNOT BE LEFT FLOATING

I

RD

- 8080 Series Parallel Interface Read enable Clock Input

- CANNOT BE LEFT FLOATING

E /

176

I

E - 68000 Series Parallel Interface Read & Write Clock Input

WR

- CANNOT BE LEFT FLOATING

2/66

STE2004S

Table 2. PIN DESCRIPTION (continued)

N°

Pad

Type

Function

E /

WR

176

I

WR

- 8080 Series Parallel Interface - Write enable clock input

- CANNOT BE LEFT FLOATING

RES

172

I

Reset Input. Active Low.

D/C

174

I

Interface Data/Command SelectorCANNOT BE LEFT FLOATING

CS

173

I

Serial & Parallel Interfaces ENABLE. When Low the Incoming Data are Clocked In.

CANNOT BE LEFT FLOATING

TEST_MODE

191

I

Test Pad - 50 kohm internal Pull-down MUST BE CONNECTED TO VSS/VSSAUX

TEST_VREF

146

O

Test Pad - MUST BE LEFT FLOATING

OSCIN

144

I

Oscillator Input:

OSC_IN

Configuration

High

Internal Oscillator Enabled

Low

Internal Oscillator Disabled

External Oscillator

Internal Oscillator Disabled

OSCOUT

210

O

Internal/External Oscillator Out - IF UNUSED MUST BE LEFT FLOATING

FR_OUT

211

O

Master Slave Frame Inversion Synchronization.

IF UNUSED MUST BE LEFT FLOATING

FR_IN

143

I

Master Slave Frame Inversion Synchronization.

CANNOT BE LEFT FLOATING

100

I

Master/Slave Configuration Bit:- CANNOT BE LEFT FLOATING

M/S

M/S

PIN

OSC_OUT

FR_OUT

FR_IN

Charge Pump

High

ENABLED

Enabled

Disabled

AuxVsense Disabled

Low

ENABLED

Enabled

Enabled

Charge Pump in Slave Mode or Ext

Power

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STE2004S

Figure 2. Chip Mechanical Drawing

ROW 6

ROW 27

ROW 5

ROW 0 COL 0

COL 50

COL 51

COL 101

ROW 32

ROW 37

MARK_1

MARK_3

STE2004S

(0,0)

Y

X

MARK_4

MARK_2

ROW 38

ROW 59

ROW28

ROW31

FR_OUT

OSC_OUT

VLCD

VLCDSENSE

VSS

TEST_MODE

VSSAUX

D0

D1

D2

D3

D4

D5

D6

D7

SCLK - SCL

SDOUT SDIN - SDAIN SDAOUT

VSSAUX

E - WR

R/W - RD

D/C

CS

RES

VDD2

VDD1

ICON

SEL1

SEL2

SEL3

EXT_SET

M/S

SA0

SA1

VSSAUX

TEST VREF

VSENSE_SLAVE OSC_IN

FR_IN VDD1_AUX

ROW64/ICON

ROW63

ROW60

LR0048

4/66

STE2004S

Figure 3. Improved ALTH & PLESKO Driving Method

	VLCD
	V2
	V3
ROW 0			∆V1(t)
			∆V2(t)
	R0 (t)
	V4
	V5
	VSS
	VLCD
	V2
	V3
ROW 1
	R1 (t)
	V4
	V5
	VSS
	VLCD
	V2
	V3
COL 0
	C0 (t)
	V4
	V5
	VSS
	VLCD
	V2
	V3
COL 1
	C1 (t)
	V4
	V5
	VSS
	VLCD - VSS
	V3 - VSS
	VLCD - V2		V4 - V5
Vstate1(t)	0V		0V
	V3 - VSS		VSS - V5
	VLCD - VSS		V4 - VLCD
			VSS - VLCD
	V3 - VSS
	VLCD - V2		V4 - V5
Vstate2(t)	0V		0V
	V3 - VSS		VSS - V5
			V4 - VLCD
			VSS - VLCD
	0 1 2 3 4 5 6 7 8 9 .......	..... 64 0 1 2 3 4 5 6 7 8 9 .......	..... 64
	FRAME n		FRAME n + 1
∆V1(t) = C1(t) - R0(t)			D00IN1154
∆V2(t) = C1(t) - R1(t)
			5/66

≥ 2 VLCD

------------------------ + 200mV (n + 4)

STE2004S

3 CIRCUIT DESCRIPTION

3.1 Supplies Voltages and Grounds

VDD2 is supply voltages to the internal voltage generator (see below). If the internal voltage generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the IC. VDD1 supply voltage could be different form VDD2.

VDD2

3.2 Internal Supply Voltage Generator

The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display supply voltage generation. The multiplying factor can be programmed to be: Auto, X5, X4, X3, X2, using the ’set CP Multiplication’ Command. If Auto is set, the multiplying factor is automatically selected to have the lowest current consumption in every condition. This make possible to have an input voltage that changes over time and a constant VLCD voltage. The output voltage (VLCD) is tightly controlled through the VL-

CDSENSE pad. For this voltage, eight different temperature coefficients (TC, rate of change with temperature) can be programmed using TC1 & TC0 or T2, T1 and T0 bits. This will ensure no contrast

degradation over the LCD operating range.

An external supply could be connected to VLCD to supply the LCD without using the internal generator. In such event the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset condition) and the Charge pump (CP[0;0]) set to 5x or Auto Mode.

3.3 Oscillator

A fully integrated oscillator (requires no external components) is present to provide the clock for the Display System. When used the OSC pad must be connected to VDD1 pad. An external oscillator could be used and fed into the OSC pin.If an external oscillator is used, it must be always present when STE2004S is not in power down mode. An oscillator out is provided on the OSCOUT Pad to cascade two or more drivers.

3.4 Master/Slave Mode

STE2004S support the Master Slave working Mode for Both Control Logic and Charge Pump. This function allows to drive matrix such as 204x65 or 102x130 using two synchronized STE2004S and the internal Charge Pump of both device.

If M/S is connected to VDD1, the driver is configured to work in Master Mode. When STE2004S is in Master Mode the Vsense_Slave Pin is disabled and is possible to control the VLCD value using Vop Bits. The Master Time Generator outputs on FR_OUT and on OSC_OUT the relevant timing references.

If M/S is connected to GND, the driver is configured to work in Slave Mode. When STE2004S is in Slave Mode, the VLCD configuration set by Vop registers and the thermal compensation slope set by TC register are neglected. The VLCD Value generated is equal to the Voltage value present on Vsense_Slave Pin so the slave configuration can follow the master configuration. The only recognized configuration is Vop=0 that forces the Charge Pump to be in off state whatever is the value of Vsense_aux.

To Synchronize the Master & Slave timing circuits, the slave driver FR_IN pad must be connected to Master Driver FR_OUT pad and Slave Driver OSC_IN pad must be connected to the master driver OSC_OUT Pad (Fig. 4). This connection ensure a synchronization at both Frame level (R0 on the master is driven together with the Slave R0 driver) and at Oscillator Level (same Frame frequency on the master and on the slave). If the Synchronization at Frame level is not required, FR_IN pin must be connected toVDD1 or to VDD1_aux (Fig. 5).

During Power Up Procesure, Master device must be forced to exit from power down before the slave device. To enter in PowerDown Mode, Slave Device must be forced in Power Down state before Master Device.

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STE2004S

Figure 4. Master Slave Logic Connection with frame Synchronization

STE2004S STE2004S

VDD1AUX OSCIN FRIN OSCOUT FROUT

FRIN OSCIN

OSCOUT FROUT

LR0219

Figure 5. Master Slave Logic Connection without frame Synchronization

STE2004S STE2004S

VDD1AUX OSCIN FRIN OSCOUT FROUT	OSCIN		OSCOUT FROUT
VDD1AUX		FRIN	LR0220

3.5 Bias Levels

To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are established to be (Fig. 6):

V

n + 3

V

n + 2

V

2

V

1

V

,V

LCD

, ------------

LCD

,------------

LCD

, ------------

LCD

,------------

LCD

SS

n + 4

n + 4

n + 4

n + 4

Figure 6. Bias level Generator

VLCD

R

n + 3

n + 4 ·VLCD

R

n + 2

n + 4 ·VLCD

nR

2

n + 4 ·VLCD

R

1

n + 4 ·VLCD

R

VSS D00IN1150

thus providing an 1/(n+4) ratio, with n calculated from:

n= m – 3

For m = 65, n = 5 and an 1/9 ratio is set.

For m = 49, n =4 and an 1/8 ratio is set.

The STE2004S provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:

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STE2004S

Table 3.

BS2	BS1	BS0	n
0	0	0	7
0	0	1	6
0	1	0	5
0	1	1	4
1	0	0	3
1	0	1	2
1	1	0	1
1	1	1	0

The following table Bias Level for m = 65 and m = 49 are provided:

Table 4.

Symbol	m = 65 (1/9)	m = 49 (1/8)
V1	VLCD	VLCD
V2	8/9*VLCD	7/8*VLCD
V3	7/9*VLCD	6/8*VLCD
V4	2/9*V VLCD	2/8*VLCD
V5	1/9 *VLCD	1/8*VLCD
V6	VSS	VSS

3.6 LCD Voltage Generation

The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to the following formula:

	VLCD(T=To) = VLCDo = (Ai+VOP · B)			(i=0,1,2)
with the following values:
Symbol	Value		Unit		Note
Ao	2.95		V		PRS = [0;0]
A1	6.83		V		PRS = [0;1]
A2	10.71		V		PRS = [1;0]
B	0.0303		V
To	27		°C

Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits are set to zero the internal voltage generator is switched off.

The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Multiplexing Rate. A general expression for this is:

	VLCD =	1 +			m		Vth
		2		1 –	1
					m

For MUX Rate m = 65 the ideal VLCD is:

VLCD(to) = 6.85 · Vth

than:

V (6.85 Vth – Ai ) op = ----------------------------------------

0.03

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STE2004S

3.7 Temperature Coefficients

As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need to vary the LCD Voltage with temperature. STE2004S provides the possibility to change the VLCD in a linear fashion against temperature with eight different Temperature Coefficient selectable through T2, T1 and T0 bits. Only four of them are available through basic instruction set.

Table 5.

NAME	TC1	TC0	Value	Unit
TC0	0	0	-0.0· 10-3	1/ °C
TC2	0	1	-0.7 · 10-3	1/°C
TC3	1	0	-1.05· 10-3	1/°C
TC6	1	1	-2.1 · 10-3	1/°C

Table 6.

NAME	T2	T1	T0	Value	Unit
TC0	0	0	0	-0.0· 10-3	1/ °C
TC1	0	0	1	-0.35 · 10-3	1/°C
TC2	0	1	0	-0.7 · 10-3	1/°C
TC3	0	1	1	-1.05· 10-3	1/°C
TC4	1	0	0	-1.4 · 10-3	1/°C
TC5	1	0	1	-1.75· 10-3	1/°C
TC6	1	1	0	-2.1 · 10-3	1/°C
TC7	1	1	1	-2.3· 10-3	1/°C

Figure 7.

LCD

V

B

2

A

1

0

A

A + B

1

A

00h

01h

02h

03h

04h

05h …. 7Ch 7Dh 7Eh

7Fh 00h 01h

02h 03h

04h 05h …. 7Ch

7Dh 7Eh 7Fh

00h 01h

02h 03h

04h 05h ….

7Ch 7Dh 7Eh 7Fh

O

PRS = [0;0]

PRS = [0;1]

PRS = [1;0]

V

Finally, the VLCD voltage at a given (T) temperature can be calculated as:

VLCD(T) = VLCDo · [1 + (T-To) · TC]

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STE2004S

3.8 Display Data RAM

The STE2004S, provides an 102X65 bits Static RAM to store Display data. This is organized into 9 (Bank0 to Bank8) banks with 102 Bytes. One of these Banks can be used for Icons. RAM access is accomplished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X101 (Horizontal) and Y0 to Y8 (Vertical).

When writing to RAM, four addressing mode are provided:

•Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the memory map. The X pointer is increased after each byte written. After the last column address (X=X-Car- riage), Y address pointer is set to jump to the following bank and X restarts from X=0. (Fig. 8)

•Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), X address pointer is set to jump to next column and Y restarts from Y=0 (Fig. 9).

•Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the memory map. The X pointer is increased after each byte written. After the last column address (X=X- Carriage), Y address pointer is set to jump to the next bank and X restarts from X=0 (fig. 10).

•Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Car- riage), the X pointer is set to jump to next column and Y restarts from Y=0 (fig. 11).

After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jump to the cell with address (X;Y) = (0;0) (Fig. 12,13,14 & 15).

Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.16) or on the bottom (D0=1, Fig. 17).

The STE2004S provides also means to alter the normal output addressing. A mirroring of the Display along the X axis is enabled setting to a logic one MY bit.This function doesn't affect the content of the memory map. It is only related to the memory read process.

When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled.

When ICON MODE=0 the Icon Row is like an other graphic line and is mirrored and scrolled.

Three are the multiplex ratio available when the partial display mode is disabled (MUX 33, MUX 49 and MUX 65). Only a subset of writable rows are output on Row drivers in MUX 33,49 & 65 Mode.

When Y-Carriage<MUX/8, if Mux 49 is selected only the first 49 memory rows are visualized; if Mux 33 is selected only the first 33 memory rows are visualized. The unused output row & column drivers must be left floating.

When Y-Carriage<=MUX/8 the icon Bank is located to BANK 8 in MUX 65 Mode, to BANK6 in MUX 49 Mode and to BANK 4 in MUX 33 Mode.

In Mux 33 & 49 Mode, when Y-Carriage>MUX/8 lines only 33, 49 lines are visualized.

It is possible to select which lines of DDRAM are connected on the output drivers using the scrolling function (Range: 0-Y-Carriage*8). When Y-Carriage>MUX/8 lines, the icon row is moved in DDRAM to the first row of the Bank correspondant to Y-CARRIAGE Return value, being always connected on the same output Driver.

When MY=0, the icon Row is output on R64 in mux 65 mode, on R56 in MUX 49 and on R48 in MUX33.

When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever is the MUX Rate.

10/66

STE2004S

Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)1

	0	1	2	3	98	99	100	101
BANK	0
BANK	1
BANK	2
BANK	3
BANK	4
BANK	5
BANK	6
BANK	7
BANK	8
								LR0049

Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)1

0

1

2

3

98

99

100

101

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

LR0050

Figure 10. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)1

	101	100	99	98	3	2	1	0
BANK	0
BANK	1
BANK	2
BANK	3
BANK	4
BANK	5
BANK	6
BANK	7
BANK	8
								LR0051

Figure 11. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)1

	101	100	99	98	3	2	1	0
BANK	0
BANK	1
BANK	2
BANK	3
BANK	4
BANK	5
BANK	6
BANK	7
BANK	8
								LR0052

1. X Carriage=101; Y-Carriage = 8

11/66

STE2004S

Figure 12. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=0)

	0	1	2	3	X CARR	99	100	101
					98
BANK	0
BANK	1
BANK	2
Y CARR
BANK 7
BANK 8
								LR0053

Figure 13. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=0)

X CARR

	0	1	2	3	98	99	100	101
BANK	0
BANK	1
BANK	2
Y CARR
BANK 7
BANK 8
								LR0054

Figure 14. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=1)

X CARR

	101	100	99	98	3	2	1	0
BANK	0
BANK	1
BANK	2
Y CARR
BANK 7
BANK 8
								LR0055

Figure 15. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=1)

X CARR

	101	100	99	98	3	2	1	0
BANK	0
BANK	1
BANK	2
Y CARR
BANK 7
BANK 8
								LR0056

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STE2004S

Figure 16. Data RAM Byte organization with D0 = 0

MSB

0

1

2

3

98

99

100

101

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

LSB

BANK 5

BANK 6

BANK 7

BANK 8

LR0057

Figure 17. Data RAM Byte organization with D0 = 1

LSB

0

1

2

3

98

99

100

101

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

MSB

BANK 5

BANK 6

BANK 7

BANK 8

LR0058

13/66

STE2004S

Figure 18. Memory Rows vs. Row Drivers Mapping ICON_MODE=1 and MUX 65

Y Address

D

ROW Output

a

Line

t

D3

D2

D1

D0

a

Address

Normal

Reverse

direction

direction

D0

00H

R0

R63

D1

01H

R1

R62

D2

02H

R2

R61

0

0

0

0

D3

Page 0

03H

R3

R60

D4

04H

R4

R59

D5

05H

R5

R58

D6

06H

R6

R57

D7

07H

R7

R56

D0

08H

R8

R55

D1

09H

R9

R54

D2

Page 1

0AH

R10

R53

0

0

0

1

D3

0BH

R11

R52

D4

0CH

R12

R51

D5

0DH

R13

R50

D6

0EH

R14

R49

D7

0FH

R15

R48

D0

10H

R16

R47

D1

11H

R17

R46

D2

Page 2

12H

R18

R45

0

0

1

0

D3

13H

R19

R44

D4

14H

R20

R43

D5

15H

R21

R42

D6

16H

R22

R41

D7

17H

R23

R40

D0

18H

R24

R39

D1

19H

R25

R38

D2

Page 3

1AH

R26

R37

0

0

1

1

D3

1BH

R27

R36

D4

1CH

R28

R35

D5

1DH

Pointer

R29

R34

Scrolling

D6

1EH

R30

R33

D7

1FH

R31

R32

Y-CARRIAGE

D0

20H

R32

R31

D1

21H

R33

R30

D2

Page 4

22H

R34

R29

0

1

0

0

D3

23H

R35

R28

D4

24H

R36

R27

D5

25H

R37

R26

D6

26H

R38

R25

D7

R39

R24

27H

D0

28H

R40

R23

D1

29H

R41

R22

D2

Page 5

2AH

R42

R21

D3

R43

R20

0

1

0

1

D4

2CH

R44

R19

D5

2DH

R45

R18

D6

2EH

R46

R17

D7

2FH

R47

R16

D0

30H

R48

R15

D1

R49

R14

31H

D2

Page 6

32H

R50

R13

0

1

1

0

D3

33H

R51

R12

D4

34H

R52

R11

D5

R53

R10

35H

D6

36H

R54

R9

R55

R8

D7

37H

D0

38H

R56

R7

D1

39H

R57

R6

D2

Page 7

3AH

R58

R5

0

1

1

1

D3

3BH

R59

R4

D4

3CH

R60

R3

D5

3DH

R61

R2

D6

3EH

R62

R1

D7

R63

R0

1

0

0

0

D0

Page 8

R64

R64

X address

00H

01H

02H

03H

04H

05H

06H

5FH

60H

61H

62H

63H

64H

65H

lr0268

Normal

C

C

C

C

C

C

C

C

C

C

C

C

C

C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

COL

0

1

2

3

4

5

6

95

96

97

98

99

100

101

Output

Reverse

C

C

C

C

C

C

C

C

C

C

C

C

C

C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

101

100

99

98

97

96

95

6

5

4

3

2

1

0

14/66

STE2004S

Figure 19. Memory Rows vs. Row Drivers Mapping ICON_MODE=0 and MUX 65

Y Address

D

a

Line

D3

D2 D1

D0

t

a

Address

D0

00H

D1

01H

D2

02H

0

0

0

0

D3

Page 0

03H

D4

04H

D5

05H

D6

06H

D7

07H

D0

08H

D1

09H

D2

Page 1

0AH

0

0

0

1

D3

0BH

D4

0CH

D5

0DH

D6

0EH

D7

0FH

D0

10H

D1

11H

D2

Page 2

12H

0

0

1

0

D3

13H

D4

14H

D5

15H

D6

16H

D7

17H

D0

18H

D1

19H

D2

Page 3

1AH

0

0

1

1

D3

1BH

D4

1CH

D5

1DH

Scrolling Pointer

D6

1EH

D7

1FH

Y-CARRIAGE

D0

20H

D1

21H

D2

Page 4

22H

0

1

0

0

D3

23H

D4

24H

D5

25H

D6

26H

D7

27H

D0

28H

D1

29H

D2

Page 5

2AH

0

1

0

1

D3

2BH

D4

2CH

D5

2DH

D6

2EH

D7

2FH

D0

30H

D1

31H

D2

Page 6

32H

0

1

1

0

D3

33H

D4

34H

D5

35H

D6

36H

D7

37H

D0

38H

D1

39H

D2

Page 7

3AH

0

1

1

1

D3

3BH

D4

3CH

D5

3DH

D6

3EH

1

0

0

0

D7

Page 8

3FH

D0

40H

X address

00H 01H 02H 03H 04H 05H 06H

5FH 60H 61H 62H 63H 64H 65H

Normal

C C C C C C C

C C C C C C C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

COL

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

0

1

2

3

4

5

6

95

96

97

98

99

100 101

Output

Reverse

C

C

C

C

C

C

C

C

C

C

C

C

C

C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

101

100

99

98

97

96

95

6

5

4

3

2

1

0

ROW Output

Normal Reverse direction direction

R0	R64
R1	R63
R2	R62
R3	R61
R4	R60
R5	R59
R6	R58
R7	R57
R8	R56
R9	R55
R10	R54
R11	R53
R12	R52
R13	R51
R14	R50
R15	R49
R16	R48
R17	R47
R18	R46
R19	R45
R20	R44
R21	R43
R22	R42
R23	R41
R24	R40
R25	R39
R26	R38
R27	R37
R28	R36
R29	R35
R30	R34
R31	R33
R32	R32
R33	R31
R34	R30
R35	R29
R36	R28
R37	R27
R38	R26
R39	R25
R40	R24
R41	R23
R42	R22
R43	R21
R44	R20
R45	R19
R46	R18
R47	R17
R48	R16
R49	R15
R50	R14
R51	R13
R52	R12
R53	R11
R54	R10
R55	R9
R56	R8
R57	R7
R58	R6
R59	R5
R60	R4
R61	R3
R62	R2
R63	R1
R64	R0

lr0269

15/66

STE2004S

Figure 20. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=6 and MUX 49

Y Address

D

ROW Output

a

Line

D3

D2 D1

D0

t

Normal

Reverse

a

Address

direction

direction

D0

00H

R0

R55

D1

01H

R1

R54

D2

02H

R2

R53

0

0

0

0

D3

Page 0

03H

R3

R52

D4

04H

R4

R51

D5

05H

R5

R50

D6

06H

R6

R49

D7

07H

R7

R48

D0

08H

R8

R47

D1

09H

R9

R46

D2

Page 1

0AH

R10

R45

0

0

0

1

D3

0BH

R11

R44

D4

0CH

R12

R43

D5

0DH

R13

R42

D6

0EH

R14

R41

D7

0FH

R15

R40

D0

10H

R16

R39

D1

11H

R17

R38

D2

Page 2

12H

R18

R37

0

0

1

0

D3

13H

R19

R36

D4

14H

R20

R35

D5

15H

R21

R34

D6

16H

R22

R33

D7

17H

R23

R32

D0

18H

R32

R23

D1

19H

R33

R22

D2

Page 3

1AH

R34

R21

0

0

1

1

D3

1BH

R35

R20

D4

1CH

R36

R19

D5

1DH

Scrolling Pointer

R37

R18

D6

1EH

R38

R17

D7

1FH

R39

R16

D0

20H

R40

R15

D1

21H

R41

R14

D2

22H

R42

R13

0

1

0

0

D3

Page 4

23H

R43

R12

D4

24H

R44

R11

D5

25H

R45

R10

D6

26H

R46

R9

D7

27H

R47

R8

D0

28H

R48

R7

D1

29H

R49

R6

D2

Page 5

2AH

R50

R5

0

1

0

1

D3

2BH

R51

R4

D4

2CH

R52

R3

D5

2DH

R53

R2

D6

2EH

R54

R1

D7

2FH

R55

R0

Y-CARRIAGE

D0

30H

R56

R56

D1

31H

D2

Page 6

32H

0

1

1

0

D3

33H

D4

34H

D5

35H

D6

36H

D7

37H

D0

38H

D1

39H

D2

Page 7

3AH

0

1

1

1

D3

3BH

D4

3CH

D5

3DH

D6

3EH

1

0

0

0

D7

Page 8

3FH

D0

X address

00H 01H 02H 03H 04H 05H 06H

5FH 60H 61H 62H 63H 64H 65H

Normal

C C C C C C C

C C C C C C C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

COL

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

0

1

2

3

4

5

6

95

96

97

98

99

100 101

Output

Reverse

C

C

C

C

C

C

C

C

C

C

C

C

C

C

lr0270

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

101

100

99

98

97

96

95

6

5

4

3

2

1

0

16/66

STE2004S

Figure 21. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage<=6 and MUX 49

Y Address

D

ROW Output

a

Line

D2

D1

D0

t

D3

a

Address

Normal

Reverse

direction

direction

D0

00H

R0

R56

D1

01H

R1

R55

D2

02H

R2

R54

0

0

0

0

D3

Page 0

03H

R3

R53

D4

04H

R4

R52

D5

05H

R5

R51

D6

06H

R6

R50

D7

07H

R7

R49

D0

08H

R8

R48

D1

09H

R9

R47

D2

Page 1

0AH

R10

R46

0

0

0

1

D3

0BH

R11

R45

D4

0CH

R12

R44

D5

0DH

R13

R43

D6

0EH

R14

R42

D7

0FH

R15

R41

D0

10H

R16

R40

D1

11H

R17

R39

D2

Page 2

12H

R18

R38

0

0

1

0

D3

13H

R19

R37

D4

14H

R20

R36

D5

15H

R21

R35

D6

16H

R22

R34

D7

17H

R23

R33

D0

18H

R32

R32

D1

19H

R33

D2

Page 3

1AH

R34

R22

D3

R21

0

0

1

1

1BH

R35

D4

1CH

R36

R20

D5

1DH

Scrolling

Pointer

R37

R19

D6

1EH

R38

R18

D7

R17

1FH

R39

D0

20H

R40

R16

R41

R15

D1

21H

D2

R42

R14

Page 4

22H

R43

R13

0

1

0

0

D3

23H

D4

24H

R44

R12

R45

R11

D5

25H

D6

26H

R46

R10

D7

27H

R47

R9

D0

28H

R48

R8

D1

R49

R7

29H

R50

R6

D2

Page 5

2AH

0

1

0

1

D3

2BH

R51

R5

D4

2CH

R52

R4

D5

R53

R3

2DH

R54

R2

D6

2EH

D7

2FH

R55

R1

Y-CARRIAGE

D0

30H

R56

R0

D1

31H

D2

Page 6

32H

0

1

1

0

D3

33H

D4

34H

D5

35H

D6

36H

D7

37H

D0

38H

D1

39H

D2

Page 7

3AH

0

1

1

1

D3

3BH

D4

3CH

D5

3DH

D6

3EH

D7

Page 8

3FH

1

0

0

0

D0

X address

00H

01H

02H

03H

04H

05H

06H

5FH

60H

61H

62H

63H

64H

65H

Normal

C

C

C

C

C

C

C

C

C

C

C

C

C

C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

COL

0

1

2

3

4

5

6

95

96

97

98

99

100

101

lr0271

Output

Reverse

C

C

C

C

C

C

C

C

C

C

C

C

C

C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

101

100

99

98

97

96

95

6

5

4

3

2

1

0

17/66

STE2004S

Figure 22. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=7, Scrolling Pointer>07h and MUX 49

Y Address

D

ROW Output

a

Line

D3

D2 D1

D0

t

Normal

Reverse

a

Address

direction

direction

D0

00H

R0

R56

D1

01H

R1

R55

D2

02H

R2

R54

0

0

0

0

D3

Page 0

03H

R3

R53

D4

04H

R4

R52

D5

05H

R5

R51

D6

06H

R6

R50

D7

07H

R7

R49

D0

08H

R8

R48

D1

09H

R9

R47

D2

Page 1

0AH

R10

R46

0

0

0

1

D3

0BH

R11

R45

D4

0CH

R12

R44

D5

0DH

R13

R43

D6

0EH

R14

R42

D7

0FH

R15

R41

D0

10H

R16

R40

D1

11H

R17

R39

D2

Page 2

12H

R18

R38

0

0

1

0

D3

13H

R19

R37

D4

14H

R20

R36

D5

15H

R21

R35

D6

16H

R22

R34

D7

17H

R23

R33

D0

18H

R32

R32

D1

19H

R33

R23

D2

Page 3

1AH

R34

R22

0

0

1

1

D3

1BH

R35

R21

D4

1CH

R36

R20

D5

1DH

Scrolling Pointer

R37

R19

D6

1EH

R38

R18

D7

1FH

R39

R17

D0

20H

R40

R16

D1

21H

R41

R15

D2

22H

R42

R14

0

1

0

0

D3

Page 4

23H

R43

R13

D4

24H

R44

R12

D5

25H

R45

R11

D6

26H

R46

R10

D7

27H

R47

R9

D0

28H

R48

R8

D1

29H

R49

R7

D2

2AH

R50

R6

0

1

0

1

D3

Page 5

2BH

R51

R5

D4

2CH

R52

R4

D5

2DH

R53

R3

D6

2EH

R54

R2

D7

2FH

R55

R1

D0

30H

R56

R0

D1

31H

D2

Page 6

32H

0

1

1

0

D3

33H

D4

34H

D5

35H

D6

36H

D7

37H

Y-CARRIAGE

D0

38H

D1

39H

D2

Page 7

3AH

0

1

1

1

D3

3BH

D4

3CH

D5

3DH

D6

3EH

1

0

0

0

D7

Page 8

3FH

D0

X address

00H 01H 02H 03H 04H 05H 06H

5FH 60H 61H 62H 63H 64H 65H

Normal

C C C C C C C

C C C C C C C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

COL

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

0

1

2

3

4

5

6

95

96

97

98

99

100 101

lr0275

Output

Reverse

C

C

C

C

C

C

C

C

C

C

C

C

C

C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

101

100

99

98

97

96

95

6

5

4

3

2

1

0

18/66

STE2004S

Figure 23. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=7, Scrolling Pointer>07h and MUX 49

Y Address

D

a

Line

D3

D2 D1

D0

t

a

Address

D0

00H

D1

01H

D2

02H

0

0

0

0

D3

Page 0

03H

D4

04H

D5

05H

D6

06H

D7

07H

D0

08H

D1

09H

D2

Page 1

0AH

0

0

0

1

D3

0BH

D4

0CH

D5

0DH

D6

0EH

D7

0FH

D0

10H

D1

11H

D2

Page 2

12H

0

0

1

0

D3

13H

D4

14H

D5

15H

D6

16H

D7

17H

D0

18H

D1

19H

D2

Page 3

1AH

0

0

1

1

D3

1BH

D4

1CH

D5

1DH

Scrolling Pointer

D6

1EH

D7

1FH

D0

20H

D1

21H

D2

Page 4

22H

0

1

0

0

D3

23H

D4

24H

D5

25H

D6

26H

D7

27H

D0

28H

D1

29H

D2

Page 5

2AH

0

1

0

1

D3

2BH

D4

2CH

D5

2DH

D6

2EH

D7

2FH

D0

30H

D1

31H

D2

Page 6

32H

0

1

1

0

D3

33H

D4

34H

D5

35H

D6

36H

D7

37H

Y-CARRIAGE

D0

38H

D1

39H

D2

Page 7

3AH

0

1

1

1

D3

3BH

D4

3CH

D5

3DH

D6

3EH

1

0

0

0

D7

Page 8

3FH

D0

X address

00H 01H 02H 03H 04H 05H 06H

5FH 60H 61H 62H 63H 64H 65H

Normal

C C C C C C C

C C C C C C C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

COL

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

0

1

2

3

4

5

6

95

96

97

98

99

100 101

Output

Reverse

C

C

C

C

C

C

C

C

C

C

C

C

C

C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

101

100

99

98

97

96

95

6

5

4

3

2

1

0

ROW Output

Normal Reverse direction direction

R0		R55
R1		R54
R2		R53
R3		R52
R4		R51
R5		R50
R6		R49
R7		R48
R8		R47
R9		R46
R10		R45
R11		R44
R12		R43
R13		R42
R14		R41
R15		R40
R16		R39
R17		R38
R18		R37
R19		R36
R20		R35
R21		R34
R22		R33
R23		R32
R32		R23
R33		R22
R34		R21
R35		R20
R36		R19
R37		R18
R38		R17
R39		R16
R40		R15
R41		R14
R42		R13
R43		R12
R44		R11
R45		R10
R46		R9
R47		R8
R48		R7
R49		R6
R50		R5
R51		R4
R52		R3
R53		R2
R54		R1
R55		R0
R56		R56

lr0276

19/66

STE2004S

Figure 24. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=8, Scrolling Pointer<10h and MUX 49

Y Address

D

ROW Output

a

Line

t

D3

D2

D1

D0

a

Address

Normal

Reverse

direction

direction

D0

00H

R0

R55

D1

01H

R1

R54

D2

02H

R2

R53

0

0

0

0

D3

Page 0

03H

R3

R52

D4

04H

R4

R51

D5

05H

R5

R50

D6

06H

R6

R49

D7

07H

R7

R48

D0

08H

R8

R47

D1

09H

Scrolling Pointer

R9

R46

D2

0AH

R10

0

0

0

1

D3

Page 1

0BH

R11

R44

D4

0CH

R12

R43

D5

0DH

R13

R42

D6

0EH

R14

R41

D7

0FH

R15

R40

D0

10H

R16

R39

D1

11H

R17

R38

D2

Page 2

12H

R18

R37

0

0

1

0

D3

13H

R19

R36

D4

14H

R20

R35

D5

15H

R21

R34

D6

16H

R22

R33

D7

17H

R23

R32

D0

18H

R32

R23

D1

R22

19H

R33

D2

R34

R21

Page 3

1AH

0

0

1

1

D3

1BH

R35

R20

D4

1CH

R36

R19

D5

1DH

R37

R18

D6

1EH

R38

R17

D7

R16

1FH

R39

D0

20H

R40

R15

R41

R14

D1

21H

D2

R42

R13

Page 4

22H

R43

R12

0

1

0

0

D3

23H

D4

24H

R44

R11

R45

R10

D5

25H

D6

26H

R46

R9

D7

27H

R47

R8

D0

28H

R48

R7

D1

R49

R6

29H

D2

R50

R5

Page 5

2AH

D3

R51

R4

0

1

0

1

2BH

D4

2CH

R52

R3

D5

R53

R2

2DH

D6

R54

R1

2EH

D7

R55

R0

2FH

R56

R56

D0

30H

D1

31H

D2

Page 6

32H

0

1

1

0

D3

33H

D4

34H

D5

35H

D6

36H

D7

37H

D0

38H

D1

39H

D2

Page 7

3AH

0

1

1

1

D3

3BH

Y-CARRIAGE

D4

3CH

D5

3DH

D6

3EH

D7

Page 8

3FH

1

0

0

0

D0

X address

00H

01H

02H

03H

04H

05H

06H

5FH

60H

61H

62H

63H

64H

65H

Normal

C

C

C

C

C

C

C

C

C

C

C

C

C

C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

COL

0

1

2

3

4

5

6

95

96

97

98

99

100

101

LR0273

Output

Reverse

C

C

C

C

C

C

C

C

C

C

C

C

C

C

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Direction

L

L

L

L

L

L

L

L

L

L

L

L

L

L

101

100

99

98

97

96

95

6

5

4

3

2

1

0

20/66