• 68000 & 8080 Parallel Interf aces (read and write)
• 3-lines and 4-lines SPI Interface (read and write)
• 3-lines 9 bit Serial Interface (read and write)
■ Fully Integrated Oscillat or requires no ex ternal
components
■ CMOS Compatible Inputs
■ Fully Integrated Configurable LCD bias voltage
generator with:
• Selectabl e
multiplication factor (up to 5X)
• Effective sensing for High Precision Output
• Eight selectable temperature compensation
coefficients
■ Designed for chip-on-glass (COG) applications.
■ Low Power Consumption, suitable for battery
operated systems
■ Logic Supply Voltage range from 1.7 to 3.6V
■ High Voltage Generator Supply Voltage range
from 1.75 to 4.5V
■ Display Supply Voltage range from 4.5 to 14.5V
■ Backward Compatibility with STE2001 and
STE2002
DESCRIPTION
The STE2004 is a low power CMOS LCD controller driver. Designed to drive a 65 rows by 102 columns graphic display, it provides all necessary
functions in a single chip, including on-chi p LCD
supply and bias voltages generators, resulting in a
minimum of externals compone nts and in a very
low power consumption.
STE2004 features six standard interfaces (3-lines
Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel,
8080 parallel & I
2
C) for ease of interfacing with the
host micro-controller
TypeOrdering Number
Bumped WafersSTE2004DIE1
Bumped Dice on Waffle Pack
E / WR176IWR - 8080 Series Parallel Interface - Write enable clock input
RES
D/C
CS
TEST_MODE191ITest Pad - 50 kohm internal Pull-down MUS T BE CO NNEC TED TO VSS/VS SAUX
TEST_VREF146OTest Pad - MUST B E LEF T FLOATIN G
OSCIN144I
OSCOUT210OInternal/External Oscillator Out - IF UNUSED MUST BE LEFT FLOATING
FR_OUT211OMaster Slav e Frame Inversion Synchronization .
FR_IN143IMaster Slave Fram e Inversi on Synchronization .
M/S100IMaster/
(continued)
- CANNOT BE LEFT FLOATING
172IReset Input. Active Low.
174IInterface Data/Command Sele ctor- CA NNOT BE LEFT FLOATING
173ISerial & Parallel Interf aces EN AB LE. When Low the Incoming Data ar e Cl ocked In.
CANNOT BE LEFT FLOATING
Oscillator Input:
OSC_INConfiguration
HighInternal Oscillator Enabled
LowInternal Oscillator Disabled
External ScillatorInternal Oscillator Disabled
IF UNUSED MUST BE LEFT FLOATING
CANNOT BE LEFT FLOATING
Slave Configuration Bit:- CANNOT BE LEFT FLOATING
M/S PINOSC_OUTFR_OUTFR_INCharge Pump
HighENABLEDEnabledDisabled AuxVsense Disabled
LowENABLEDEnabledEnabled Charge Pump in Slave Mode or Ext
Power
3/67
STE2004
Figure 2. Chip Mechanical Drawing
ROW 5
ROW 0
COL 0
COL 50
COL 51
ROW 6
MARK_1
STE2004
(0,0)
X
ROW 27
ROW28
ROW31
FR_OUT
MARK_3
Y
MARK_4
OSC_OUT
VLCD
VLCDSENSE
VSS
TEST_MODE
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK - SCL
SDOUT
SDIN - SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
4/67
COL 101
ROW 32
ROW 37
MARK_2
ROW 38
ROW 59
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
ROW64/ICON
ROW63
ROW60
LR0048
Figure 3. Improved ALTH & PLESKO Driving Method
V
LCD
V
2
V
3
ROW 0
R0 (t)
V
4
V
5
V
SS
V
LCD
V
2
V
3
ROW 1
R1 (t)
V
4
V
5
V
SS
V
LCD
V
2
V
3
COL 0
C0 (t)
V
4
V
5
V
SS
V
LCD
V
2
V
3
COL 1
C1 (t)
V
4
V
5
V
SS
V
- V
LCD
SS
V3 - V
SS
STE2004
∆V1(t)
∆V
(t)
2
V
V
state1
state2
- V
V
LCD
(t)
V3 - V
V
- V
LCD
V3 - V
- V
V
LCD
(t)
V3 - V
(t) = C1(t) - R0(t)
∆V
1
∆V
(t) = C1(t) - R1(t)
2
2
0V
SS
SS
SS
2
0V
SS
0 1 2 3 4 5 6 7 8 964
.......
FRAME nFRAME n + 1
0 1 2 3 4 5 6 7 8 964
.....
.......
.....
V
4 - V5
0V
V
SS - V5
V4 - V
VSS - V
V
4 - V5
0V
V
SS - V5
V4 - V
VSS - V
D00IN1154
LCD
LCD
LCD
LCD
5/67
STE2004
CIRCUIT DESCRIPTION
Supplies Voltages and Gro un ds
is supply voltages to the internal voltage generator (see below). If the internal voltage generator is
V
DD2
not used, this should be c onnected to V
could be different form V
DD2
.
Internal Supply Voltage Ge nerator
The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display
supply voltage generation. T he m ultiplyin g fac tor can be program m ed t o be : Aut o, X 5, X4, X3, X 2, us ing
the ’set CP Multiplication’ Command. If Auto is set, the multiplying factor is automatically selected to have
the lowest current consumption in every condition. This make possible to have an input voltage that changes over time and a constant V
CDSENSE
pad. For this voltage, eight different temperature coefficients (TC, rate of change with
voltage. The output voltage (V
LCD
temperature) can be programmed using TC1 & TC 0 or T2, T1 and T0 bits. This will ensure no contrast
degradation over the LCD operating range.
An external supply could be connected to V
such event the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset condition) and the Charge pump (CP[0;0]) set to 5x or Auto Mode.
Oscillator
A fully integrated oscillator (requires no externa l com ponen ts) is presen t to provi de t he clock f or t he Display System. When u sed the O SC pad must be connec ted to V
used and fed into the OSC pin.If an external oscillator is used, it must be alwa ys pres ent wh en STE2 004
is not in power down mode. An oscillator out is provided on the OSCOUT Pad to cascade two or more
drivers.
Master/Slave Mode
STE2004 support the Master Slave working Mode for Both Control Logic and Charge Pump. This function
allows to drive matrix such as 204x65 or 102x 130 using two synchronized STE2004 and the internal
Charge Pump of both device.
If M/S
is connected to VDD1, the driver is configured to work in Master Mode. When STE2004 is in Master
Mode the Vsense_Slave P in is disabled and is possib le to control the VLCD value using Vop Bits. The
Master Time Generator outputs on FR_OUT and on OSC_O UT the relevant timing referen ces.
If M/S
is connected to GND, the driver i s configured to wo rk in Slave Mode. When S TE2004 is i n Slave
Mode, the VLCD configuration set by Vop registers and the thermal compensation slope set by TC register
are neglected. The VLCD Value generated is equal to the Voltage value present on Vsense_Slave Pin so
the slave configuration can follow t he master c onfiguration. The onl y recognized configuration is Vop=0
that forces the Charge Pump to be in off state whatever is the value of Vsense_aux.
To Synchronize the Master & Slave timing circuits, the slave driver FR_IN pad must be connected to Master Driver FR_OUT pad and Slave Driver OSC_IN pad must be connected to the master driver OSC_OUT
Pad (Fig. 4). This conn ection ensu re a syn chronization at bot h Fram e level (R0 on the m aster is driven
together with the Slave R0 driver) and at Osc illator Level (sam e Frame freque ncy on the master and on
the slave). If the Synchronization at Frame level is not required, FR_IN pin must be connected toVDD1 or
to VDD1_aux (Fig. 5).
During Power Up Procesure, Master device must be forced to exit from power down before the slave device. To enter in PowerDown Mode, Slave Device must be forced in Power Down state before Master Device.
V
DD1
DD2
pad. V
2VLCD⋅
------------------------ -200mV+≥
n4+()
to supply the LCD without using the internal generator. In
LCD
supplies the rest of the IC. V
DD1
) is tightly controlled through the V
LCD
pad. An external oscillator could be
DD1
supply voltage
DD1
L-
6/67
Figure 4. Master Slave Logic Connection with frame Synchronization
0
0
STE2004
STE2004
VDD1AUX
OSCOUT
FROUTOSCINFRINOSCIN FRIN
STE2004
OSCOUT FROUT
LR0219
Figure 5. Master Slave Logic Connection without frame Synchronization
STE2004
VDD1AUX
OSCOUT
FROUTOSCIN FRIN
VDD1AUX
STE2004
OSCIN
OSCOUT FROUT
FRIN
LR022
Bias Levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias ) levels are generated.
The ratios among these levels and VLCD, s hould be selected acc ording to the MUX ratio (m). They are
established to be (Fig. 6):
V
LCD
n3+
------------ -
,
n4+
V
LCD
n2+
------------ -
,
n4+
V
LCD
2
------------ -
,
n4+
V
LCD
------------ -
,
n4+
1
V
LCD,VSS
Figure 6. Bias level Generator
V
R
R
nR
R
R
LCD
n + 3
n + 4
n + 2
n + 4
n + 4
n + 4
V
2
1
SS
·V
LCD
·V
LCD
·V
LCD
·V
LCD
D00IN115
thus providing an 1/(n+4) ratio, with n calculated from:
nm3–=
For m = 65, n = 5 and an 1/9 ratio is set.
For m = 49, n =4 and an 1/8 ratio is set.
The STE2004 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:
7/67
STE2004
BS2BS1BS0n
0007
0016
0105
0114
1003
1012
1101
1110
The following table Bias Level for m = 65 and m = 49 are provided:
Symbolm = 65 (1/9)m = 49 (1/8)
V1V
V28/9*V
V37/9*V
V42/9*V V
V51/9 *V
V6V
LCD
LCD
LCD
LCD
LCD
SS
V
7/8*V
6/8*V
2/8*V
1/8*V
V
LCD
LCD
LCD
LCD
LCD
SS
LCD Voltage Generation
The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to
the following formula:
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits
are set to zero the internal voltage generator is switched off.
The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Multiplexing Rate. A general expression for this is:
1m+
For MUX Rate m = 65 the ideal V
LCD
V
is:
LCD
----------------------------------- -
21
V
LCD(to)
⋅
= 6.85 · V
-------- -–
1
m
th
V
⋅=
th
than:
6.85 VthAi–⋅()
op
-----------------------------------------=
0.03
V
8/67
STE2004
Temperature Coefficients
As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's
the need to vary the LCD Voltage with temperature. STE2004 provides the possibility to change the VLCD
in a linear fashion against temperature with eight different Temperature Coefficient selectable through T2,
T1 and T0 bits. Only four of them are available through basic instruction set.
voltage at a given (T) temperature can be calculated as:
LCD
A
7Fh 00h 01h 02h
(T) = V
V
LCD
03h 04h
05h …. 7Ch
PRS = [0;1]
o · [1 + (T-To) · TC]
LCD
7Dh 7Eh 7Fh
2
A
00h 01h 02h 03h 04h
05h 7Ch
….
PRS = [1;0]
7Dh 7Eh 7Fh
O
V
9/67
STE2004
Display Data RAM
The STE2004, provides an 102X65 bits Static RAM to store Display data. This is organized into 9 (Bank0
to Bank8) banks with 102 Bytes. One of these Banks can be used for Icons. RAM access is accomplished
in either one of the Bus Interfaces provid ed (s ee be low). A llowed addres ses are X 0 to X101 (Horizontal)
and Y0 to Y8 (Vertical).
When writing to RAM, four addressing mode are provided:
• Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the memory map. The X pointer is increased after each byte written. After the last column address (X=X-Carriage), Y address pointer is set to jump to the following bank and X restarts from X=0. (Fig. 8)
• Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory
map. The Y pointer is increased after each byte written. After th e l ast Y b ank address (Y=Y-Carriage),
X address pointer is set to jump to next column and Y restarts from Y=0 (Fig. 9).
• Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the
memory map. The X pointer is increased af ter each byte written. After the last column address (X=XCarriage), Y address pointer is set to jump to the next bank and X restarts from X=0 (fig. 10).
• Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), the X pointer is set to jump to next column and Y restarts from Y=0 (fig. 11).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jump to the
cel l with addre ss (X;Y) = (0;0) (Fig. 12,13,14 & 15).
Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.16) or on the bottom (D0=1, Fig.
17).
The STE2004 provides also means to alter the normal output addressing. A mirroring of the Display along
the X axis is enabled setting t o a l ogic one MY bit.This function does n't af fect t he cont ent of the me mory
map. It is only related to the memory read process.
When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled.
When ICON MODE=0 the Icon Row is like an other graphic line and is mirrored and scrolled.
Three are the multiplex ratio available when the partial display mode i s disabled (MUX 33, MU X 49 and
MUX 65). Only a subset of writable rows are output on Row drivers in MUX 33,49 & 65 Mode.
When Y-Carriage<M U X/ 8, if Mux 49 is selected only the first 49 m emory rows are v isualized; if Mux 33 i s
selected only the first 33 memo ry rows are v isualized. Th e unused output row & colum n drivers m ust be
left floating.
When Y-Carri ag e<=MUX/8 the icon Bank is locat ed to BANK 8 i n MUX 65 Mode, to BANK6 in MUX 49
Mode and to BANK 4 in MUX 33 Mode.
In Mux 33 & 49 Mode, when Y-Carriage>MUX/8 lines only 33, 49 lines are visualized.
It is possible to select whic h l ines of DDRAM are c onnected on the output dri vers using the scrolling func-
tion (Range: 0-Y-Carriage*8). When Y-Carriage>MUX/8 lines, the icon row is moved in DDRAM to the
first row of the Bank correspondant to Y-CARRIAGE Return value, being always connected on the same
output Driver.
When MY=0, the icon Row is output on R64 in mux 65 mode, on R56 in MUX 49 and on R48 in MUX33.
When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever is the MUX Rate.
10/67
STE2004
2
Figure 8. Auto m at ic da ta RAM wri t in g sequence with V=0 and Data RAM N or m a l Form a t ( MX =0)1
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
01239899100101
LR0049
Figure 9. Auto m at ic da ta RAM wri t in g sequence with V=1 and Data RAM N or m a l Form a t ( MX =0)
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
0101239899100101
LR0050
Figure 10. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)
1
1
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
32109899100101
LR0051
Figure 11. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)1
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
1. X Carriage=101; Y-Carriage = 8
10329899100101
LR005
11/67
STE2004
3
4
6
Figure 12. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=0)
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
0123
X CARR
9899 100 101
LR005
Figure 13. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=0)
0123
X CARR
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
9899 100 101
LR005
Figure 14. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=1)
X CARR
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
1239899100101
0
LR0055
Figure 15. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=1)
X CARR
9899100101
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
0
123
LR005
12/67
Figure 16. Data RA M Byte or ga n iza ti on with D0 = 0
8
MSB
0
12398 99 100 101
LSB
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
Figure 17. Data RA M Byte or ga n iza ti on with D0 = 1
LSB
01239899100101
MSB
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
STE2004
LR0057
LR005
13/67
STE2004
Figure 18. Memory Rows vs. Row Drivers Mapping ICON_MODE=1 and MUX 65