ST STE2001 User Manual

查询STE2001DIE1供应商

65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2001

PRODUCT PREVIEW

■

65 x 128 bits Display Data RAM

■

Configurable matrix: 65 x 128 or 33 x 128

■

Programmable (65/33) MUX rate

■

Row byRow Scrolling

■ Automatic data RAM Blanking procedure

■

Selectable Input Interface:

• I2C Bus Fast and Hs-mode (read and write)

• Parallel Interface (write only)

• Serial Interface (write only)

■

Fully Integrated Oscillator requires no external
components

■

Fully IntegratedConfigurable LCD biasvoltages
generator with:

•Selectable (5X, 4X, 3X, 2X) multiplication factor

• Effective sensing for High Precision Output

• Four selectable temperature compensation

coefficients

■

Designed for chip-on-glass (COG) applications

■ Programmable bottom row pads mirroring and

top row pads mirroring for compatible with both
TCP and COG applications

Figure 1. Block Diagram

■

Low Power Consumption, suitable for battery
operated systems

■

Logic Supply Voltage range from 1.9 to 5V

■

High Voltage Generator Supply Voltage range
from 2.4 to 4.5V

■

Display Supply Voltage range from 4.5 to 9V

DESCRIPTION

The STE2001 is a low power CMOS LCD controller
driver. Designed to drive a 65 rows by 128 columns
graphic display, provides all necessary functions in a
single chip, including on-chip LCD supply and bias
voltages generators, resulting in a minimum of exter­nals components and in a very low power consump­tion. TheSTE2001 features three standard interfaces
(Serial, parallel, I
host

µcontroller.

Bumped Wafers STE2001DIE1

Bumped Dice on WafflePack STE2001DIE2

2

C) for ease of interfacing with the

Type Ordering Number

CO to C127 R0 to R64

OSC

VLCDIN

VLCDSENSE

VLCDOUT

RES

VDD1,2,3

V

1,2

SS

SEL1,2

SAO

DATA

TIMING

GENERATOR

CLOCK

INSTRUCTION

REGISTER

OSC

VOLTAGE

BIAS

GENERATOR

VOLTAGE

HIGH

GENERATOR

RESET

REGISTER

I2CBUS

SDA_IN SDA_OUTSCL DB0 to DB7 E PD/C

COLUMN
DRIVERS

LATCHES

65 x

RAM

PARALLEL

DATA

128

DISPLAY

CONTROL

LOGIC

SCE SDIN SCLK SD/C

SERIAL

ROW

DRIVERS

SHIFT

REGISTER

SCROLL

LOGIC

October 2001

This ispreliminary information on a new product now in development. Details are subject to change without notice.

TEST

TEST_0_13

BSY_FLG

D00IN1137

1/36

STE2001

PIN DESCRIPTION

N° Pad Type Function

R0 to R64 1 to 16

O LCD Row Driver Output
145 to 177
257 to 272

C0 to C127 17 to 144 O LCD Column Driver Output

V

SS1,2

V

DD1

V

DD2,3

V

LCDIN

V

LCDOUT

V

LCDSENSE

227 to 238 GND Ground pads. V
186 to 191 Supply IC Positive Power Supply
192 to 201 Supply Internal Generator Supply Voltages.
246 to 251 Supply LCD Supply Voltages forthe Column and Row Output Drivers.
239 to 244 Supply Voltage Multiplier Ouput

245 Supply Voltage Multiplier Regulation Input. V

is GND for V

SS1

Tuning

SEL1,2 183, 184 I Interface Mode Selection

SDA_IN 223 I

SDA_OUT 222 O

SCL 224 I
SA0 225 I

2

C Bus Data In

I

2

C Bus Data Out

I

2

C bus Clock

I

2

C Slave Address LSB

I

OSC 185 I External Oscillator Input

DD1,VSS2

LCDOUT

for V

DD2

and V

DD3

Sensing for Output Voltage Fine

RES 221 I Reset Input. Active Low.

DB0 to

211 to 218 I Parallel Interface 8 BitData Bus

DB7

E 220 I Parallel Interface Data Latch Signal. Data are Latched on the Falling EDGE.
PD/C 219 I Parallel Interface Data/Command Selector
SDIN 207 I Serial InterfaceData Input

SCLK 210 I Serial InterfaceClock

SCE 209 I Serial Interface ENABLE. When Low the Incoming Dataare Clocked In.

SD/C 208 I Serial InterfaceData/Command selection

BSYFLG 206 O Active Procedure Flag. Notice if There is an ongoing Internal Operation. Active

Low.

T1 to T13 178 to 181

I/O Test Pads.

202 to 205

226

252 to 256

2/36

STE2001

ABSOLUTEMAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

DD2,3

V

P

T

DD1

LCD

I

SS

V
I

I

out

P

T

in

tot

stg

Supply Voltage Range - 0.5 to + 6.5 V
Supply Voltage Range - 0.5 to + 5 V
LCD Supply Voltage Range - 0.5 to + 10 V
Supply Current - 50 to +50 mA
Input Voltage(all input pads) -0.5 to V

i

DD2,3

DC Input Current - 10 to + 10 mA
DC Output Current - 10 to + 10 mA
Total Power Dissipation (Tj=85°C) 300 mW
Power Dissipation per Output 30 mW

o

Operating Junction Temperature -40 to + 85 °C

j

Storage Temperature - 65 to150 °C

+ 0.5 V

ELECTRICAL CHARACTERISTICS
DC OPERATION

(V

DD1

= 1.9to V

DD2,3

+ 0.5V; V

= 2.4 to 4.5 V; V

DD2,3

ss1,2

= 0V; V

= 4.5to 9V; T

LCD

=-40to 85°C; unless otherwise

amb

specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Supply Voltages

V

DD1

V

DD2,3

V

LCDIN

V

LCDOUT

I(V

I(V

DD2,3

Supply Voltage 1.9

Supply Voltage LCD Voltage Internally

LCD Supply Voltage LCD Voltage Supplied externally 4.5 9 V
LCD Supply Voltage Internally generated; note 1 4.5 9 V

) Supply Current VDD= 2.8V;V

DD1

) Voltage Generator Supply

Current

T

=-20 to 85°C

amb

generated

= 7.6V; 4x

LCD

charge pump; f

=25°C; note 3.

T

amb

sclk

=0;

with VOP = 0 and PRS= 0
with external V

V

=7.6V; VDD=2.8V;

LCD

=0;T

f

sclk

amb

= 7.6V

LCD

=25°C; no display
load; 4x charge pump; note 3,6
F

=0

osc

V

DD2,3

+0.5

1.8

V

DD2,3

+0.5

2.4 4.5 V

815µA

10 15

70 115 µA

V

V

A

µ

3/36

STE2001

ELECTRICAL CHARACTERISTICS

(continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

I(V

) TotalSupply Current V

DD1,2,3

= 7.6V; VDD=2.8V;

LCD

4x charge pump; f

sclk

=0;T

amb

80 125 µA

=25°C; no displayload; note 3,6
F

=0

osc

I(V

) External LCD Supply Voltage

LDCIN

Current

VDD=2.8V; V
display load; f

=25°C; note 3. F

T

amb

LCD

sclk

=7.6V;no
=0;

osc

=0

15 25 µA

Logic Inputs

V

V

I

Logic LOW voltage level VIN=Vih(tp<10µs) V

IL

Logic HIGH Voltage Level VIN=Vil(tp<10µs) 0.7

IH

Input Current Vin=V

in

SS1

or V

DD1

SS

V

DD

0.3

V

DD

V

DD2,3

+0.5

-1 1 µA

Columnand Row Driver

R

R
V

V

ROWOutput Resistance 12 20 kohm

row

Column Output resistance 12 20 kohm

col

Column Bias voltage accuracy No load -100 100 mV

col

Row Bias voltage accuracy -100 100 mV

row

LCD Supply Voltage

V

LCD

LCD Supply Voltage accuracy;
Internally generated

VDD= 2.8V;V

LCD

= 7.6V;

fsclk=0; Tamb=25 C;

-300 300 mV

no display load; note 2, 3, 6 & 7

TC Temperature coefficient 00 -550

PPM/°C

01 -1350 PPM/°C
10 -1650 PPM/°C
11 -2650 PPM/°C

Notes: 1. The maximum possible V

2. Internalclock

3. When f

4. Power-down mode. During power-down all static currents are switched-off.

5. If external V

6. Tolerance depends on the temperature; (typically zero at T
ature range limit.

7. ForTC0 to TC3

= 0 there is no interface clock.

sclk

, the display load current is not transmitted to I

LCD

voltage that can be generated is dependent on voltage, temperature and (display) load.

LCD

DD

=27°C), maximum tolerance values are measured at the temper-

amb

V

V

AC OPERATION

(V

DD1

= 1.9to V

DD2,3

+ 0.5V; V

= 2.4 to 4.5 V; V

DD2,3

ss1,2

= 0V; V

= 4.5to 9V; T

LCD

=-40to 85°C; unless otherwise

amb

specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

INTERNAL OSCILLATOR

F

F

OSC

EXT

Internal Oscillator frequency VDD= 2.8V; 20 38 70 kHz
External Oscillator frequency 20 38 100 kHz

4/36

STE2001

ELECTRICAL CHARACTERISTICS

(continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

F

FRAME

T

VHRL

T

w(RES)

Frame frequency fosc or fext = 38 kHz; note 1 73 Hz
Vdd1 to RES Low note 2 and 10; C

=1µF0 5ms

VLCD

RES LOW pulse width note 3 600 ns
Reset Pulse Rejection T

=25°C; note 11 370 µs

amb

Reset Pulse Rejection note 11 200

T

START

T

VDD

2

I

C BUS INTERFACE (See note 4)

F

SCL

T

SCLL

T

SCLH

T

SCLL

T

SCLH

T

SU;DAT

T

HD;DAT

T

SU;DAT

T

HD;DAT

T

SU;STA

T

SU;STA

T

HD;STA

T

HD;STA

T

SU;STO

T

SU;STO

T
T

T

rCL1

T

rCL1

T
T
T
T

Reset Pulse vs. Device Ready 1 ms

0

SCL Clock Frequency Fast Mode ;V

=18V; T

V

DD1

High Speed Mode; Cb=100pF
(max); note 6; V

High Speed Mode; Cb=400pF
(max); note 6 ; V

=4.5V DC 400 kHz

DD1

= -20 to 70°C 400 kHz

amb

DC 3.4 MHz

=4.5V

DD1

DC 1.7 MHz

=4.5V

DD1

Cb=100pF 160 ns
Cb=100pF 160 ns
Cb=400pF 320 ns
Cb=400pF 320 ns
Cb=100pF 30 ns
Cb=100pF 30 ns
Cb=400pF 30 ns
Cb=400pF 30 ns
Cb=100pF Note 8 170 ns
Cb=400pF Note 8 330 ns
Cb=100pF Note 8 170 ns
Cb=400pF Note 8 330 ns
Cb=100pF Note 8 170 ns
Cb=400pF Note 8 330 ns
Cb=100pF Note 5, 8 25 ns

rCL

Cb=400pF Note 5, 8 50 ns

rCL

Cb=100pF Note 5, 8 30 ns
Cb=400pF Note 5, 8 120 ns
Cb=100pF Note 5, 8 30 ns

rDA

Cb=400pF Note 5, 8 120 ns

rDA

Cb=100pF Note 5, 8 25 ns

fCL

Cb=400pF Note 5, 8 50 ns

fCL

s

µ

5/36

STE2001

ELECTRICAL CHARACTERISTICS

(continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

T
T

C

Cb=100pF 25 ns

fDA

Cb=400pF 120 ns

fDA

Capacitive load for SDAH and

b

100 400 pF

SCLH

C

Capacitive load for SDAH + SDA

b

400 pF

line and SCLH + SCL line

T

SW

note 5 10 ns

PARALLEL INTERFACE

T

CY(EN)

T

W(EN)

T

SU(A)

T

H(A)

T

SU(D)

T

H(D)

Enable Cycle Time VDD= 4.5V;Write 125 ns
Enable Pulse width VDD= 4.5V;Write 60 ns
Address Set-up Time VDD= 4.5V;Write 30 ns
Address Hold Time VDD= 4.5V;Write 50 ns
Data Set-Up Time VDD= 4.5V;Write 30 ns
Data Hold Time VDD= 4.5V;Write 50 ns

SERIAL INTERFACE

F

SCLK

T

T

PWH1

T

PWL1

T
T

T

PWH2

T
T
T
T
T

CYC

Clock Frequency VDD= 4.5V 8 MHz

V

= 1.8V 5 MHz

DD1

Clock Cycle SCLK VDD= 4.5V 125 ns
SCLK pulse width HIGH VDD= 4.5V 70 ns
SCLK Pulse width LOW VDD= 4.5V 70 ns
SCE setup time 50 ns

S2

SCE hold time 50 ns

H2

SCE minimum high time 60 ns
SCE start hold time Note 8 60 ns

H5

SD/C setup time 60 ns

S3

SD/C hold time 40 ns

H3

SDIN setup time 40 ns

S4

SDIN hold time 40 ns

H4

f

Notes: 1.

F

frame

2. RES may be LOW or HIGH before V

3. If T

w(RES)

4. All timing values are valid within the operatingsupply voltage and ambient temperature ranges and referenced toV
an inputvoltage swing of V

5. Therise and fall times specified here refer to the driver device and arepart of general Hs-mode specification.

6. Thedevice inputs SDA and SCLare filtered and will reject any spike on the bus-lines of with T

7. Cb is thecapacitive load for each bus line.

8. T

H5

9. Forbus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated

10.C

VLCD

11.If T

w(RES)

osc

----------=

520

goes HIGH.

to V

DD1

DD

is longer than 500ns (typical) a reset may be generated.

SS

is the time from theprevious SCLK positive edge to the negative edge of SCE

is the filteringcapacitor on VLCDOUT

is shorter than max.value a reset pulse is rejected.

SW

6/36

and VIHwith

IL

STE2001

CIRCUITDESCRIPTION
SuppliesVoltages and Grounds

V

andV

DD2

If the internal voltagegenerator is not used, these should be connectedto V
This supply voltage could be different form V

InternalSupply Voltage Generator

The IC has a fullyintegrated (no external capacitorsrequired)charge pump for the Liquid CrystalDisplay supplyvolt­age generation. The multiplyingfactor can be programmed to be: X5; X4; X3; X2, using the ’set CP Multiplication’
Command. The output voltage (V
ferent temperaturecoefficients(TC, rateof changewithtemperature) can beprogrammedusing the bitsTC1 and TC0.
This will ensure no contrast degradation over theLCD operating range. Using the internal charge pump, the V
and V

LCDOUT

without using the internal generator. In such event the V
internal voltagegenerator must be programmed to zero (PRS = 0, Vop = 0 - Reset condition).

Oscillator

A fully integrated oscillator (requires no externalcomponents) is present to provide the clock for the DisplaySystem.
Whenused theOSCpadmustbeconnectedtoVDD1pad. Anexternaloscillatorcouldbeused andfedintotheOSCpin.

DisplayData RAM

The STE2001, provides an 65X128 bits Static RAM to store Display data. This is organized into 8 (Bank0 to
Bank7) banks with 128 Bytes and one Bank (Bank8) with 128 Bits to be used for icons. RAM access is accom­plished in either one of the Bus Interfaces provided (seebelow). Allowed addresses are X0 to X127 (Horizontal)
and Y0 to Y8 (Vertical). When writing to RAM, four addressing mode are provided:

• NormalHorizontal (MX = 0 and V = 0), having the column with address X = 0 locatedon the left ofthe memorymap.
The Xpointerisincreased after each byte written. After the lastcolumnaddress(X = 127), Yaddress pointer is mod­ified to jump to nextrow. X restarts fromX = 0 (Fig.2).

• Normal Vertical (MX = 0 and V = 1), having the column with address X = 0 located on the left of the memory map.
The Y pointeris increased after each byte written. After the last row address (Y = 8), the X pointer is modified to
jump to next column and Y restarting from Y = 0. (Fig. 3).

• Mirrored Horizontal (MX = 1 and V = 0), having the column with address X = 0 located on the right of the memory
map. The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer
is modified to jump to nextrow. X restarts from X = 0 (fig. 4).

• Mirrored Vertical (MX =1 andV = 1), havingthe columnwith address X = 0 located onthe rightof the memory map.
The Y pointeris increased after each byte written. After the last row address (Y = 8), the X pointer is modified to
jump to next column and Y restarting from Y = 0. (Fig. 5).

After the last allowed address (X;Y) = (128;8), the address pointers always jump to the cell with address (X;Y)= (0;0). Data
bytes in the memory couldhave the MSB either on top (D0 = 0, Fig. 6) oron the bottom (D0 = 1, Fig. 7).

are supply voltagesto the internalvoltagegenerator(see below). Theymust be externally connected.

DD3

and V

DD2

) is tightlycontrolled through the V

LCDOUT

DD3.VDD1

must be lower than V

pads must beconnected together. An external supply couldbeconnected to V

LDCOUT

and V

LCDSENSE

pad. V

DD1

LCDSENSE

supplies the rest of the IC.

DD1

+ 0.5V.

DD2,3

pad. For this voltage, four dif-

to supply the LCD

LCDIN

must be connected to GND and the

LCDIN

Mux 65 Mode

The STE2001 provides also means to alter the normal output addressing.A mirroring of the Display along the X axis
is enabled setting to a logic one the MY bit. This function is achievedreading the matrix from physical row 63 to 0,
since the relation between the physical memory rows and the output row drivers is only dependent on the memory
reading sequence (1st row read output on R0, 2nd on R1... last on R65). This function doesn’t affect the content of
the memory map. It is only related to the visualizationprocess (Fig. 8 & Fig. 9).
It is also possible to modify thewhywith whichrow driversare connected withDDRAM memory.A flip along y-axisof
each sub-block can be appliedon both the Row Pads located onthe Interface Side(the edge of the chip where the
Interface Padsare located),setting the TRS bitto a logic one, andon the Row Pads located onthe otheredge,setting
the BRS bitto a logic one.
Figure 2 Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) Figure 3 Automatic
data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)

7/36

STE2001

Figure 2. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)

BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8

0123 124125126127

D00IN1138

Figure 3. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)

BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8

0 1 2 3 124 125 126 127

D00IN1139

Figure 4. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)

BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8

127126125124 3210

D00IN1140

Figure 5. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)

BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8

8/36

127 126 125 124 3 2 1 0

D00IN1141

Figure 6. Data RAM Byte organization with D0 = 0

MSB

0

1 2 3 124 125 126 127
BANK 0
BANK 1
BANK 2
BANK 3

LSB

BANK 4
BANK 5
BANK 6
BANK 7
BANK 8

Figure 7. Data RAM Byte organization with D0 = 1

LSB

0

1 2 3 124 125 126 127

MSB

BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8

STE2001

D00IN1142

D00IN1143

Figure 8. Output drivers rows and physical memory rows correspondence with MY =0

PHYSICAL MEMORY ROWROW DRIVER

0
R0
R1
R2
R3
R4
R5

R60
R61
R62
R63
R64

ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5

ROW 60
ROW 61
ROW 62
ROW 63
ROW 64

1 2 3 124 125 126 127

D00IN1144

Figure 9. Output drivers rows and physical memory rows correspondence with MY =1

PHYSICAL MEMORY ROWROW DRIVER

0
R63
R62
R61
R60
R59
R58

R3
R2
R1
R0

R64

ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5

ROW 60
ROW 61
ROW 62
ROW 63
ROW 64

1 2 3 124 125 126 127

D00IN1145

9/36

STE2001

MUX 33 Mode

When using the 1:33 MUX ratio (MUX bit Set), the memory map is changed so that the only”active” row drivers
are the ones related to Bank4 to Bank7.

When writing data RAM, as for Mux 65, four addressing mode are provided. The memory matrix is written as in
mux 65 mode so the user must take care of updating X and Y pointers to fill the memory matrix in the correct
way.

In MUX 33 mode only the MUX 33 memory logic matrix is read. The MY bit control the reading process. If MY

is set to a logic zero the row reading sequence is 0-1-2..........33 (fig.11). If MY is set to a logic one the reading

sequence is 32....1-33 (Fig12).

The icon row (BANK8) is always the last being output either MY bit is a logic one or zero.
The functions relatedto bit TRS is the same as in MUX 65 mode.
In fig. 11 is shown the output drivers pad connection for MUX 33 mode. Note that the unused BANK 0-3 row

drivers become columns drivers.
If a 33x128 LCD matrix is driven, the output row drivers R0-R15and R32-R47 must be floating.

Figure 10. Physical 65x128 memory matrix and 33x128 correspondence

0 1 14 15 16 17 18 112 113110 111109 126127

BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8

NOT USED

D00IN1146

10/36

R16-R23
R24-R31
R48-R55
R56-R63

R64

C1

C0C3C2C5C4C7C6

C121

C120

C123

C122

C124

C125

C126

D00IN1147

C127

Figure 11. Output drivers rows and logical memory rows correspondence with MY = 0

ROW DRIVER MUX 33PHYSICAL MEMORY ROW

STE2001

R16
R23

R24
R31

R48
R55

R56
R63

R64 Row 32

Row 0

to

Row 7
Row 8

to

Row15

Row 16

to

Row 23
Row 24

to

Row 31

01234567 123 124 125121 122120 126127

to

to

to

to

BANK 4

BANK 5

BANK 6

BANK 7
BANK 8

D00IN1148

Figure 12. Output drivers rows and logical memory rows correspondence with MY = 1

ROW DRIVER MUX 33PHYSICAL MEMORY ROW

R16
R23

R24
R31

R48
R55

R56
R63

R64 Row 32

Row 0

to

Row 7
Row 8

to

Row15

Row 16

to

Row 23
Row 24

to

Row 31

01234567 123 124 125121 122120 126127

to

to

to

to

BANK 4

BANK 5

BANK 6

BANK 7
BANK 8

D00IN1148

InstructionSet

Two different instructions formats are provided:

- With D/C set to LOW
commands are sent to the Control circuitry.

- With D/C set to HIGH
the Data RAM is addressed Instructions have the syntax summarized in Table.1.

Reset (RES)

At power-on, all internal registers and RAM content are not defined. A Reset pulse mustbe applied on RES pad
(active low) toinitialize the internal registers content (see Tables 3,4,5,&6). Every on-going communication with
the host controller is interrupted. The IC after the reset pulse is programmed in Power Down mode.

The Default configurations is:

- Horizontaladdressing (V = 0)

- Normal instruction set (H = 0)

- Normal display (MX = MY = TRS =BRS = 0)

- MUX 65 mode (MUX= 0)

11/36