The STE10/100A is a high performance PCI Fast
Ethernet controller with int egrated physical layer i nterface for 10BASE-T and 100BASE-TX application.
It was designed with advanced CMOS technology to
provide glueless 32-bit bus mast er interface for PCI
bus, boot ROM interface, CSMA/CD protocol for Fast
Ethernet, as well as the physical media interface for
100BASE-TX of IEEE802.3u and 10BASE-T of
IEEE802.3. The auto-negotiation function is also
supported for speed and duplex detection.
The STE10/100A provides both half-dupl ex and f ul l duplex operation, as well as support for full-duplex
flow control. It provides long FIFO buffers f or transmission and receiving, and early interrupt mechanism to enhance performance. The STE10/100A also
supports ACPI and PCI compliant power management function.
2.0 FEATURES
2.1 Industry standard
■ IEEE802.3u 100BASE-TX and IEEE802.3
10BASE-T comp l ia n t
■ Support for IEEE802.3x flow control
■ IEEE802.3u Auto-Negotiation support for
10BASE-T and 100BASE-TX
STE10/100A
WITH INTEGRATED PHY (3.3V)
PQFP128 (14x20x2.7mm)
ORDERING INFO:
STE10/100A - Commercial Temp version
STE10/100E - Industrial Temp version
■ PCI bus interface Rev. 2.2 compliant
■ ACPI and PCI power management standard
compliant
■ Support for PC99 wake on LAN
■ Provides 32-bit PCI bus master data transfer at
PCI clocks of 20-33 MHz
■ Provides writeable EEPROM/ Boot Rom
Interface
■ Provides independent transmission and
receiving FIFOs, each 2k bytes long
■ Supports big endian or little endian byte
ordering
Figure 1. STE10/100A Block Diagram
November 2002
REVISION: A07
Details are subject to change without notice.
1/66
STE10/100A
2.2 FIFO
■ Provides independent transmission and receiving FIFO s , each 2k bytes long
■ Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us
■ Retransmits collid ed pac ke t without reload from hos t memory wit hin 64 bytes.
■ Automatically retransmits FIFO under-run packet with max. drain threshold until 3rd time retry failure
threshold of next packet.
2.3 PCI I/F
■ Provides 32-bit PCI bus master data transfer
■ Supports PCI clock with frequency from 0Hz to 33MHz
■ Supports network operation with PCI system clock from 20MHz to 33MHz
■ Provides performance meter and PCI bus master latency timer for tuning the threshold to enhance the
performance
■ Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU
utilizatio n
■ As bus master, supports memory-read, memory-read-line, memory-read-multiple, memory-write,
memory-write-and-invalidate command
■ Supports big or little endian byte ordering
2.4 EEPROM/Boot ROM I/F
■ Provides writeable Flash ROM and EPROM as boot ROM, up to 128kB
■ Provides PCI to access boot ROM by byte, word, or double word
■ Re-writes Flash boot ROM through I/O port by programming register
■ Provides serial interface for read/write 93C46 EEPROM
Minimum-Grand from the 64 byte contents of 93C46 after PCI reset de-asserted
2.5 MAC/Physical
■ Integrates the complete set of Physical layer 100BASE-TX and 10BASE-T functions
■ Provides Full-duplex operation in both 100Mbps and 10Mbps modes
■ Provides Auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbps
■ Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
■ Provides transmit wave-shaper, receive filters, and adaptive equalizer
■ Provides MAC and Transceiver (TXCVR) loop-back modes for diagnostic
■ Built-in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
■ Supports external transmit and receive transformer with 1:1 turn ratio
2.6 LED Display
■ Provides 2 LED display modes:
3 LED displays for
100Mbps (on) or 10Mbps (off)
Link (Remains on when link ok) or Activity (Blinks at 10Hz when receiving or transmitti ng collisi on-free)
FD (Remains on when in Full duplex mode) or when collision detected (Blinks at 20Hz)
2/66
STE10/100A
4 LED displays for
100 Link (On when 100M link ok)
10 Link (On when 10M link ok)
Activity (Blinks at 10Hz when receiving or transmitting)
FD (Remains on when in Full duplex mode) or when collision detected (Blinks at 20Hz)
■ If no LED is used, then: Pull the pins 90, 91, 92 of U4 to high with 4.7K resistor (see STE10/100A
evaluation board schematics for details)
2.7 Miscellaneous
■ ACPI and PCI compliant power management functions offer significant power-savings performance
113INTA#O/DPCI interrupt request. STE10/100A asserts this signal when one of the interrupt
event is set.
114RST#IPCI Reset signal to initialize the STE10/100A. The RST signal should be
asserted for at least 100µs to ensure that the STE10/100A completes
initialization. During the reset period, all the output pins of STE10/100A will be
placed in a high-impedance state and all the O/D pins are floated.
116PCI-CLKIPCI clock input to STE10/100A for PCI Bus functions. The Bus signals are
synchronized relative to the rising edge of PCI-CLK PCI-CLK must operate at a
frequency in the range between 20MHz and 33MHz to ensure proper network
operation
117GNT#IPCI Bus Granted. This signal indicates that the STE10/100A has been granted
ownership of the PCI Bus as a result of a Bus Request.
118REQ#OPCI Bus Request. STE10/100A asserts this line when it needs access to the PCI
The Power Management Event signal is an open drain, active low signal. The
OD
I/OMultiplexed PCI Bus address/data pins
I/OBus command and byte enable
STE10/100A will assert PME# to indicate that a power management event has
occurred.
When WOL (bit 18 of CSR18) is set, the STE10/100A is placed in Wake On LAN
mode. While in this mode, the STE10/100A will activate the PME# signal upon
receipt of a Magic Packet frame from the network.
In the Wake On LAN mode, when LWS (bit 17 of CSR18) is set, the LAN-WAKE
signal follows HP’s protocol; otherwise, it is IBM protocol.
4IDSELIInitialization Device Select. This signal is asserted when the host issues
configuration cycles to the STE10/100A.
18FRAME#I/OAsserted by PCI Bus master during bus tenure
20IRDY#I/OMaster device is ready to begin data transaction
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STE10/100A
Table 1. Pin Description
Pin No.NameTypeDescription
21TRDY#I/OTarget device is ready to begin data transaction
22DEVSEL#I/ODevice select. Indicates that a PCI target device address has been decoded
23STOP#I/OPCI target device request to the PCI master to stop the current transaction
24PERR#I/OData parity error detected, driven by the device receiving data
25SERR#O/DAddress parity error
26PARI/OParity. Even parity computed for AD[31:0] and C/BE[3:0]; master drives PAR for
address and write data phase, target drives PAR for read data phase
BootROM/EEPROM Interface
56~59
61~66
80~86
87
67~71
72
73
74
76EECSOChip Select of serial EEPROM
77BrCS#OBootROM Chip Selec t
78BrOE#OBootROM Read Output Enable for flash ROM application
79BrWE# OBootROM Write Enable for flash ROM application.
Physical Interface
98X1I25 MHz reference clock input for Physical portion. When an external 25 MHz
97X2O25 MHz reference clock output for Physical portion. When an external 25MHz
BrA0~3
BrA4~9
BrA10~15
BrA16/
LED M2 -
Fd/Col
BrD0~4
BrD5/EDO
BrD6/EDI
BrD7/ECK
I/OROM data bus
Provides up to 128kB EPROM or Flash-ROM application space.
This pin can be programmed as mode 2 LED display for Full Duplex or Collision
status. It will be driven (LED on) continually when a full duplex configuration is
detected, or it will be driven at a 20 Hz blinking frequency when a collision status
is detected in the half duplex configuration.
O
O/I
O/O
O/O
BootROM data bus (0~7)
EDO: Data output of serial EEPROM, data input to STE10/100A
EDI:Data input to serial EEPROM, data output from STE10/100A
ECK:Clock input to serial EEPROM, sourced by STE10/100A
crystal is used, this pin will be connected to one of its terminals, and X2 will be
connected to the other terminal. If an external 25 MHz oscillator is used, then this
pin will be connected to the oscillator’s output pin.
crystal is used, this pin will be connected to one of the crystal terminals (see X1,
above). If an external clock source is used, then this pin should be left open.
107,109TX+, TX-OThe differential Transmit outputs of 100BASE-TX or 10BASE-T, these pins
105,104RX+, RX-IThe differential Receive inputs of 100BASE-TX or 10BASE-T, these pins connect
101IrefOReference Resistor connecting pin for reference current, directly connects a 5K
6/66
connect directly to Magnetic.
directly from Magnetic.
Ohm ± 1% resistor to Vss.
Table 1. Pin Description
Pin No.NameTypeDescription
LED display & Miscellaneous
STE10/100A
90LED M1-
LK/Act
or
LED M2-
Act
92LED M1-
Speed
or
LED M2-
100 Link
91LED M1-
Fd/Col
or
LED M2-
10 Link
89Vaux-
detect
OThis pin can be programmed as mode 1 or mode 2:
For mode 1:
LED display for Link and Activity status. This pin will be driven on continually
when a good Link test is detected. This pin will be driven at a 10 Hz blinking
frequency when either effective receiving or transmitting is detected.
For mode 2:
LED display for Activity status. This pin will be driven at a 10 Hz blinking
frequency when either effective receiving or transmitting is detected.
OThis pin can be programmed as mode 1 or mode 2:
For mode 1:
LED display for 100M b/s or 10M b/s speed. This pin will be driven on continually
when the 100M b/s network operating speed is detected.
For mode 2:
LED display for 100Ms/s link status. This pin will be driven on continually when
100Mb/s network operating speed is detected.
OThis pin can be programmed as mode 1 or mode 2:
For mode 1:
LED display for Full Duplex or Collision status. This pin will be driven on
continually when a full duplex configuration is detected. This pin will be driven at
a 20 Hz blinking frequency when a collision status is detected in the half duplex
configuration.
For mode 2:
LED display for 10Ms/s link status. This pin will be driven on continually when
10Mb/s network operating speed is detected.
IWhen this pin is asserted, it indicates an auxiliary power source is supported from
the system.
88Vcc-detectIWhen this pin is asserted, it indicates a PCI power source is supported.
There are three kinds of registers within the STE10/100A: STE10/100A configuration registers, PCI control/status registers, and Transceiver control/status registers.
The STE10/100A configuration registers are used to initialize and configure the STE10/100A and for identifying
and querying the STE10/100A.
The PCI control/status registers are used t o communicate between the host and STE10/100A. The host can
initialize, control, and read the status of the STE10/100A through mapped I/O or memory address space.
The STE10/100A contains 11 16-bit registers to supported Transceiver control and status. They include 7 basic
registers which are defined according to clause 22 “Reconciliation Sub-layer and Media Independent Interface”
and clause 28 “Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of the
IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status.
The STE10/100A also provides receive and transmit descriptors for packet buffering and management.
5.1 STE10/100A Configuration Registers
An STE10/100A software driver can i ni t iali z e and conf i gure the chip by writing i t s c onfi gurat i on regi st ers. The
contents of configuration registers are set to their default values upon power-up or whenever a hardware reset
occurs, but their settings remain unchanged whenever a s oftware reset occurs. The configuration registers are
byte, word, and double word accessible.
Table 2. STE10/100A configuration registers list
OffsetIndexN ameDescriptions
00hCR0LIDLoaded device ID and vendor ID
04hCR1CSCConfiguration Status and Command
08hCR2CCClass Code and revision number
0chCR3LTLatency Timer
10hCR4IOBAIO Base Address
14hCR5MBAMemory Base Address
2chCR11SIDSubsystem ID and vendor ID
30hCR12BRBABoot ROM Base Address (ROM size = 128KB)
34hCR13CPCapability Pointer
3chCR15CINTConfiguration Interrupt
40h CR16DSdriver space for special purpose
80hCR32SIGSignature of STE10/100A
c0hCR48PMR0Power Management Register 0
c4hCR49PMR1Power Management Register 1
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STE10/100A
Table 3. STE10/100A configuration registers table
offsetb31 ----------- b16b15 ---------- b0
00hDevice ID*Vendor ID*
04hStatusCommand
08hBase Class CodeSubclass------Revision #Step #
0ch------------Latency timercache line size
10hBase I/O address
14hBase memory address
18h~
28h
2chSubsystem ID*Subsystem vendor ID*
30hBoot ROM base address
34hReservedCap_Ptr
38hReserved
3chMax_Lat*Min_Gnt*Interrupt pinInterrupt line
40hReservedDriver Space Reserved
Reserved
80hSignature of STE10/1 00A
c0hPMCNext_Item_P trCap_ID
c4hReservedPMCSR
Note: * : automatically recalled from EEPROM when PCI reset is deserted
DS(40h), bit15-8, is read/write able register
SIG(80h) is hard wired register, read only
CR0(offset = 00h), LID - Loaded Identification number of Device and Vendor
31~16LDIDLoaded Device ID, the device ID number loaded from serial
EEPROM.
15~0LVIDLoaded Vendor ID, the vendor ID number loaded from serial
EEPROM.
From EEPROM: Loaded from EEPROM
CR1(offset = 04h), CSC - Configuration command and status
31SPEStatus Parity Error.
1: means that STE10/100A detected a parity error. This bit will
be set even if the parity error response (bit 6 of CR1) is
disabled.
From
EEPROM
From
EEPROM
0R/W
R/O
R/O
30SESStatus System Error.
1: means that STE10/100A asserted the system error pin.
0R/W
9/66
STE10/100A
Table 4. Configuration Registers Descriptions
Bit #NameDescriptionsDefault ValRW Type
29SMASt atus Maste r Abort.
1: means that STE10/100A received a master abort and has
terminated a master transaction.
28STASt atus Target Abort.
1: means that STE10/100A received a target abort and has
terminated a master transaction.
27---Reserved.
26, 25SDSTStatus Device Select Timing. Indicates the timing of the chip’s
assertion of device select.
01: indicates a medium assertion of DEVSEL#
24SDPRStatus Data Parity Report.
1: when three conditions are met:
a. STE10/100A asserted parity error (PERR#) or it detected
parity error asserted by another device.
b. STE10/100A is operating as a bus master.
c. STE10/100A’s parity error response bit (bit 6 of CR1) is
enabled.
23SFBBStatus Fast Back-to-Bac k
Always 1, since STE10/100A has the ability to accept fast
back to back transactions.
22~21---Reserved.
20NCNew Capabilities. Indicates whether the STE10/100A provides
a list of extended capabilities, such as PCI power
management.
1: the STE10/100A provides the PCI management function
0: the STE10/100A doesn’t provide New Capabilities.
0R/W
0R/W
01R/O
0R/W
1R/O
Same as
bit 19 of
CSR18
RO
19~ 9---Reserved.
8CSECommand System Error Response
1: enable system error response. The STE10/100A will assert
SERR# when it finds a parity error during the address phase.
7---Reserved.
6CPECommand Parity Error Response
0: disable parity error response. STE10/100A will ignore any
detected parity error and keep on operating. Default value is
0.
1: enable parity error response. STE10/100A will assert
system error (bit 13 of CSR5) when a parity error is
detected.
5~ 3 ---Reserved.
2CMOCommand Master Opera tion Ability
0: disable the STE10/100A bus master ability.
1: enable the PCI bus master ability. Default value is 1 for
normal operation.
1CMSA Command Memory Space Access
0: disable the memory space access ability.
1: enable the memory space access ability.
10/66
1R/W
0R/W
1R/W
1R/W
STE10/100A
Table 4. Configuration Registers Descriptions
Bit #NameDescriptionsDefault ValRW Type
0CIOSACommand I/O Space Access
R/W: Read and Write ab le. RO: Read able only.
CR2(offset = 08h), CC - Class Code and Revision Number
31~24BCC Base Class Code. It means STE10/100A is a network
23~16SCSubclass Code. It means STE10/100A is a Fast Ethernet
15~ 8---Reserved.
7 ~ 4RNRevision Number, identifies the revision number of STE10/
3 ~ 0SNStep Number, identifies the STE10/100A steps within the
RO: Read Only.
CR3(offset = 0ch), LT - Latency Timer
31~16--- Reserved.
15~ 8LTLatency Timer. This value specifies the latency timer of the
0: enable the I/O space access ability.
1: disable the I/O space access ability.
controller.
Controller.
100A.
current revision.
STE10/100A
asserts FRAME#, the latency timer starts to count. If the
100A
latency timer expires and the STE10/100A is still asserting
FRAME#, the STE10/100A will terminate the data transaction
as soon as its GNT# is removed.
in units of PCI bus clock cycles. Once the STE10/
1R/W
02hRO
00hRO
AhRO
1hRO
40hR/W
7 ~ 0CLS Cache Line Size. This value specifies the system cache line
size in units of 32-bit double words(DW). The STE10/100A
supports cache line sizes of 8, 16, or 32 DW. CLS is used by
the STE10/100A driver to program the cache alignment bits
(bit 14 and 15 of CSR0) which are used for cache oriented PCI
31~ 7IOBAI/O Base Address. This value indicate the base address of PCI
control and status register (CSR0~28), and Transceiver
registers (XR0~10)
6 ~ 1---reserved.
0IOSII/O Space Indicator.
1: means that the configuration registers map into I/O space.
CR5(offset = 14h), MBA - Memory Base Address
31~ 7MBAMemory Base Address. This value indicate the base address
of PCI control and status register(CSR0~28), and Transceiver
registers(XR0~10)
6 ~ 1---reserved.
08hR/W
0R/W
1RO
0R/W
11/66
STE10/100A
Table 4. Configuration Registers Descriptions
Bit #NameDescriptionsDefault ValRW Type
0IOSI Memory Space Indicator.
1: means that the configuration registers map into I/O space.
CR11(offset = 2ch), SID - Subsystem ID.
31~16SIDSubsystem ID. This value is loaded from EEPROM as a result
of power-on or hardware reset.
15~ 0SVIDSubsystem Vendor ID. This value is loaded from EEPROM as
a result power-on or hardware reset.
CR12(offset = 30h), BRBA - Boot ROM Base Address. This register should be initialized before accessing the
boot ROM space.
31~10BRBABoot ROM Base Address. This value indicates the address
mapping of the boot ROM field as well as defining the boot
ROM size. The values of bit 16~10 are set to 0 indicating that
the STE10/100A supports up to 128kB of boot ROM.
9 ~ 1---reservedRO R/W R/
0BREBoot ROM Enable. The STE10/100A will only enable its boot
ROM access if both the memory space access bit (bit 1 of
CR1) and this bit are set to 1.
1: enable Boot ROM. (if bit 1 of CR1 is also set)
CR13(offset = 34h), CP - Capabilities Pointer.
31~8---reserved
0RO
From
EEPROM
From
EEPROM
X: b31~17
0: b16~10
0R/W
RO
RO
R/W
RO
W
7~0CPCapabilities Pointer. C0HRO
CR15(offset = 3ch), CI - Configuration Interrupt
31~24MLMax_Lat register. This value indicates how often the STE10/
100A needs to access to the PCI bus in units of 250ns. This
value is loaded from serial EEPROM as a result of power-on
or hardware reset.
23~16MGMin_Gnt register. This value indicates how long the STE10/
100A needs to retain the PCI bus ownership whenever it
initiates a transaction, in units of 250ns. This value is loaded
from serial EEPROM as a result power-on or hardware reset.
15~ 8IPInterrupt Pin. This value indicates one of four interrupt request
pins to which the STE10/100A is connected.
01h: means the STE10/100A always connects to INTA#
7 ~ 0ILInterrupt Line. This value indicates the system interrupt
request lines to which the INTA# of STE10/100A is routed. The
BIOS will fill this field when it initializes and configures the
system. The STE10/100A driver can use this value to
determine priority and vector information.
CR16(offset = 40h), DS - Driver Space for special purpose.
31~16--- reserved
From
EEPROM
From
EEPROM
01hRO
0R/W
RO
RO
12/66
STE10/100A
Table 4. Configuration Registers Descriptions
Bit #NameDescriptionsDefault ValRW Type
15~8DSDriver Space for implementation-specific purpose. Since this
7 ~ 0---reserved
CR32(offset = 80h), SIG - Signature of STE10/100A
31~16DIDDevice ID, the device ID number of the STE10/100A.2774hRO
15~0VIDVendor ID, the vendor ID number of STMicroelectronics104AhRO
CR48(offset = c0h), PMR0, Power Management Register0.
31
30
29
28
27
26D2SD2_Support. The STE10/100A supports the D2 Power
25D1SD1_Support. The STE10/100A supports the D1 Power
PSD3c,
PSD3h,
PSD2,
PSD1,
PSD0
area won’t be cleared upon software reset, an STE10/100A
driver can use this R/W area as user-specified storage.
PME_Support.
The STE10/100A will assert PME# signal while in the D0, D1,
D2, D3hot and D3cold power state. The STE10/100A supports
Wake-up from the above five states. Bit 31 (support wake-up
from D3cold) is loaded from EEPROM after power-up or
hardware reset. To support the D3cold wake-up function, an
auxiliary power source will be sensed during reset by the
STE10/100A V aux_detect pin. If sensed low, PSD3c will be set
to 0; if sensed high, and if D3CS (bit 31of CSR18) is set
(CSR18 bits 16~31 are recalled from EEPROM at reset), then
bit 31 will be set to 1.
Management State.
Management State.
0R/W
X1111bRO
1RO
1RO
24~22AUXCAux Current. These three bits report the maximum 3.3Vaux
current requirements for STE10/100A chip. If bit 31 of PMR0 is
‘1’, the default value is 111b, meaning the STE10/100A needs
375 mA to support remote wake-up in D3cold power state.
Otherwise, the default value is 000b, meaning the STE10/100A
does not support remote wake-up from D3cold power state.
21DSIThe Device Specific Initialization bit indicates whether any
special initialization of this function is required before the
generic class device driver is able to use it.
0: indicates that the function does not require a device-specific
initialization sequence following transition to the D0
uninitialized state.
20---Reserved.
19PMECPME Clock. Indicates that the STE10/100A does not rely on
the presence of the PCI clock for PME# operation
18~16VERVersion. The value of 010b indicates that the STE10/100A
complies with Revision 1.0a of the PCI Power Management
Interface Specification.
15~8NIPNext Item Pointer. This value is always 0h, indicating that there
are no additional items in the Capabilities List.
7~0CAPIDCapability Identifier. This value is always 01h, indicating the
link list item as being the PCI Power Management Registers.
XXXbRO
0RO
0RO
010bRO
00hRO
01hRO
13/66
STE10/100A
Table 4. Configuration Registers Descriptions
Bit #NameDescriptionsDefault ValRW Type
CR49(offset = c4h), PMR1, Power Management Register 1.
31~16--- reserved
15PMESTPME_Status. This bit is set whenever the STE10/100A detects
a wake-up event, regardless of the state of the PME-En bit.
Writing a “1” to this bit will clear it, causing the STE10/100A to
deassert PME# (if so enabled). Writing a “0” has no effect.
If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not support
PME# generation from D3cold), this bit is by default 0;
otherwise, PMEST is cleared upon power-up reset only and is
not modified by either hardware or software reset.
14,13DSCALData_Scale. Indicates the scaling factor to be used when
interpreting the value of the Data register. This field is required
for any function that implements the Data register.
The STE10/100A does not support Data register and
Data_Scale.
12~9DSELData_Select. This four bit field is used to select which data is
to be reported through the Data register and Data_Scale field.
This field is required for any function that implements the Data
register.
The STE10/100A does not support Data_select.
8PME_EnPME_En. When set, enables the STE10/100A to assert
PME#. When cleared, disables the PME# assertion.
If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not support
PME# generation from D3cold), this bit is by default 0;
otherwise, PME_En is cleared upon power up reset only and is
not modified by either hardware or software reset.
7~2---reserved.000000bRO
XR/W1C*
00bRO
0000bR/W
XR/W
1,0PWRSPowerState. This two bit field is used both to determine the
current power state of the STE10/100A and to place the
STE10/100A in a new power state. The definition of this field is
given below.
00b - D0
01b - D1
10b - D2
11b - D3hot
If software attempts to write an unsupported state to this field,
the write operation will complete normally on the bus, but the
data is discarded and no state change occurs.
R/W1C*, Read Only and Wri t e one cleared.
14/66
00bR/W
5.2 PCI Control/Status registers
Table 5. PCI Control/Status registers list
offset from base
address of CSR
00hCSR0PARPCI acces s register
08hCSR1TDRtransmit demand register
10hCSR2RDRreceive demand register
18hCSR3RDBreceive descriptor base address
20hCSR4TDBtransmit descriptor base address
28hCSR5SRstatus register
30hCSR6NARnetwork access register
38hCSR7IERinterrupt enable register
40hCSR8LPClost packet counter
48hCSR9SPRserial port register
IndexNameDescriptions
STE10/100A
50hCSR10---Reserved
58hCSR11TMRTimer
60hCSR12---Reserved
68hCSR13WCSRWake-up Control/Status Register
70hCSR14WPDRWake-up Pattern Data Register
78hCSR15WTMRwatchdog timer
80hCSR16ACSR5status register 2
84hCSR17ACSR7interrupt enable register 2
88hCSR18CRcommand register
8chCSR19PCICPCI bus performance counter
90hCSR20PMCSRPower Management Comm and and Status
94hCSR21- --Reserved
98hCSR22- --Reserved
9chCSR23TXBRtransmit burst counter/time-out register
a0hCSR24FROMflash(boot) ROM port
a4hCSR25PAR0physical address register 0
a8hCSR26PAR1physical address register 1
achCSR27MAR0multicast address hash table register 0
b0hCSR28MAR1multicast address hash table register 1
15/66
STE10/100A
Table 6. Control/Status register description
Bit #NameDescriptionsDefault ValRW Type
CSR0(offset = 00h), PAR - PCI Access Register
31~25---reserved
24MWIEMemory Write and Invalidate Enable.
1: enable STE10/100A to generate memory write invalidate
command. The STE10/100A will generate this command
while writing full cache lines.
0: disable generating memory write invalidate command. The
STE10/100A will use memory write commands instead.
23MRLEMemory Read Line Enable.
1: enable STE10/100A to generate memory read line
command when read access instruction reaches the cache
line boundary. If the read access instruction doesn’t reach
the cache line boundary then the STE10/100A uses the
13 ~ 8PBLProgrammable Burst Length. This value defines the maximum
number of DW to be transferred in one DMA transaction.
value: 0 (unlimited), 1, 2, 4, 8, 16(default), 32
7BLEBig or Little Endian selection.
0: little endian (e.g. INTEL)
1: big endian (only for data buffer)
6 ~ 2DSLDescriptor Skip Length. Defines the gap between two
descriptors in the units of DW.
1BARBus arbitration
0: receive operations have higher priority
1: transmit operations have higher priority
16/66
00R/W*
000000R/W*
0R/W*
0R/W*
0R/W*
STE10/100A
Table 6. Control/Status register description
Bit #NameDescriptionsDefault ValRW Type
0SWRSoftware reset
0R/W*
1: Reset all internal hardware (excluding transceivers and
configuration registers). This signal will be cleared by the
STE10/100A itself after the reset process is completed.
R/W* = Before writing the transmit and receive operations should be stopped.
While the STE10/100A is in the suspended state, a write to
FFFFFFFF
h
this register (any value) will trigger the read-tx-descriptor
process, which checks the own-bit; if set, the transmit process
is then started.
R/W* = Before writing the transmit process should be in the suspended state.
CSR2(offset = 10h), RDR - Receive demand register
31 ~ 0RPDMReceive poll demand
While the STE10/100A is in the suspended state, a write to this
FFFFFFFF
h
register (any value) will trigger the read-rx-descriptor process,
which checks the own-bit, if set, the process to move data
from the FIFO to buffer is then started.
R/W* = Before writing the receive process should be in the suspended state.
CSR3(offset = 18h), RDB - Receive descriptor base address
31~ 2SARStart address of receive descriptor0R/W*
1, 0RBNDmust be 00, DW boundary00RO
R/W*
R/W*
R/W* = Before writing the receive process should be stopped.
CSR4(offset = 20h), TDB - Transmit descriptor base address
31~ 2SATStart address of transmit descriptor0R/W*
1, 0TBNDmust be 00, DW boundary00RO
R/W* = Before writing the transmit process should be stopped.
CSR5(offset = 28h), SR - Status register
31~ 26----reserved
25~ 23BETBus Error Type. This field is valid only when bit 13 of
000RO
CSR5(fatal bus error) is set. There is no interrupt generated by
this field.
000: parity error, 001: master abort, 010: target abort
011, 1xx: reserved
17/66
STE10/100A
Table 6. Control/Status register description
Bit #NameDescriptionsDefault ValRW Type
22~ 20TSTransmit State. Reports the current transmission state only, no
interrupt will be generated.
000: stop
001: read descriptor
010: transmitting
011: FIFO fill, read the data from memory and put into FIFO
100: reserved
101: reserved
110: suspended, unavailable transmit descriptor or FIFO
overflow
111: write descriptor
19~17RSReceive State. Reports current receive state only, no interrupt
will be generated.
000: stop
001: read descriptor
010: check this packet and pre-fetch next descriptor
011: wait for receiving data
100: suspended
101: write descriptor
110: flush the current FIFO
111: FIFO drain, move data from receiving FIFO into memory
16NISSNormal Interrupt Status Summary. Set if any of the following
15AISSAbnormal Interrupt Status Summary. Set if any of the following
bits of CSR5 are asserted:
TPS, transmit process stopped (bit 1)
TJT, transmit jabber timer time-out (bit 3)
TUF, transmit under-flow (bit 5)
RDU, receive descriptor unavailable (bit 7)
RPS, receive process stopped (bit 8)
RWT, receive watchdog time-out (bit 9)
GPTT, general purpose timer time-out (bit 11)
FBE, fatal bus error (bit 13)
000RO
000RO
0RO/LH*
0RO/LH*
14----reserved
13FBEFatal Bus Error.
1: on occurrence of parity error, master abort, or target abort
(see bits 25~23 of CSR5). The STE10/100A will disable all bus
access. A software reset is required to recover from a parity
error.
12---reserved
11GPTTGeneral Purpose Timer Timeout, based on CSR11 timer
register
10---reserved
9RWTReceive Watchdog Timeout, based on CSR15 watchdog timer
register
8RPSReceive Process Stopped, receive state = stop0RO/LH*
18/66
0RO/LH*
0RO/LH*
0RO/LH*
STE10/100A
Table 6. Control/Status register description
Bit #NameDescriptionsDefault ValRW Type
7RDUReceive Descriptor Unavailable
1: when the next receive descriptor can not be obtained by the
STE10/100A. The receive process is suspended in this
situation. To restart the receive process, the ownership bit of
the next receive descriptor should be set to STE10/100A and a
receive poll demand command should be issued (if the receive
poll demand is not issued, the receive process will resume
when a new recognized frame is received).
6RCIReceive Completed Interrupt
1: when a frame reception is completed.
5T UFTransmit Unde r-Flow
1: when an under-flow condition occurs in the transmit FIFO
during transmitting. The transmit process will enter the
suspended state and report the under-flow error on bit 1 of
TDES0.
4---Reserved
3TJTTransmit Jabber Timer Time-out
1: when the transmit jabber timer expires. The transmit
processor will enter the stop state and TO (bit 14 of TDES0,
transmit jabber time-out flag) will be asserted.
2TDUTransmit Descriptor Unavailable
1: when the next transmit descriptor can not be obtained by
the STE10/100A. The transmission process is suspended in
this situation. To restart the transmission process, the
ownership bit of the next transmit descriptor should be set to
STE10/100A and, if the transmit automatic polling is not
enabled, a transmit poll demand command should then be
issued.
0RO/LH*
0RO/LH*
0RO/LH*
0RO/LH*
0RO/LH*
1T PSTransmit Proce ss Stopped .
1: while transmit state = stop
0TCITransmit Completed Interrupt.
1: set when a frame transmission completes with IC (bit 31 of
TDES1) asserted in the first transmit descriptor of the frame.
LH = High Latching and cleared by writing 1.
CSR6(offset = 30h), NAR - Network access register
31~22---reserved
21SFStore and forward for transmit
0: disable
1: enable, ignore the transmit threshold setting
20---reserved
19SQESQE Disable
0: enable SQE function for 10BASE-T operation. The STE10/
100A provides SQE test function for 10BASE-T half duplex
operation.
0: disable
1: generate collision upon transmit (for testing in loop-back
mode)
11, 10OMOperating Mode
00: normal
01: MAC loop-back, regardless of contents of XLBEN (bit 14 of
XR0, XCVR loop-back)
10,11: reserved
9, 8---reserved
7MMMulticast Mode
1: receive all multicast packets
6PRPromiscuous Mode
1: receive any good packet.
0: receive only the right destination address packets
5SBCStop Back-off Counter
1: back-off counter stops when carrier is active, and resumes
when carrier is dropped.
0: back-off counter is not effected by carrier
00R/W*
0R/W
0R/W**
00R/W**
0R/W***
1R/W***
0R/W**
4 ---reserved
3PBPass Bad packet
1: receives any packets passing address filter, including runt
packets, CRC error, truncated packets. For receiving all bad
packets, PR (bit 6 of CSR6) should be set to 1.
0: filters all bad packets
2---reserved
1SRStart/Stop Receive
0: receive processor will enter stop state after the current
frame reception is completed. This value is effective only
when the receive processor is in the running or suspending
state. Note: In “Stop Receive” state, the PAUSE packet and
Remote Wake Up packet will not be affected and can be
received if the corresponding function is enabled.
1: receive processor will enter running state.
0---reserved
W* = only write when the transmit processor stopped.
W** = only write when the tran smit and receive processor both stop ped .
W*** = only write when the receive processor stopped.