ST STDVE103A User Manual
Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer
Features
■ Digital video signal equalizer with 3:1 HDMI
switch
■ Compatible with the high-definition multimedia
interface (HDMI) v1.3 digital interface
■ 340 MHz maximum clock speed operation
supports all video formats with deep color at
maximum refresh rates
■ 3.4 Gbps data rate per channel
■ Fully automatic adaptive equalizer for cable
lengths up to 25 m
■ Selectable 50 Ω input termination to V
3.135 to 3.465 V
■ Low speed control lines supply to V
5 V (typ)
■ ESD HBM model: > ±5 KV for TMDS I/Os
■ Integrated open-drain I
data channel (DDC)
■ 5.3 V tolerant DDC and HPD I/Os
■ Lock-up free operation of I
■ 0 to 400 kHz clock frequency for I
■ Low capacitance TMDS channels
■ Equalizer for signal regeneration
■ Low output skew and jitter
Applications
■ Advanced TVs supporting the HDMI/DVI
standard
■ Front projectors, LCD TVs and PDPs
■ Monitors and notebooks
■ Set-top box and DVD players
Table 1. Device summary
Order code Operating temperature Package Packaging
2
C buffer for display
2
C bus
2
CC
:
DD
C bus
STDVE103A
TQFP64
:
Description
The STDVE103A integrates a 4-channel 3.4 Gbps
TMDS equalizer and a 3:1 switch to select one of
the three HDMI ports. The high-speed data paths
and flow-through pinout minimize the internal
device jitter and simplify the board layout. The
equalizer overcomes the jitter effects from lossy
cables. The buffer/driver on the output can drive
the TMDS output signals over long distances.
Also, STDVE103A integrates the 50 Ω
termination resistor on all the input channels to
improve performance and reduce board space.
The device can be placed in a low-power mode by
disabling the output current drivers.
The differential signal from the HDMI/DVI ports
can be routed through the STDVE103A to
guarantee good signal quality at the HDMI
receiver.
Designed for very low skew, jitter and low I/O
capacitance, the switch preserves the signal
integrity to pass the stringent HDMI compliance
requirements.
STDVE103ABTR -40°C to 85°C TQFP64 Tape and reel
STDVE103ABTY -40°C to 85°C TQFP64 Tray
June 2009 Doc ID 14911 Rev 4 1/44
www.st.com
44
Contents STDVE103A
Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.1 SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 I2C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8 Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 24
5.4 Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5 Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . 28
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.1 I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2/44 Doc ID 14911 Rev 4
STDVE103A Contents
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Doc ID 14911 Rev 4 3/44
List of tables STDVE103A
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Gain frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. DC specifications for TMDS differential outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. DC specifications for SEL (S1, S2) inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. DDC I/O pins (switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Status pins (HPD_SINK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16. Status pins (HPD1, HPD2, HPD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 20. Equalizer gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21. Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22. Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 23. Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 24. DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 25. Status pins (HPD_SINK, HPD1, HPD2, HPD3, S1, S2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 26. Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 27. I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 28. ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 29. TQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 30. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4/44 Doc ID 14911 Rev 4
STDVE103A List of figures
List of figures
Figure 1. STDVE103A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. DDC I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. STDVE103A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Pin configuration (TQFP64 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. STDVE103A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. Test circuit for turn off and turn off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. Test circuit for short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. TSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. TSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. TSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 19. I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20. Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. TQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. TQFP64 tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 23. TQFP64 tray drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 24. TQPF64 tray drawing dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Doc ID 14911 Rev 4 5/44
General description STDVE103A
1 General description
The STDVE103A is a TMDS/HDMI 3:1 switch with signal equalizer. The device is a HDMI
switch featuring an integrated 4-channel 3.4 Gbps TMDS equalizer and 3:1 switch to select
one of the three HDMI ports (either external ports or internal sources).
The high-speed data paths and flow-through pinout minimize the internal device jitter and
simplify the board layout.
The equalizer provides compensation to overcome the intersymbol interference (ISI) jitter
effects from lossy cables.
The output driver buffers the TMDS output signals over long distances.
Also, the STDVE103A integrates the 50 Ω termination resistor on all the input channels to
improve performance and reduce board space.
The device can operate in a low-power mode by disabling the output current drivers.
The STDVE103A is ideal for advanced TV and STB applications supporting the HDMI/DVI
standard. The differential signal from the HDMI/DVI ports can be routed through the
STDVE103A to guarantee good signal quality at the HDMI receiver. Designed for very low
skew, jitter and low I/O capacitance, the switch preserves the signal integrity to pass the
stringent HDMI compliance requirements.
The STDVE103A provides the ability to boost the incoming TMDS signal and drive it to a
level which allows efficient signal recovery at the HDMI receiver. It is especially useful for
boosting signals for longer distance transmission when the HDMI receiver is physically
distant from the HDMI input port.
6/44 Doc ID 14911 Rev 4
STDVE103A Block diagram
2 Block diagram
Figure 1. STDVE103A block diagram
HDMI input
port A
HDMI input
port B
HDMI input
port C
DDC port A
DDC port B
DDC port C
S1,S2
3:1
HDMI
input
select
switch
Input stage
2
2
2
Equalizer
DDC
switch
2
Output
driver/
transmitter
2
I C
repeater
HDMI output
port Y
DDC
port Y
HPD port A
HPD port B
HPD port C
HPD
analog
switch
Figure 2. Equalizer functional diagram (one signal pair)
S1, S2
Data+
Ω
Data-
50
termination
selectable
Pre-Amp
S1,S2
REXT
Switch
(3:1)
Current
control
Equalizer
HPD
port Y
CS00061A
Data+
driver
Quantizer
Output I
Data-
AM00716V1
Doc ID 14911 Rev 4 7/44
Block diagram STDVE103A
A
Figure 3. DDC I2C bus repeater
2
I
C Bus Repeater
A_DDC_SDA
B_DDC_SDA
C_DDC_SDA
Switch
A_DDC_SCL
B_DDC_SCL
C_DDC_SCL
S1, S2
2.1 Application diagrams
Figure 4. STDVE103A in a digital TV
Game
console
Y_DDC_SD
Y_DDC_SCL
DVD-R STB
Digital TV
STDVE103A
HDMI receiver
8/44 Doc ID 14911 Rev 4
CS00063A
STDVE103A Pin configuration
3 Pin configuration
Figure 5. Pin configuration (TQFP64 package)
SDA3
SCL3
GND
B31
A31
VCC
B32
A32
GND
B33
A33
VCC
B 34
A34
GND
REXT
A24
HPD3
B24
4
62
63
6
VCC
61
A23
60
B23
59
GND
58
B22
A22
57
56
55
A21
B21
SCL2
54
52
53
VCC
1
2
3
4
5
6
7
8
STDVE103A
9
10
11
12
13
14
15
16
7
1
4
Y
0
8
1
4
Z
1
9
2
1
3
C
Y
C
V
3
2
2
2
2
2
3
D
Y
Z
GN
6
4
2
2
Z
7
9
5
2
C
C
V
8
2
2
2
2
1
1
Y
K
D
Z
N
N
I
G
S
_
L
C
S
SDA2
51
VDD
HPD2
48
50
49
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
0
1
3
3
3
1
K
K
S
N
N
I
I
S
S
_
_
A
D
D
P
S
H
A14
B14
VCC
A13
B13
GND
A12
B12
VCC
A11
B11
SCL1
SDA1
HPD1
NC
S2
Table 2. Pin description
Pin number Pin name Type Function
1-2 SDA3, SCL3 I/O Port3 DDC bus data and clock lines
3 GND Power Ground
4-5 B31, A31 Input, TMDS Port 3 differential inputs for channel 1
6 V
CC
Power Supply voltage (3.3 V ± 5%)
7-8 B32, A32 Input, TMDS Port 3 differential inputs for channel 2
9 GND Power Ground
10-11 B33, A33 Input, TMDS Port 3 differential inputs for channel 3
12 V
13-14 B34, A34 Input, TMDS Port 3 differential inputs for channel 4
CC
Power Supply voltage (3.3 V ± 5%)
15 GND Power Ground
Doc ID 14911 Rev 4 9/44
Pin configuration STDVE103A
Table 2. Pin description (continued)
Pin number Pin name Type Function
Connect to GND through a 4.7 K ± 1% precision
16 R
17-18 Y4, Z4
19
20-21 Y3, Z3
22 GND Power Ground
23-24 Y2, Z2
25
26-27 Y1, Z1
28 GND Power Ground
29 SCL_SINK I/O Sink side DDC bus clock line
30 SDA_SINK I/O Sink side DDC bus data line
31 HPD_SINK Input
Analog
EXT
Output,
TMDS
V
CC
Power Supply voltage (3.3 V ± 5%)
Output,
TMDS
Output,
TMDS
V
CC
Power Supply voltage (3.3 V ± 5%)
Output,
TMDS
reference resistor. Sets the output current to
generate the output voltage compliant with TMDS
Channel 4 differential outputs
Channel 3 differential outputs
Channel 2 differential outputs
Channel 1 differential outputs
Sink side hot plug detector input
High: 5 V power signal asserted from source to
sink and EDID is ready
Low: No 5 V power signal is asserted from source
to sink or EDID is not ready
32-33 S1,S2 Input Source select inputs
34 NC No connect
35 HPD1 Output Port 1 hot plug detector output.
36
SDA1 I/O Port 1 DDC bus data line
37 SCL1 I/O Port 1 DDC bus clock line
38-39 B11, A11 Input, TMDS Port 1 differential inputs for channel 1
40
V
CC
Power Supply voltage (3.3 V ± 5%)
41-42 B12, A12 Input, TMDS Port 1 differential inputs for channel 2
43 GND Power Ground
44-45 B13, A13 Input, TMDS Port 1 differential inputs for channel 3
46 V
CC
Power Supply voltage (3.3 V ± 5%)
47-48 B14, A14 Input, TMDS Port 1 differential inputs for channel 4
49 V
Power
DD
Supply voltage (5.0 V ± 10%) for DDC, HPD and
source selector pins
50 HPD2 Output Port 2 hot plug detector output
51 SDA2 I/O Port 2 DDC bus data line
10/44 Doc ID 14911 Rev 4
STDVE103A Pin configuration
Table 2. Pin description (continued)
Pin number Pin name Type Function
52 SCL2 I/O Port 2 DDC bus clock line
53-54 B21, A21 Input, TMDS Port 2 differential inputs for channel 1
55 VCC Power Supply voltage (3.3 V ± 5%)
56-57 B22, A22 Input, TMDS Port 2 differential inputs for channel 2
58 GND Power Ground
59-60 B23, A23 Input, TMDS Port 2 differential inputs for channel 3
61
V
CC
62-63 B24, A24 Input, TMDS Port 2 differential inputs for channel 4
64 HPD3 Port 3 hot plug detector output.
Power Supply voltage (3.3 V ± 5%)
Doc ID 14911 Rev 4 11/44
Functional description STDVE103A
4 Functional description
The STDVE103A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standards such as the TMDS. The device
passes the differential inputs from a video source to a common display when it is in the
active mode of operation. The device conforms to the TMDS standard on both inputs and
outputs.
The low on-resistance and low I/O capacitance of the switch in STDVE103A result in a very
small propagation delay. The device integrates SPDT-type switches for 3 differential data
TMDS channels and 1 differential clock channel. Additionally, it integrates the switches for
DDC and HPD line switching with I
2
The I
C interface of the selected input port is linked to the I2C interface of the output port,
and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the
unused ports, the I
2
C interfaces are isolated and the HPD pins are driven to L state.
4.1 Adaptive equalizer
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation
from long or lossy transmission media. The inputs present high impedance when the device
is not active or when V
on input channels are present.
is absent or 0 V. In all other cases, the 50 Ω termination resistors
CC
2
C repeater on the DDC lines.
This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the
gain stage of the equalizer to compensate the signal degradation and then the signals are
driven on to the output ports.
The equalizer is fully adaptive and automatic in function providing smaller gain at low
frequencies and higher gain at high frequencies. The equalizer is optimized internally for an
adaptive operation.
Table 3. Gain frequency response
Frequency
(MHz)
225 3
325 5
410 6.5
825 11
1650 16
Gain in dB
12/44 Doc ID 14911 Rev 4
STDVE103A Functional description
Figure 6. STDVE103A gain vs. frequency
The STDVE103A equalizer is fully adaptive and automatic in function. The equalizer’s
performance is optimized for all frequencies over the cable lengths from 1 m to 25 m.
Input termination
The STDVE103A integrates precise 50 Ω ± 5% termination resistors, pulled up to VCC, on all
its differential input channels. External terminations are not required. This gives better
performance and also minimizes the PCB board space. These on-chip termination resistors
should match the differential characteristic impedance of the transmission line. Since the
output driver consists of current steering devices, an output voltage is not generated without
a termination resistor. Output voltage levels are dependent on the value of the total
termination resistance. The STDVE103A produces TMDS output levels for point-to-point
links that are doubly terminated (100
Ω at each end). With the typical 10 mA output current,
the STDVE103A produces an output voltage of 3.3 – 0.5 V = 2.8 V when driving a
termination line terminated at each end. The input terminations are selectable thus saving
power for the unselected ports.
Output buffers
Each differential output of the STDVE103A drives external 50 Ω load (pull-up resistor) and
conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential
current-steering devices.
The driver outputs are short-circuit current limited and are high-impedance to ground when
S1, S2 = HL or the device is not powered. The current steering architecture requires a
resistive load to terminate the signal to complete the transmission loop from V
through the termination resistor. Because the device switches the direction of the current
flow and not voltage levels, the output voltage swing is determined by V
minus the voltage
CC
drop across the termination resistor. The output current drivers are controlled by the S1, S2
pin and are turned off when S1, S2 is a HL. A stable 10 mA current is derived by accurate
internal current mirrors of a stable reference current which is generated by band-gap voltage
across the REXT. The differential output driver provides a typical 10 mA current sink
capability, which provides a typical 500 mV voltage drop across a 50
Ω termination resistor.
to GND
CC
Doc ID 14911 Rev 4 13/44
Functional description STDVE103A
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point
communication over a tightly controlled impedance medium. The TMDS standard uses a
lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing EMI emissions and system
susceptibility to noise. The device is capable of detecting differential signals as low as
100 mV within the entire common mode voltage range.
14/44 Doc ID 14911 Rev 4
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