Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer
Features
■ Compatible with the high-definition multimedia
interface (HDMI) v1.3 digital interface
■ Conforms to the transition minimized
differential signaling (TMDS) voltage standard
on input and output channels
■ 340 MHz maximum clock speed operation
supports all video formats with deep color at
maximum refresh rates
■ 3.4 Gbps data rate per channel
■ Fully automatic adaptive equalizer
■ Single supply V
■ ESD: >± 5 KV HBM for all TMDS I/Os
■ Integrated open-drain I
data channel (DDC)
■ 5.3 V tolerant DDC and HPD I/Os
■ Lock-up free operation of I
■ 0 to 400 kHz clock frequency for I
■ Low capacitance of all the channels
■ Equalizer regenerates the incoming attenu-
ated TMDS signal
■ Buffer drives the TMDS outputs over long PCB
track lengths
■ Low output skew and jitter
■ Tight input thresholds reduce bit error rates
■ On-chip selectable 50 Ω input termination
■ Low ground bounce
■ Data and control inputs provide undershoot
clamp diode
■ -40°C to 85°C operating temperature range
■ Evaluation kit is available
Table 1. Device summary
: 3.135 to 3.465 V
CC
2
C buffer for display
2
C bus
2
C bus
STDVE003A
TQFP80
Description
The STDVE003A integrates a 4-channel 3.4 Gbps
TMDS equalizer and a 3:1 switch to select one of
the three HDMI ports. The 3-input HDMI ports can
be either external ports or internal sources. Highspeed data paths and flow-through pinout
minimize the internal device jitter and simplify the
board layout. The equalizer overcomes the
intersymbol interference (ISI) jitter effects from
lossy cables. The buffer/driver on the output can
drive the TMDS output signals over long
distances. In addition to this, STDVE003A
integrates the 50 Ω termination resistor on all the
input channels to improve performance and
reduce board space. The device can be placed in
a low-power mode by disabling the output current
drivers. The STDVE003A is ideal for advanced TV
and STB applications supporting HDMI/DVI
standard. The differential signal from the
HDMI/DVI ports can be routed through the
STDVE003A to guarantee good signal quality at
the HDMI receiver. Designed for very low skew,
jitter and low I/O capacitance, the switch
preserves the signal integrity to pass the stringent
HDMI compliance requirements.
Order code Operating temperature Package Packaging
STDEV003ABTR -40°C to 85°C TQFP80 Tape and reel
December 2008 Rev 4 1/42
www.st.com
42
Contents STDVE003A
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 I2C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8 Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5 Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . 26
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.1 I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2/42
STDVE003A List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Gain frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. OE_N operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. DC specifications for TMDS differential ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. DC specifications for OE_N, EQ_BOOST, SEL (S1, S2, S3) inputs . . . . . . . . . . . . . . . . . 19
Table 13. Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14. External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 15. DDC I/O pins (switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 16. Status pins (Y_HPD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 17. Status pins (A_HPD, B_HPD, C_HPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 18. Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 19. Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 20. Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 21. Equalizer gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 22. Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 23. Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 24. Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 25. DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 26. Status pins (Y_HPD, A_HPD, B_HPD, C_HPD, SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 27. Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 28. I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 29. ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 30. TQFP80 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 31. Reel mechanical data (dimensions in mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 32. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3/42
List of figures STDVE003A
List of figures
Figure 1. STDVE003A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. DDC I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. STDVE003A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Pin configuration (TQFP80 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. STDVE003A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8. TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Test circuit for turn off and turn off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Test circuit for short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14. TSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 15. TSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16. TSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 21. TQFP80 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 22. TQFP80 tape information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 23. Reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4/42
STDVE003A Block diagram
1 Block diagram
Figure 1. STDVE003A block diagram
HDMI input
port A
HDMI input
port B
HDMI input
port C
DDC port A
DDC port B
DDC port C
S1,S2,S3
3:1
HDMI
input
select
switch
Input stage
2
2
2
Equalizer
DDC
switch
2
Output
driver/
transmitter
2
I C
repeater
HDMI output
port Y
DDC
port Y
HPD port A
HPD port B
HPD port C
HPD
analog
switch
Figure 2. Equalizer functional diagram (one signal pair)
S1, S2, S3
Data+
OE_N
REXT
Switch
(3:1)
Current control
Equalizer
Quantizer
Data-
50 Ω
termination
selectable
Pre-amp
Output
I
driver
Data+
Data-
HPD
port Y
CS00061
AM00715V1
5/42
Block diagram STDVE003A
Figure 3. DDC I2C bus repeater
2
I C bus repeater
A_DDC_SDA
B_DDC_SDA
C_DDC_SDA
A_DDC_SCL
B_DDC_SCL
C_DDC_SCL
S1, S2, S3
Switch
1.1 Application diagrams
Figure 4. STDVE003A in a digital TV
Game
console
Y_DDC_SDA
Y_DDC_SCL
CS00062
DVD -R STB
Digital TV
6/42
STDVE003A
HDMI receiver
CS00063
STDVE003A Pin configuration
2 Pin configuration
Figure 5. Pin configuration (TQFP80 package)
DDC_1_PWR
SDA1
SCL1
GND
B11
A11
VCC
B12
A12
GND
B13
A13
VCC
B14
A14
GND
VCC
REXT
EQ_BOOST
DDC_Y_PWR
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
HPD1
80
21
S1
VCC
79
22
S2
GND
78
23
S3
A24
B24
77
76
242526
Y4
GND
VCC
75
Z4
A23
B23
74
73
27
VCC
GND
A22
71
72
STDVE003A
30
28
29
Z3
Y3
GND
B22
70
SCL2
37
GND
SDA2
HPD2
62
63
39
38
SCL_SINK
SDA_SINK
VCC
60
61
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
HPD_SINK
DDC_2_PWR
GND
A34
B34
VCC
A33
B33
GND
A32
B32
VCC
A31
B31
GND
SCL3
SDA3
HPD3
VCC
OE_N
DDC_3_PWR
CS00064
GND
GND
A21
B21
VCC
65
67
64
66
69
68
31
32
34
33
Z2
Y2
VCC
36
35
Z1
Y1
GND
Table 2. Pin description
Pin number Pin name Type Function
1 DDC_1_PWR Power
External power to connect the pull-up resistor on
DDC A ports. Connect to GND if unused.
2, 3 SDA1, SCL1 I/O Port1 DDC bus data and clock lines
4 GND Power Ground
5, 6 B11, A11 Input,TMDS Port 1 differential inputs for channel 1
7
V
CC
Power Supply voltage (3.3 V ± 5%)
8, 9 B12, A12 Input,TMDS Port 1 differential inputs for channel 2
10 GND Power Ground
11, 12 B13, A13 Input,TMDS Port 1 differential inputs for channel 3
13
V
CC
Power Supply voltage (3.3 V ± 5%)
14, 15 B14, A14 Input, TMDS Port 1 differential inputs for channel 4
7/42
Pin configuration STDVE003A
Table 2. Pin description (continued)
Pin number Pin name Type Function
16 GND Power Ground
17
V
CC
Power Supply voltage (3.3 V ± 5%)
Connect to GND through a 4.7 KΩ ± 1% precision
18
R
EXT
Analog
reference resistor. Sets the output current to
generate the output voltage compliant with TMDS
19 EQ_BOOST Input
20 DDC_Y_PWR Power
Provides equalizer boost function. Set to L for
short cables and H for long cables.
External power to connect the pull-up resistor on
DDC Y ports. Connect to GND if unused.
21, 23 S1,S2,S3 Input Source select inputs
24 GND Power Ground
25, 26 Y4, Z4
27
V
CC
28, 29 Y3, Z3
Output,
TMDS
Channel 4 differential outputs
Power Supply voltage (3.3 V ± 5%)
Output,
TMDS
Channel 3 differential outputs
30 GND Power Ground
31, 32 Y2, Z2
33
V
CC
34, 35 Y1, Z1
Output,
TMDS
Channel 2 differential outputs
Power Supply voltage (3.3 V ± 5%)
Output,
TMDS
Channel 1 differential outputs
36 GND Power Ground
37 GND Power Ground
38 SCL_SINK I/O Sink side DDC bus clock line
39 SDA_SINK I/O Sink side DDC bus data line
40 HPD_SINK Input
41 DDC_3_PWR Power
42 OE_N Input Output enable, active low
43 VCC Power Supply voltage (3.3 V ± 5%)
44 HPD3 Output
45 SDA3 I/O Port 3 DDC bus data line
46 SCL3 I/O Port 3 DDC bus clock line
8/42
Sink side hot plug detector input
High: 5 V power signal asserted from source to
sink and EDID is ready.
Low: No 5 V power signal is asserted from source
to sink or EDID is not ready.
External power to connect the pull-up resistor on
DDC C ports. Connect to GND if unused.
Port 3 hot plug detector output. Open drain output.
Connect an external resistor according to the
HDMI specification.
STDVE003A Pin configuration
Table 2. Pin description (continued)
Pin number Pin name Type Function
47 GND Power Ground
48, 49 B31, A31 Input, TMDS Port 3 differential inputs for channel 1
50 V
CC
51, 52 B32, A32 Input, TMDS Port 3 differential inputs for channel 2
53 GND Power Ground
54, 55 B33, A33 Input, TMDS Port 3 differential inputs for channel 3
56
V
CC
57, 58 B34, A34 Input, TMDS Port 3 differential inputs for channel 4
59 GND Power Ground
60 DDC_2_PWR Power
61
V
CC
62 HPD2 Output
Power Supply voltage (3.3 V ± 5%)
Power Supply voltage (3.3 V ± 5%)
External power to connect the pull-up resistor on
DDC B ports. Connect to GND if unused.
Power Supply voltage (3.3 V ± 5%)
Port 2 hot plug detector output. Open drain output.
Connect an external resistor according to the
HDMI specification.
63 SDA2 I/O Port 2 DDC bus data line
64 SCL2 I/O Port 2 DDC bus clock line
65 GND Power Ground
66 GND Power Ground
67, 68 B21, A21 Input, TMDS Port 2 differential inputs for channel 1
69
V
CC
Power Supply voltage (3.3 V ± 5%)
70, 71 B22, A22 Input, TMDS Port 2 differential inputs for channel 2
72 GND Power Ground
73, 74 B23, A23 Input, TMDS Port 2 differential inputs for channel 3
75
V
CC
Power Supply voltage (3.3 V ± 5%)
76, 77 B24, A24 Input, TMDS Port 2 differential inputs for channel 4
78 GND Power Ground
79
V
CC
Power Supply voltage (3.3 V ± 5%)
Port 1 hot plug detector output. Open drain output.
80 HPD1
Connect an external resistor according to the
HDMI specification.
9/42
Functional description STDVE003A
3 Functional description
The STDVE003A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standard like TMDS. The device passes the
differential inputs from a video source to a common display when it is in the active mode of
operation. The device conforms to the TMDS standard on both inputs and outputs.
The low on-resistance and low I/O capacitance of the switch in STDVE003A result in a very
small propagation delay. The device integrates SPDT-type switches for 3 differential data
TMDS channels and 1 differential clock channel. Additionally, it integrates the switches for
DDC and HPD line switching with I
2
The I
C interface of the selected input port is linked to the I2C interface of the output port,
and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the
unused ports, the I
2
C interfaces are isolated and the HPD pins are driven to L state.
3.1 Adaptive equalizer
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation
from long or lossy transmission media. The inputs present high impedance when the device
is not active or when V
on input channels are present.
is absent or 0 V. In all other cases, the 50 Ω termination resistors
CC
2
C repeater on the DDC lines.
This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the
gain stage of the equalizer to compensate the signal degradation and then the signals are
driven on to the output ports.
The equalizer is fully adaptive and automatic in function providing smaller gain at low
frequencies and higher gain at high frequencies. The default setting of EQ_BOOST = L is
recommended for optimized operation.
Table 3. Gain frequency response
Frequency
(MHz)
225 3 6.5
325 5 8.5
410 6.5 11
825 11 16
1650 16 21.5
Gain in dB
(EQ_BOOST = 0)
Gain in dB
(EQ_BOOST = 1)
10/42
STDVE003A Functional description
Figure 6. STDVE003A gain vs. frequency
The STDVE003A equalizer is fully adaptive and automatic in function. The default setting of
EQ_BOOST = L is recommended for optimal operation. The equalizer’s performance is
optimized for all frequencies over the cable lengths from 1 m to 25 m at EQ_BOOST = L.
If cable lengths greater than 25 m are desired in application, then EQ_BOOST = H setting is
recommended.
Input termination
The STDVE003A integrates precise 50 Ω ± 5% termination resistors, pulled up to VCC, on all
its differential input channels. External terminations are not required. This gives better
performance and also minimizes the PCB board space. These on-chip termination resistors
should match the differential characteristic impedance of the transmission line. Since the
output driver consists of current steering devices, an output voltage is not generated without
a termination resistor. Output voltage levels are dependent on the value of the total
termination resistance. The STDVE003A produces TMDS output levels for point-to-point
links that are doubly terminated (100
Ω at each end). With the typical 10 mA output current,
the STDVE003A produces an output voltage of 3.3 – 0.5 V = 2.8 V when driving a
termination line terminated at each end. The input terminations are selectable thus saving
power for the unselected ports.
Output buffers
Each differential output of the STDVE003A drives external 50 Ω load (pull-up resistor) and
conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential
current-steering devices.
The driver outputs are short-circuit current limited and are high-impedance to ground when
OE_N = H or the device is not powered. The current steering architecture requires a
resistive load to terminate the signal to complete the transmission loop from V
through the termination resistor. Because the device switches the direction of the current
flow and not voltage levels, the output voltage swing is determined by V
minus the voltage
CC
drop across the termination resistor. The output current drivers are controlled by the OE_N
pin and are turned off when OE_N is a high. A stable 10 mA current is derived by accurate
internal current mirrors of a stable reference current which is generated by band-gap voltage
to GND
CC
11/42
Functional description STDVE003A
across the REXT. The differential output driver provides a typical 10 mA current sink
capability, which provides a typical 500 mV voltage drop across a 50
Ω termination resistor.
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point
communication over a tightly controlled impedance medium. The TMDS standard uses a
lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing EMI emissions and system
susceptibility to noise. The device is capable of detecting differential signals as low as
100 mV within the entire common mode voltage range.
3.2 Operating modes
Table 4. OE_N operating modes
Input Output
OE_N
(ports A1, A2 or A3)
LH LHLActive mode
LL HLHActive mode
H X X Hi-Z Hi-Z Low power mode
IN+
(ports B1, B2 or B3)
IN-
OUT+ OUT-
Function
The OE_N input activates a hardware power down mode. When the power down mode is
active (OE_N = H), all input and output buffers and internal bias circuitry are powered-off
and disabled.
Outputs are tri-stated in power-down mode. When exiting power-down mode, there is a
delay associated with turning on band-references and input/output buffer circuits.
12/42
STDVE003A Functional description
3.2.1 SEL operating modes
The active source is selected by configuring source select inputs, S1, S2 and S3. The
selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I
interface of the selected input port is linked to the I
hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused
ports, the I
2
C interfaces are isolated, and the HPD pins are kept low.
2
C interface of the output port, and the
2
C
Table 5. SEL operating modes
Control pins I/O selected Hot-plug detect status
S1 S2 S3 Y/Z
HXXA1/B1
LHXA2/B2
LLHA3/B3
LLL
H: logic high; L: logic low; X: don't care; Z: high impedance
None
(Z)
SCL_SINK
SDA_SINK
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3
None (Z) L L L
HPD1 HPD2 HPD3
HPD_SINK L L
LHPD_SINKL
L L HPD_SINK
3.3 HPD pins
The input pin HPD_SINK is 5 V tolerant, allowing direct connection to 5 V signals. The
switch is able to pass both 0 V and 5 V signal levels. The HPD_SINK is an input pin while
the A_HPD, B_HPD and C_HPD are open-drain outputs.
3.4 DDC channels
The DDC channels are designed with a bidirectional NMOS gate, providing 5 V signal
tolerance. The 5 V tolerance allows direct connection to a standard I
the need for a level shifter. There should be external pull-up resistors on either side of the
device on both the SCL and SDA lines.
2
C bus, thus eliminating
13/42
Functional description STDVE003A
3.5 I2C DDC line repeater
The device contains two identical bidirectional open-drain, non-inverting buffer circuits that
enable I
2
C DDC bus lines to be extended without degradation in system performance. The
STDVE003A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I2C
bus, while retaining all the operating modes and features of the I
two buses of 400 pF bus capacitance to be connected in an I
2
C system. This enables
2
C application. These buffers
are operational from a supply V of 3.0 V to 3.6 V.
2
The I
C bus capacitance limit of 400 pF restricts the number of devices and bus length. The
STDVE003A enables the system designer to isolate the two halves of a bus,
accommodating more I
2
C devices or longer trace lengths. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz
bus is isolated when 400 kHz operation of the other bus is required. The STDVE003A can
be used to run the I
2
C bus at both 5 V and 3.3 V interface levels.
The S1, S2 and S3 (SEL) lines act as control signals for the corresponding A, B or C ports.
Note that the SEL line has an internal pull-down resistor. The SEL line should not change
state during an I
enabling part way through a bus cycle could confuse the I
2
C operation, because disabling during bus operation hangs the bus and
2
C parts being enabled. The SEL
input should change state only when the global bus and the repeater port are in idle state, to
prevent system failures.
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage
of each internal buffer must be 70 mV or more below the output low level, when the output
internally is driven low. This prevents a lock-up condition from occurring when the input low
condition is released.
As with the standard I
2
C system, pull up resistors are required to provide the logic high
levels on the buffered bus. The STDVE003A has standard open collector configuration of
2
the I
C bus. The size of the pull up resistors depends on the system, but each side of the
repeater must have a pull up resistor.
This part is designed to work with standard mode and fast mode I
mode I
in a generic I
2
C devices only specify 3 mA output drive, this limits the termination current to 3 mA
2
C system where standard mode devices and multiple masters are possible.
2
C devices. Standard
Under certain conditions, higher termination currents can be used.
3.6 Power-down condition
The OE_N is used to disable most of the internal circuitry of STDVE003A that puts the
device in a low power mode of operation.
3.7 Bias
The bandgap reference voltage over the external R
bias reference current. This current and its factors (achieved by employing highly accurate
and well matched current mirror circuit topologies) are generated on-chip and used by
several internal modules. The 10 mA current used by the transmitter block is also generated
using this reference current. It is important to ensure that the R
tolerance range of its typical value.
14/42
reference resistor sets the internal
EXT
value is within the ±1%
EXT
STDVE003A Functional description
Table 6. Bias parameter
Parameter Min Typ Max Unit
Bandgap voltage
- 1.2 - V
The output voltage swing depends on 3 components: supply voltage (V
resistor (R
termination resistor can vary from 50
) and current drive (I
T
). The supply voltage can vary from 3.3 V ±5%,
drive
Ω ±10%.
The voltage on the output is given by:
− I
V
supply
The variation on I
drive
x RT.
drive
must be controlled to ensure that the voltage on HDMI output is within
the HDMI specification under all conditions.
This is achieved when:
400 mV
≤ I
x RT ≤ 600 mV with typical value centered at 500 mV.
drive
3.8 Timing between HPD and DDC
It is important to ensure that the I2C DDC interface is ready by the time the HPD detection is
complete.
As soon as the discovery is finished by the HPD detection, the configuration data is
exchanged between a source and sink through the I
DDC interface is ready for communication as soon as the power supply to the chip is
present and stable. When the desired port is enabled and the chip is out of shutdown mode,
2
the I
C DDC lines can be used for communication.
, termination
supply)
2
C DDC interface. The STDVE003 Afs
Thus, as soon as the HPD detection sequence is complete, the DDC interface can be
readily used. There is no delay between the HPD detection and I
2
C DDC interface to be
ready.
15/42
Maximum rating STDVE003A
4 Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 7. Absolute maximum ratings
Symbol Parameter Value Unit
V
Supply voltage to ground -0.5 to +4.0 V
CC
DC input voltage (TMDS ports) 1.7 to +4.0 V
SEL (S1, S2, S3), OE_N -0.5 to +4.0 V
V
I
A_DDC_SDA, A_DDC_SCL, B_DDC_SDA, B_DDC_SCL,
T
C_DDC_SDA, C_DDC_SCL,Y_DDC_SDA, Y_DDC_SCL,
Y_HPD, A_HPD, B_HPD, C_HPD
I
DC output current 120 mA
O
Storage temperature -65 to +150 °C
STG
T
Lead temperature (10 sec) 300 °C
L
-0.5 to +6.0 V
Table 8. Thermal data
Symbol Parameter TQFP80 Unit
Θ
Thermal coefficient (junction-ambient) 48 °C/W
JA
16/42
STDVE003A Maximum rating
4.1 Recommended operating conditions
4.2 DC electrical characteristics
TA = -40 to +85 °C, VCC = 3.3 V ± 5%
Table 9. Power supply characteristics
Symbol Parameter Test condition
(a)
Val ue
Min Typ Max
Unit
V
CC
Supply voltage 3.135 3.3 3.465 V
All inputs/outputs
are enabled.
Inputs are
I
CC
Supply current
terminated with
50 Ω to VCC.
= 3.465 V
V
CC
Data rate =
3.4 Gbps
Table 10. DC specifications for TMDS differential inputs
Symbol Parameter Test condition
Min Typ Max
= 3.465 V
Differential input high
V
TH
threshold
(peak-to-peak)
V
TL
Differential input low
threshold
V
CC
over the entire
V
CMR
V
= 3.465 V
CC
over the entire
V
CMR
-150 0 mV
Differential input
V
ID
voltage
(peak-to-peak)
(1)
VCC = 3.465 V 150 1560 mV
280 mA
Val ue
Unit
0150mV
V
CMR
Common mode
voltage range
IN+ or IN- to
C
IN
Input capacitance
GND
F = 1 MHz
1. Differential output voltage is defined as | (OUT+ - OUT-) |.
Differential input voltage is defined as | (IN+ - IN-) |.
a. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
- 0.3 VCC - 0.04 V
V
CC
3.5 pF
17/42
Maximum rating STDVE003A
Table 11. DC specifications for TMDS differential ouputs
Value
Symbol Parameter Test condition
Min Typ Max
Unit
V
V
V
|I
OH
V
OL
swing
OD
I
OL
SC
Single-ended high level
output voltage
Single-ended low level
output voltage
Single ended output
swing voltage
Differential output
voltage
(peak-to-peak)
Differential output low
level current
Output driver short-
|
circuit current
(continuous)
(1)
= 3.3 V
V
CC
R
= 50 Ω
TERM
VCC = 3.3 V
R
= 50 Ω
TERM
OUT± = GND
through a 50 Ω
resistor.
See Figure 11
-10 VCC+10 mV
V
CC
V
-600 VCC-400 mV
CC
400 500 600 mV
800 1000 1200 mV
81012mA
12 mA
OUT+ or OUT-
C
OUT
Output capacitance
to GND when tristate
5.5 pF
F = 1 MHz
1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |
18/42
STDVE003A Maximum rating
Table 12. DC specifications for OE_N, EQ_BOOST, SEL (S1, S2, S3) inputs
Val ue
Symbol Parameter Test condition
Min Typ Max
V
IH
V
IL
V
IK
I
IH
I
IL
C
IN
Table 13. Input termination resistor
HIGH level input voltage
LOW level input voltage
Clamp diode voltage
Input high current
Input low current
Input capacitance
High level
guaranteed
Low level
guaranteed
V
= 3.465 V
CC
= -18 mA
I
IN
= 3.465 V
V
CC
V
= V
IN
CC
V
= 3.465 V
CC
V
= GND
IN
Pin to GND
F = 1 MHz
2.0 V
-0.5 0.8 V
-1.2 -0.8 V
-5 +5 µA
-5 +5 µA
3.5 pF
Symbol Parameter Test condition Value Unit
Differential input
R
TERM
termination resistor on
IN± channels relative to
V
CC
IIN = -10mA 455055Ω
Unit
Table 14. External reference resistor
Symbol Parameter Test condition
R
EXT
Resistor for TMDS
compliant voltage swing
range
Tolerance for
R = ±1%
Table 15. DDC I/O pins (switch)
Symbol Parameter Test condition
V
I(DDC)
Input voltage GND 5.3 V
Val ue
Unit
Min Typ Max
4.7 KΩ
Val ue
Unit
Min Typ Max
19/42
Maximum rating STDVE003A
Table 15. DDC I/O pins (switch)
Val ue
Symbol Parameter Test condition
VCC = 3.465 V
A, B, C ports = 5.3 V
Y port = 0.0 V
Switch is isolated
I
I(leak)
Input leakage current
= 3.465 V
V
CC
A, B, C ports = 3.3 V
Y port = 0.0 V
Switch is isolated
=0 V
V
I
F = 1 MHz
Switch disabled
C
I/O
Input/output capacitance
VI=0 V
F = 1 MHz
Switch enabled
Min Typ Max
6µA
2µA
5pF
9pF
Unit
20/42
STDVE003A Maximum rating
Table 16. Status pins (Y_HPD)
Val ue
Symbol Parameter Test condition
Min Typ Max
Unit
V
V
High level input voltage
IH
Low level input voltage
IL
VCC = 3.3 V
High level guaranteed
VCC = 3.3 V
Low level guaranteed
V
= 3.465 V
CC
2.0 5.3 V
GND 0.8 V
Y = 5.3 V
I
I(leak)
Input leakage current
V
= 3.465 V
CC
Y = 3.3 V
Table 17. Status pins (A_HPD, B_HPD, C_HPD)
(1)
Val ue
Symbol Parameter Test condition
Min Typ Max
V Voltage GND 5.3 V
=0V
V
I
F = 1 MHz
5pF
Switch disabled
C
Input/output capacitance
I/O
VI=0V
F = 1 MHz
9pF
Switch enabled
4µA
2µA
Unit
= 3.3 V
V
1. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
Output low voltage
OL
(open drain I/Os)
V
CC
IOL=8mA
0.4 V
21/42
Maximum rating STDVE003A
4.3 DC electrical characteristics (I2C repeater)
(TA = -40 to +85 °C, VCC = 3.3 V ± 5%, GND = 0 V; unless otherwise specified)
Table 18. Supplies
Symbol Parameter Test condition
Val ue
Unit
Min Typ Max
V
CC
Table 19. Input/output SDA, SCL
DC supply voltage 3.135 3.3 3.465 V
Symbol Parameter Test condition
Min Typ Max
V
IH
V
IL
V
ILc
V
IK
I
IL
I
IH
V
OL
I
OH
C
1. VIL specification is for the first low level seen by the SDA/SCL lines. V
by the SDA/SCL lines.
2. The SCL/SDA C
secured to the repeater but an active bus remains on either set of the SDA/SCL pins.
High level input
voltage
Low level input
(1)
voltage
Low level input voltage
contention
(1)
0.7 V
CC
-0.5 0.3 V
-0.5 0.4 V
Input clamp voltage II = -18 mA −−-1.2 V
Input current low
(SDA, SCL)
Input current high
(SDA, SCL)
LOW-level output
voltage
Output high level
leakage current
Input capacitance VI = 3V or 0V − 67
I
is about 200 pF when VCC= 0 V. The STDVE003A should be used in applications where power is
I
Input current low
(SDA, SCL)
= 3.465 V
V
I
(SDA, SCL)
VI = 5.3 V
(SDA, SCL)
= 3 mA 0.4 V
I
OL
= 6 mA 0.65 V
I
OL
= 3.6 V;
V
O
driver disabled
VO = 5.3 V;
driver disabled
−−1 μA
−−10 μA
−−10 μA
−−10 μA
−−10 μA
is for the second and subsequent low levels seen
ILc
Val ue
Unit
5.3 V
CC
(2)
V
pF
22/42
STDVE003A Maximum rating
4.4 Dynamic switching characteristics
TA = -40 to +85 °C, VCC = 3.3 V ± 5%, R
Typical values are at T
f
CK
rate
Clock frequency
(1/10th of the
differential data rate)
Signaling rate 3.4 Gbps
Table 20. Clock and data rate
Symbol Parameter Test condition
D
Table 21. Equalizer gain
Symbol Parameter Test condition
G_EQ Equalizer gain
= +25 °C and VCC = 3.3 V.
A
At all frequencies
(EQ_BOOST = L) for short
cables
At all frequencies
(EQ_BOOST = H) for long
cables
= 50 Ω ± 5%, CL = 5 pF).
TERM
(b)
Val ue
Unit
Min Typ Max
25 340 MHz
Val ue
Unit
Min Typ Max
15 dB
20 dB
Table 22. Differential output timings
Val ue
Symbol Parameter Test condition
Unit
Min Typ Max
t
r
Differential data and
20% to 80% of V
OD
75 150 240 ps
clock output rise/fall
t
t
t
f
PLH
PHL
times
Differential low to high
propagation delay
Differential high to low
propagation delay
80% to 20% of V
OD
Alternating 1 and 0 pattern
at slow and fast data rates
Measure at 50% V
OD
between input to output
75 150 240 ps
250 800 ps
250 800 ps
b. The timing values in this section are tested during characterization and are guaranteed by
design and simulation. Not tested in production.
23/42
Maximum rating STDVE003A
Table 23. Skew times
Symbol Parameter Test condition
t
SK(O)
t
SK(P)
t
SK(D)
Inter-pair channel-tochannel output skew
Pulse skew | t
Intra-pair differential
skew
PLH
- t
PHL
Difference in
propagation
t
SK(CC)
Output channel to
channel skew
delay
(t
PLH
or t
among all output
channels
Table 24. Turn-on and turn-off times
Symbol Parameter Test condition
Time from
t
ON
TMDS output enable
time
OE_N to OUT±
change from tristate to active
Time from
OE_N to OUT±
change from
active to tri-
t
OFF
TMDS output disable
time
state
Val ue
Unit
Min Typ Max
100 ps
|2580ps
44 ps
PHL
)
50 125 ps
Val ue
Unit
Min Typ Max
12 20 ns
610 ns
Table 25. DDC I/O pins
Symbol Parameter Test condition
Min Typ Max
Refer to Section 4.5
Table 26. Status pins (Y_HPD, A_HPD, B_HPD, C_HPD, SEL)
Symbol Parameter Test condition
Min Typ Max
t
PD(HPD)
Propagation delay
(from Y_HPD to the
active port of HPD)
= 10 pF,
C
L
RPU=1KΩ
Switch time
T
ON/OFF
(from port select to the
latest valid status of
= 10 pF 50 ns
C
L
HPD)
24/42
Val ue
Unit
Val ue
Unit
150 ns
STDVE003A Maximum rating
Table 27. Jitter
Val ue
Symbol Parameter Test condition
Min Typ Max
Unit
t
JIT
Total jitter
(1)
PRBS pattern
at 1.6 Gbps
35 ps (p-p)
(800 MHz)
1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been
subtracted. Input differential voltage = V
parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis.
= 500 mV, PRBS random pattern at 1.65 Gbps, tr=tf=50 ps (20% to 80%). Jitter
ID
25/42
Maximum rating STDVE003A
4.5 Dynamic switching characteristics (I2C repeater)
TA = -40 to +85 °C, VCC = 3.3 V ± 5%.
Typical values are at T
Table 28. I2C repeater
(1)
= +25 °C and VCC = 3.3 V.
A
Symbol Parameter Test condition
Standard mode 100 kHz
f
SCL
I2C clock frequency
Fast mode 400 kHz
100 KHz
See Figure 19
Voltage on line = 5V
Cmax=400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions.
t
LOW
Low duration on SCL pin
400 KHz
See Figure 19
Voltage on line = 5V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions.
Val ue
Unit
Min Typ Max
4.7 μs
1.3 μs
t
LOW
Low duration on SCL pin
100 KHz
See Figure 19
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions.
400 KHz
See Figure 19
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions.
4.7 μs
1.3 μs
26/42
STDVE003A Maximum rating
Table 28. I2C repeater
(1)
(continued)
Symbol Parameter Test condition
100 KHz
See Figure 19
Voltage on line = 5V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions
t
HIGH
High duration on SCL pin
400 KHz
See Figure 19
Voltage on line = 5 V
Cmax = 400 pF, Rmax=2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions
100 KHz
Refer section 14.12,
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions
t
HIGH
High duration on SCL pin
400 KHz
See Figure 19
Voltage on line = 3.3 V,
Cmax=400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20% time intervals
on both transitions
Value
Unit
Min Typ Max
4.0 μs
0.6 μs
4.0 μs
0.6 μs
27/42
Maximum rating STDVE003A
Table 28. I2C repeater
(1)
(continued)
Symbol Parameter Test condition
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
t
PHL
Propagation delay
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
Output fall time
t
f
400 KHz
Waveform 1
(2)
Voltage on line = 3.3 V
Cmax = 400pF, Rmax = 2 K
Value
Unit
Min Typ Max
250 μs
300 μs
250 ns
450 ns
250 ns
300 ns
250 ns
450 ns
(2)
300 ns
300 ns
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STDVE003A Maximum rating
Table 28. I2C repeater
(1)
(continued)
Value
Symbol Parameter Test condition
Min Typ Max
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V
(2)
300 ns
Cmax = 400 pF, Rmax = 2 K
Output fall time
t
f
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V
(2)
300 ns
Cmax = 400 pF, Rmax = 2 K
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 5 V
(2)
300 ns
Cmax = 400 pF, Rmax = 2 K
t
r
Output rise time
400 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V
(2)
300 ns
Cmax = 400 pF, Rmax = 2 K
100 KHz
Waveform 1
Voltage on line = 5 V
(2)
1000 ns
Cmax = 400 pF, Rmax = 2 K
t
r
Output rise time
100 KHz
Waveform 1 (Figure 17)
Voltage on line = 3.3 V
(2)
1000 ns
Cmax = 400 pF, Rmax = 2 K
1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in
production.
2. The t
transition time is specified with maximum load of 2 kΩ pull-up resistance and 400 pF load capacitance. Different load
r
resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
Refer to Figure 9.
Unit
Table 29. ESD performance
Symbol Parameter Test conditions Min Typ Max Unit
TMDS I/Os Human body model ±5 kV
ESD
Other I/Os Human body model ±2 kV
29/42
Maximum rating STDVE003A
Figure 7. Test circuit for electrical characteristics
V
CC
C
L
V
V
IN+
Pulse
generator
R
T
R
T
V
IN-
1. CL= load capacitance: include jig and probe capacitance.
= termination resistance; should be equal to Z
2. R
T
of the pulse generator.
OUT
STDVE003A
OUT+
100 Ω
V
OUT-
C
L
CS00065
Figure 8. TMDS output driver
R
ZO = R
T
TMDS
driver
1. ZO = characteristic impedance of the cable.
= termination resistance: should be equal to ZO of the cable. Both are equal to 50W.
2. R
T
ZO = R
T
V
CC
T
R
T
TMDS
receiver
CS00069
30/42
STDVE003A Maximum rating
Figure 9. Test circuit for HDMI receiver and driver
VCC
V
A
VB
1. RT = 50 Ω.
RT
A
VID
B
VID = VA - VB
RT
TMDS
receiver
TMDS
driver
VSwing = VY - VZ
Y
CL =
0.5pF
Z
VZ
VY
RT
RT
V
CC
CS00071
31/42
Maximum rating STDVE003A
Figure 10. Test circuit for turn off and turn off times
0.01
10µF 0.1 µF
µF
1.15 V
1.0 V
1.15 V
1.0 V
Pulse
generator
50 Ω
4.7 KΩ
VIN+
VIN-
SHDN_N
REXT
±1%
V
CC
STDVE003A
GND
1. CL = 5 pF
Figure 11. Test circuit for short circuit output current
50 Ω
CL
50 Ω
1.2 V
50 Ω
CL
CS00072
TMDS
driver
32/42
50 Ω
0V or 3.465 V
I
SC
STDVE003A Maximum rating
Figure 12. Propagation delays
VA
ID
ID(p-p)
V
80%
tr tf
VB
V
Output
VCM V
ID
tpLH
20% 20%
Figure 13. Turn-on and turn-off times
VCC
VCM
VCC – 0.4
0.4V
VID
0V
-0.4V
V
OD(O)
OD(p-p)
V
tpHL
80%
V
OD(U)
100%
0V Differential
0%
SHDN_N
V
OUT+
when VID= +150mV
OUT-
when VID= -150mV
V
OUT+
when VID= -150mV
V
OUT-
when VID= +150mV
V
1.50 V
OFF
t
OFF
t
50%
50%
1.50 V
3.0 V
t
ON
0 V
V
OH
50%
1.2 V
t
ON
1.2 V
50%
OL
V
33/42
Maximum rating STDVE003A
Figure 14. TSK(O)
3.5V
2.5V
Data In
Data Out at Port 0
Data Out at Port 1
Figure 15. TSK(P)
tpLHX tpHLX
2.5V
tpLHY
tSK(o) = | tpLHy – tpLHx | or | tpHLy – tpHLx |
tpHLY
tSK(o)
1.5V
V
2.5V
V
V
2.5V
V
OH
OL
OH
OL
Figure 16. TSK(D)
34/42
STDVE003A Maximum rating
Figure 17. AC waveform 1 (I2C lines)
Figure 18. Test circuit for AC measurements (I
2
Figure 19. I
C bus timing
2
C lines)
35/42
Application information STDVE003A
5 Application information
5.1 Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to
always apply V
5.2 Power supply requirements
before applying any signals to the input/output or control pins.
CC
Bypass each of the V
pins with 0.1 μF and 1 nF capacitors in parallel as close to the
CC
device as possible, with the smaller-valued capacitor as close to the V
possible.
All V
from each V
pins can be tied to a single 3.3 V power source. A 0.01 μF capacitor is connected
CC
pin directly to ground to filter supply noise. The maximum power supply
CC
variation can only be ±5% as per the HDMI specifications.
The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit.
5.3 Differential traces
The high-speed TMDS inputs are the most critical parts for the device. There are several
considerations to minimize discontinuities on these transmission lines between the
connectors and the device.
(a) Maintain 100-Ω differential transmission line impedance into and out of the STDVE003A.
(b) Keep an uninterrupted ground plane below the high-speed I/Os.
(c) Keep the ground-path vias to the device as close as possible to allow the shortest return
current path.
(d) Layout of the TMDS differential inputs should be with the shortest stubs from the
connectors.
Output trace characteristics affect the performance of the STDVE003A. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.
pin of the device as
CC
36/42
STDVE003A Application information
5.3.1 I2C lines application information
A typical application is shown in the figure below. In the example, the system master is
running on a 3.3 V I
2
C-bus while the slave is connected to a 5 V bus. Both buses run at
100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz.
Master devices can be placed on either bus.
Figure 20. Typical application of I
2
C bus system
The STDVE003A DDC lines are 5 V tolerant; so it does not require any extra circuitry to
translate between the different bus voltages.
37/42
Package mechanical data STDVE003A
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 21.
TQFP80 package outline
38/42
STDVE003A Package mechanical data
Table 30. TQFP80 mechanical data
Millimeters
Symbol
Min Typ Max
A 1.200
A1 0.050 0.150
A2 0.950 1.000 1.050
b 0.170 0.220 0.270
c 0.090 0.200
D14.000
D1 12.000
D2 9.500
e 0.500
E14.000
E1 12.000
E2 9.500
L 0.450 0.600 0.750
L1 1.000
k0
ccc 0.080
° 7°
Figure 22. TQFP80 tape information
39/42
Package mechanical data STDVE003A
Figure 23. Reel information
Table 31. Reel mechanical data (dimensions in mm)
ACNT
330.2 13
±0.25 178 24.4
0084694_J
40/42
STDVE003A Revision history
7 Revision history
Table 32. Document revision history
Date Revision Changes
23-Apr-2008 1 Initial release.
26-May-2008 2 Minor updates: Ta b le 4 ,Ta bl e 7, Ta b l e 2 3 and Tab le 2 9 .
Added: Fully automatic adaptive equalizer feature
21-Jul-2008 3
01-Dec-2008 4
Modified: title, features Chapter 3.1 and Figure 2
Removed: Table 21.: Equalizer gain
Updated ESD information in the Features section and Table 29: ESD
performance on page 29.
Modified Section 3.6: Power-down condition on page 14 and Ta bl e 7 :
Absolute maximum ratings on page 16.
41/42
STDVE003A
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