ST STDVE003A User Manual

Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer

Features

■ Compatible with the high-definition multimedia

interface (HDMI) v1.3 digital interface

■ Conforms to the transition minimized

differential signaling (TMDS) voltage standard
on input and output channels

■ 340 MHz maximum clock speed operation

supports all video formats with deep color at
maximum refresh rates

■ 3.4 Gbps data rate per channel

■ Fully automatic adaptive equalizer

■ Single supply V

■ ESD: >± 5 KV HBM for all TMDS I/Os

■ Integrated open-drain I

data channel (DDC)

■ 5.3 V tolerant DDC and HPD I/Os

■ Lock-up free operation of I

■ 0 to 400 kHz clock frequency for I

■ Low capacitance of all the channels

■ Equalizer regenerates the incoming attenu-

ated TMDS signal

■ Buffer drives the TMDS outputs over long PCB

track lengths

■ Low output skew and jitter

■ Tight input thresholds reduce bit error rates

■ On-chip selectable 50 Ω input termination

■ Low ground bounce

■ Data and control inputs provide undershoot

clamp diode

■ -40°C to 85°C operating temperature range

■ Evaluation kit is available

Table 1. Device summary

: 3.135 to 3.465 V

CC

2

C buffer for display

2

C bus

2

C bus

STDVE003A

TQFP80

Description

The STDVE003A integrates a 4-channel 3.4 Gbps
TMDS equalizer and a 3:1 switch to select one of
the three HDMI ports. The 3-input HDMI ports can
be either external ports or internal sources. High­speed data paths and flow-through pinout
minimize the internal device jitter and simplify the
board layout. The equalizer overcomes the
intersymbol interference (ISI) jitter effects from
lossy cables. The buffer/driver on the output can
drive the TMDS output signals over long
distances. In addition to this, STDVE003A
integrates the 50 Ω termination resistor on all the
input channels to improve performance and
reduce board space. The device can be placed in
a low-power mode by disabling the output current
drivers. The STDVE003A is ideal for advanced TV
and STB applications supporting HDMI/DVI
standard. The differential signal from the
HDMI/DVI ports can be routed through the
STDVE003A to guarantee good signal quality at
the HDMI receiver. Designed for very low skew,
jitter and low I/O capacitance, the switch
preserves the signal integrity to pass the stringent
HDMI compliance requirements.

Order code Operating temperature Package Packaging

STDEV003ABTR -40°C to 85°C TQFP80 Tape and reel

December 2008 Rev 4 1/42

www.st.com

42

Contents STDVE003A

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2.1 SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5 I2C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6 Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.7 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.8 Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5 Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . 26

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2 Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.1 I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2/42

STDVE003A List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Gain frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. OE_N operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 11. DC specifications for TMDS differential ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12. DC specifications for OE_N, EQ_BOOST, SEL (S1, S2, S3) inputs . . . . . . . . . . . . . . . . . 19

Table 13. Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 14. External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 15. DDC I/O pins (switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 16. Status pins (Y_HPD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 17. Status pins (A_HPD, B_HPD, C_HPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 18. Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 19. Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 20. Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 21. Equalizer gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 22. Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 23. Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 24. Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 25. DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 26. Status pins (Y_HPD, A_HPD, B_HPD, C_HPD, SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 27. Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 28. I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 29. ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 30. TQFP80 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 31. Reel mechanical data (dimensions in mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 32. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3/42

List of figures STDVE003A

List of figures

Figure 1. STDVE003A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. DDC I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. STDVE003A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Pin configuration (TQFP80 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. STDVE003A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 8. TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 9. Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10. Test circuit for turn off and turn off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 11. Test circuit for short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 13. Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 14. TSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 15. TSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16. TSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17. AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18. Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 19. I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 20. Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 21. TQFP80 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 22. TQFP80 tape information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 23. Reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4/42

STDVE003A Block diagram

1 Block diagram

Figure 1. STDVE003A block diagram

HDMI input

port A

HDMI input

port B

HDMI input

port C

DDC port A

DDC port B

DDC port C

S1,S2,S3

3:1

HDMI

input

select
switch

Input stage

2

2

2

Equalizer

DDC

switch

2

Output

driver/

transmitter

2

I C

repeater

HDMI output
port Y

DDC

port Y

HPD port A

HPD port B

HPD port C

HPD

analog

switch

Figure 2. Equalizer functional diagram (one signal pair)

S1, S2, S3

Data+

OE_N

REXT

Switch

(3:1)

Current control

Equalizer

Quantizer

Data-

50 Ω

termination

selectable

Pre-amp

Output

I

driver

Data+

Data-

HPD
port Y

CS00061

AM00715V1

5/42

Block diagram STDVE003A

Figure 3. DDC I2C bus repeater

2

I C bus repeater

A_DDC_SDA

B_DDC_SDA

C_DDC_SDA

A_DDC_SCL

B_DDC_SCL

C_DDC_SCL

S1, S2, S3

Switch

1.1 Application diagrams

Figure 4. STDVE003A in a digital TV

Game

console

Y_DDC_SDA

Y_DDC_SCL

CS00062

DVD -R STB

Digital TV

6/42

STDVE003A

HDMI receiver

CS00063

STDVE003A Pin configuration

2 Pin configuration

Figure 5. Pin configuration (TQFP80 package)

DDC_1_PWR

SDA1

SCL1

GND

B11

A11

VCC

B12

A12

GND

B13

A13

VCC

B14

A14

GND

VCC

REXT

EQ_BOOST

DDC_Y_PWR

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

2

3

HPD1

80

21

S1

VCC

79

22

S2

GND

78

23

S3

A24

B24

77

76

242526

Y4

GND

VCC

75

Z4

A23

B23

74

73

27

VCC

GND

A22

71

72

STDVE003A

30

28

29

Z3

Y3

GND

B22

70

SCL2

37

GND

SDA2

HPD2

62

63

39

38

SCL_SINK

SDA_SINK

VCC

60

61

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

HPD_SINK

DDC_2_PWR

GND

A34

B34

VCC

A33

B33

GND
A32

B32

VCC
A31

B31

GND

SCL3

SDA3

HPD3

VCC

OE_N

DDC_3_PWR

CS00064

GND

GND

A21

B21

VCC

65

67

64

66

69

68

31

32

34

33

Z2

Y2

VCC

36

35

Z1

Y1

GND

Table 2. Pin description

Pin number Pin name Type Function

1 DDC_1_PWR Power

External power to connect the pull-up resistor on
DDC A ports. Connect to GND if unused.

2, 3 SDA1, SCL1 I/O Port1 DDC bus data and clock lines

4 GND Power Ground

5, 6 B11, A11 Input,TMDS Port 1 differential inputs for channel 1

7

V

CC

Power Supply voltage (3.3 V ± 5%)

8, 9 B12, A12 Input,TMDS Port 1 differential inputs for channel 2

10 GND Power Ground

11, 12 B13, A13 Input,TMDS Port 1 differential inputs for channel 3

13

V

CC

Power Supply voltage (3.3 V ± 5%)

14, 15 B14, A14 Input, TMDS Port 1 differential inputs for channel 4

7/42

Pin configuration STDVE003A

Table 2. Pin description (continued)

Pin number Pin name Type Function

16 GND Power Ground

17

V

CC

Power Supply voltage (3.3 V ± 5%)

Connect to GND through a 4.7 KΩ ± 1% precision

18

R

EXT

Analog

reference resistor. Sets the output current to
generate the output voltage compliant with TMDS

19 EQ_BOOST Input

20 DDC_Y_PWR Power

Provides equalizer boost function. Set to L for
short cables and H for long cables.

External power to connect the pull-up resistor on
DDC Y ports. Connect to GND if unused.

21, 23 S1,S2,S3 Input Source select inputs

24 GND Power Ground

25, 26 Y4, Z4

27

V

CC

28, 29 Y3, Z3

Output,

TMDS

Channel 4 differential outputs

Power Supply voltage (3.3 V ± 5%)

Output,

TMDS

Channel 3 differential outputs

30 GND Power Ground

31, 32 Y2, Z2

33

V

CC

34, 35 Y1, Z1

Output,

TMDS

Channel 2 differential outputs

Power Supply voltage (3.3 V ± 5%)

Output,

TMDS

Channel 1 differential outputs

36 GND Power Ground

37 GND Power Ground

38 SCL_SINK I/O Sink side DDC bus clock line

39 SDA_SINK I/O Sink side DDC bus data line

40 HPD_SINK Input

41 DDC_3_PWR Power

42 OE_N Input Output enable, active low

43 VCC Power Supply voltage (3.3 V ± 5%)

44 HPD3 Output

45 SDA3 I/O Port 3 DDC bus data line

46 SCL3 I/O Port 3 DDC bus clock line

8/42

Sink side hot plug detector input
High: 5 V power signal asserted from source to

sink and EDID is ready.
Low: No 5 V power signal is asserted from source

to sink or EDID is not ready.

External power to connect the pull-up resistor on
DDC C ports. Connect to GND if unused.

Port 3 hot plug detector output. Open drain output.
Connect an external resistor according to the
HDMI specification.

STDVE003A Pin configuration

Table 2. Pin description (continued)

Pin number Pin name Type Function

47 GND Power Ground

48, 49 B31, A31 Input, TMDS Port 3 differential inputs for channel 1

50 V

CC

51, 52 B32, A32 Input, TMDS Port 3 differential inputs for channel 2

53 GND Power Ground

54, 55 B33, A33 Input, TMDS Port 3 differential inputs for channel 3

56

V

CC

57, 58 B34, A34 Input, TMDS Port 3 differential inputs for channel 4

59 GND Power Ground

60 DDC_2_PWR Power

61

V

CC

62 HPD2 Output

Power Supply voltage (3.3 V ± 5%)

Power Supply voltage (3.3 V ± 5%)

External power to connect the pull-up resistor on
DDC B ports. Connect to GND if unused.

Power Supply voltage (3.3 V ± 5%)

Port 2 hot plug detector output. Open drain output.
Connect an external resistor according to the
HDMI specification.

63 SDA2 I/O Port 2 DDC bus data line

64 SCL2 I/O Port 2 DDC bus clock line

65 GND Power Ground

66 GND Power Ground

67, 68 B21, A21 Input, TMDS Port 2 differential inputs for channel 1

69

V

CC

Power Supply voltage (3.3 V ± 5%)

70, 71 B22, A22 Input, TMDS Port 2 differential inputs for channel 2

72 GND Power Ground

73, 74 B23, A23 Input, TMDS Port 2 differential inputs for channel 3

75

V

CC

Power Supply voltage (3.3 V ± 5%)

76, 77 B24, A24 Input, TMDS Port 2 differential inputs for channel 4

78 GND Power Ground

79

V

CC

Power Supply voltage (3.3 V ± 5%)

Port 1 hot plug detector output. Open drain output.

80 HPD1

Connect an external resistor according to the
HDMI specification.

9/42

Functional description STDVE003A

3 Functional description

The STDVE003A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standard like TMDS. The device passes the
differential inputs from a video source to a common display when it is in the active mode of
operation. The device conforms to the TMDS standard on both inputs and outputs.

The low on-resistance and low I/O capacitance of the switch in STDVE003A result in a very
small propagation delay. The device integrates SPDT-type switches for 3 differential data
TMDS channels and 1 differential clock channel. Additionally, it integrates the switches for
DDC and HPD line switching with I

2

The I

C interface of the selected input port is linked to the I2C interface of the output port,
and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the
unused ports, the I

2

C interfaces are isolated and the HPD pins are driven to L state.

3.1 Adaptive equalizer

The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation
from long or lossy transmission media. The inputs present high impedance when the device
is not active or when V
on input channels are present.

is absent or 0 V. In all other cases, the 50 Ω termination resistors

CC

2

C repeater on the DDC lines.

This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the
gain stage of the equalizer to compensate the signal degradation and then the signals are
driven on to the output ports.

The equalizer is fully adaptive and automatic in function providing smaller gain at low
frequencies and higher gain at high frequencies. The default setting of EQ_BOOST = L is
recommended for optimized operation.

Table 3. Gain frequency response

Frequency

(MHz)

225 3 6.5

325 5 8.5

410 6.5 11

825 11 16

1650 16 21.5

Gain in dB

(EQ_BOOST = 0)

Gain in dB

(EQ_BOOST = 1)

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STDVE003A Functional description

Figure 6. STDVE003A gain vs. frequency

The STDVE003A equalizer is fully adaptive and automatic in function. The default setting of
EQ_BOOST = L is recommended for optimal operation. The equalizer’s performance is
optimized for all frequencies over the cable lengths from 1 m to 25 m at EQ_BOOST = L.
If cable lengths greater than 25 m are desired in application, then EQ_BOOST = H setting is
recommended.

Input termination

The STDVE003A integrates precise 50 Ω ± 5% termination resistors, pulled up to VCC, on all
its differential input channels. External terminations are not required. This gives better
performance and also minimizes the PCB board space. These on-chip termination resistors
should match the differential characteristic impedance of the transmission line. Since the
output driver consists of current steering devices, an output voltage is not generated without
a termination resistor. Output voltage levels are dependent on the value of the total
termination resistance. The STDVE003A produces TMDS output levels for point-to-point
links that are doubly terminated (100

Ω at each end). With the typical 10 mA output current,

the STDVE003A produces an output voltage of 3.3 – 0.5 V = 2.8 V when driving a
termination line terminated at each end. The input terminations are selectable thus saving
power for the unselected ports.

Output buffers

Each differential output of the STDVE003A drives external 50 Ω load (pull-up resistor) and
conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential
current-steering devices.

The driver outputs are short-circuit current limited and are high-impedance to ground when
OE_N = H or the device is not powered. The current steering architecture requires a
resistive load to terminate the signal to complete the transmission loop from V
through the termination resistor. Because the device switches the direction of the current
flow and not voltage levels, the output voltage swing is determined by V

minus the voltage

CC

drop across the termination resistor. The output current drivers are controlled by the OE_N
pin and are turned off when OE_N is a high. A stable 10 mA current is derived by accurate
internal current mirrors of a stable reference current which is generated by band-gap voltage

to GND

CC

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Functional description STDVE003A

across the REXT. The differential output driver provides a typical 10 mA current sink
capability, which provides a typical 500 mV voltage drop across a 50

Ω termination resistor.

TMDS voltage levels

The TMDS interface standard is a signaling method intended for point-to-point
communication over a tightly controlled impedance medium. The TMDS standard uses a
lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing EMI emissions and system
susceptibility to noise. The device is capable of detecting differential signals as low as
100 mV within the entire common mode voltage range.

3.2 Operating modes

Table 4. OE_N operating modes

Input Output

OE_N

(ports A1, A2 or A3)

LH LHLActive mode

LL HLHActive mode

H X X Hi-Z Hi-Z Low power mode

IN+

(ports B1, B2 or B3)

IN-

OUT+ OUT-

Function

The OE_N input activates a hardware power down mode. When the power down mode is
active (OE_N = H), all input and output buffers and internal bias circuitry are powered-off
and disabled.

Outputs are tri-stated in power-down mode. When exiting power-down mode, there is a
delay associated with turning on band-references and input/output buffer circuits.

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STDVE003A Functional description

3.2.1 SEL operating modes

The active source is selected by configuring source select inputs, S1, S2 and S3. The
selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I
interface of the selected input port is linked to the I
hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused
ports, the I

2

C interfaces are isolated, and the HPD pins are kept low.

2

C interface of the output port, and the

2

C

Table 5. SEL operating modes

Control pins I/O selected Hot-plug detect status

S1 S2 S3 Y/Z

HXXA1/B1

LHXA2/B2

LLHA3/B3

LLL

H: logic high; L: logic low; X: don't care; Z: high impedance

None

(Z)

SCL_SINK

SDA_SINK

SCL1
SDA1

SCL2
SDA2

SCL3
SDA3

None (Z) L L L

HPD1 HPD2 HPD3

HPD_SINK L L

LHPD_SINKL

L L HPD_SINK

3.3 HPD pins

The input pin HPD_SINK is 5 V tolerant, allowing direct connection to 5 V signals. The
switch is able to pass both 0 V and 5 V signal levels. The HPD_SINK is an input pin while
the A_HPD, B_HPD and C_HPD are open-drain outputs.

3.4 DDC channels

The DDC channels are designed with a bidirectional NMOS gate, providing 5 V signal
tolerance. The 5 V tolerance allows direct connection to a standard I
the need for a level shifter. There should be external pull-up resistors on either side of the
device on both the SCL and SDA lines.

2

C bus, thus eliminating

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