STDP3100
DisplayPort to VGA converter
Data Brief
Features
■ Two lane DisplayPort™ 1.1a receiver
■ Triple 10-bit video DAC
– 162 MSPS throughput rate
– VSIS compatible
– RGB output with 0 to 700mV range
■ 3.3V HSYNC, VSYNC
■ Resolution through WUXGA
■ EDID, MCCS pass-through support
■ 3.3V DDC output signals
27 MHz
Crystal
Clock
Generator
SPI Flash
SPI
Controller
OCM
■ Sink detection logic
■ Low power operation – Active 400mW, standby
mode 15mW
■ Package: 64-pin LQFP, 10 x 10 mm
Applications
■ DisplayPort to VGA dongle as an attachment to
Notebook and Desktop PCs
■ DisplayPort to VGA conversion for Notebook
and Desktop PC motherboard applications
Reset
Reset
Circuit
GPIO
L0
L1
AUX
HPD
2 Lane
DisplayPort
Receiver
Pattern
Generator
HSYNC, VSYNC
Gen
DAC 10-bit color
DDC
HSYNC
VSYNC
Red
Green
Blue
DDC SDA
DDC SCL
November 2008 Rev 1 1/7
For further information contact your local STMicroelectronics sales office.
www.st.com
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Description STDP3100
1 Description
STDP3100 is a DisplayPort to VGA signal format converter for interfacing next generation
DisplayPort based PC and notebook computers with conventional VGA displays, such as
CRT, LCD monitors, and projectors. DisplayPort offers a unified, scalable, and cost effective
interface for embedded and external display applications. As desktop and notebook PCs are
increasingly transitioning from conventional analog type interfaces to DisplayPort,
STDP3100 facilitates the transition by offering seamless connectivity between new
DisplayPort PC and notebooks and the installed base VGA monitors and projectors.
STDP3100 is a highly integrated converter featuring a DisplayPort receiver, video DAC,
clock form generator, test pattern generator, and sink detection block. In addition,
STDP3100 includes EDID and MCCS pass-through features, forming a fully transparent
operation between the PC and display. Active power consumption of this device is as low as
400mW, and thus it can be powered by the DisplayPort source when used in dongle
application. The device has a built in sink detection feature that determines the active and
standby state. The device enters into standby (low power) state whenever the VGA cable is
disconnected and returns to normal operation when the cable is connected back.
STDP3100 supports video resolutions from VGA through WUXGA. The input DisplayPort
interface consists of two main lanes, AUX channel, and HPD signal that maps directly to a
standard DisplayPort connector via two layers PCB. The output interface consists of analog
R, G, B video, Hsync, Vsync, and DDC signals. Analog video signal amplitude ranges from 0
to 700mV from a 10 bit video DAC with maximum sampling frequency of 162 MHz. The VGA
output signal interface conforms to the VSIS standards with separate Hsync and Vsync
control signals. The DDC_SDA and DDC_CLK signals are driven from an I2C master, which
controls I2C traffic between the DisplayPort AUX channel and external slave device.
ST offers STDP3100 designers kit with complete reference hardware and firmware.
Figure 1. System diagram
SPI
Flash
SPI
Display
DP
Source
Main Link
AUX CH
HPD_out
3.3V from DP connector
27.000 MHz
Crystal
STDP3100
TCLK
XCLK
I2C maste r
Analog R,G,B
and Hsync, Vsync
DDC
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STDP3100 Benefits
2 Benefits
● Production-proven DisplayPort receiver from the DisplayPort leader
● Comprehensive feature set for DisplayPort to VGA dongle and for notebook embedded
application
● Proven interoperability with DisplayPort sources from all major graphics vendors
● Cost savings due to optimized BOM, low power, low EMI, and small form factor
● DisplayPort CTS compliant
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Feature attributes STDP3100
3 Feature attributes
● DisplayPort 1.1a compliant receiver offering 5.4 Gbps bandwidth over 2 lanes
● Integrated triple 10-bit, 162 MHz video DAC for analog VGA signal output
● Supports up to 1080p, 1920 x 1200 reduced blanking video resolution
● EDID and MCCS pass-through from PC source to display
● Spread Spectrum (de-spreading) for EMI reduction
● Automatic sink detection
● Low power standby mode operation initiated based on sink detection status
● SPI interface with external Serial Flash for storing firmware and system configuration
data for customization purposes
● Optional two-wire host interface for device configuration using external controller
● UART interface for chip debug and development purposes
● ISP over DP AUX channel
● General purpose I/O pins for system usage
● Powered from DisplayPort source
● 3.3V IO, 1.2V Core
● 64-pin LQFP (10 x 10 mm) package
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STDP3100 Ordering information
4 Ordering information
b
Table 1. Order codes
Part number Description
STDP3100 64-pin LQFP
(10 x 10 mm) Lead Free
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Revision history STDP3100
5 Revision history
Table 2. Document revision history
Date Revision Changes
4-Nov-2008 1 Initial release.
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STDP3100
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