ST STB7N52K3, STD7N52K3, STF7N52K3, STP7N52K3 User Manual

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STB7N52K3 - STD7N52K3

STF7N52K3 - STP7N52K3

N-channel 525 V, 0.84 Ω, 6.3 A, D2PAK, DPAK, TO-220FP, TO-220

SuperMESH3™ Power MOSFET

Preliminary Data

Features

	Type	VDSS	RDS(on)	ID	Pw
			max			3	3
			< 0.98 Ω				1
	STB7N52K3	525 V		6.3 A	90 W	1	DPAK
	STD7N52K3	525 V	< 0.98 Ω	6.3 A	90 W	D²PAK
	STF7N52K3	525 V	< 0.98 Ω	6.3 A(1)	25 W
	STP7N52K3	525 V	< 0.98 Ω	6.3 A	90 W
1.	Limited by package
						3	3
■	100% avalanche tested						2
						2	1
						1	TO-220FP
■ Extremely high dv/dt capability						TO-220

■Gate charge minimized

■Very low intrinsic capacitances

■	Improved diode reverse recovery	Figure 1. Internal schematic diagram
	characteristics
■	Zener-protected

Application

■ Switching applications

Description

The new SuperMESH3™ series is obtained through the combination of a further fine tuning of ST's well established strip-based PowerMESH™ layout with a new optimization of the vertical structure. In addition to reducing on-resistance significantly versus previous generation, special attention has been taken to ensure a very good dv/dt capability and higher margin in breakdown voltage for the most demanding application.

Table 1. Device summary

Order codes	Marking		Package	Packaging
STB7N52K3	7N52K3		D²PAK	Tape and reel
STD7N52K3	7N52K3		DPAK	Tape and reel
STF7N52K3	7N52K3		TO-220FP	Tube
STP7N52K3	7N52K3		TO-220	Tube
July 2008	Rev 1			1/15

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to	www.st.com
change without notice.

Contents	STB7N52K3 - STD7N52K3 - STF7N52K3 - STP7N52K3

Contents

1	Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 3
2	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
3	Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
4	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
5	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

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STB7N52K3 - STD7N52K3 - STF7N52K3 - STP7N52K3	Electrical ratings

1 Electrical ratings

Table 2.	Absolute maximum ratings
Symbol	Parameter			Value			Unit
			TO-220	DPAK	D²PAK	TO-220FP
VDS	Drain-source voltage (VGS = 0)		525				V
VGS	Gatesource voltage		± 30				V
I	Drain current (continuous) at T	= 25 °C	6.3			6.3 (1)	A
D	C
I	Drain current (continuous) at T	= 100 °C	4			4(1)	A
D	C
IDM (2)	Drain current (pulsed)		25			25 (1)	A
PTOT	Total dissipation at TC = 25 °C		90			25	W
	Derating factor		0.72			0.2	W/°C
VESD(G-S)	Gate source ESD(HBM-C = 100 pF,		2500				V
	R = 1.5 kΩ)
dv/dt (3)	Peak diode recovery voltage slope			TBD			V/ns
	Insulation withstand voltage (RMS) from all
VISO	three leads to external heat sink		--			2500	V
	(t = 1 s; TC = 25 °C)
Tstg	Storage temperature			-55 to 150			°C
Tj	Max. operating junction temperature		150				°C

1.Limited by package

2.Pulse width limited by safe operating area

3.ISD ≤ 6.3 A, di/dt = TBD, VDD = 80% V(BR)DSS.

Table 3.	Thermal data
Symbol	Parameter	TO-220	DPAK		D²PAK	TO-220FP	Unit
Rthj-case	Thermal resistance junction-case max		1.39			5	°C/W
Rthj-pcb	Thermal resistance junction-pcb max	--	50		30	--	°C/W
Rthj-amb	Thermal resistance junction-ambient max	62.5	--		--	62.5	°C/W
Tl	Maximum lead temperature for soldering			300			°C
	purpose

	Table 4.	Avalanche characteristics
	Symbol	Parameter	Max value	Unit
	IAR	Avalanche current, repetitive or not-repetitive	6.3	A
		(pulse width limited by Tj max)
	EAS	Single pulse avalanche energy	TBD	mJ
		(starting Tj = 25°C, ID = IAR, VDD = 50V)

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Electrical characteristics	STB7N52K3 - STD7N52K3 - STF7N52K3 - STP7N52K3

2 Electrical characteristics

(TC = 25 °C unless otherwise specified)
Table 5.	On /off states
Symbol	Parameter		Test conditions			Min.	Typ.	Max.	Unit
V(BR)DSS	Drain-source	ID = 1 mA, VGS = 0				525			V
	breakdown voltage
IDSS	Zero gate voltage	VDS = Max rating						1	µA
	drain current (VGS = 0)	VDS = Max rating, TC=125 °C						50	µA
IGSS	Gate-body leakage	VGS = ± 20 V						± 10	µA
	current (VDS = 0)
VGS(th)	Gate threshold voltage	VDS = VGS, ID = 50 µA				3	3.75	4.5	V
R	Static drain-source on	V	= 10 V, I	D	= 3.1 A		0.84	0.98	Ω
DS(on	resistance	GS

Table 6.	Dynamic
Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
gfs (1)	Forward	VDS = 15 V, ID = 3.1 A		TBD		S
	transconductance
Ciss	Input capacitance			TBD		pF
	Output capacitance
Coss		VDS = 50 V, f = 1 MHz, VGS = 0		TBD		pF
	Reverse transfer
Crss				TBD		pF
	capacitance
(1)	Equivalent output
COSS eq	capacitance	VGS = 0, VDS = 0 to 420 V		TBD		pF
RG	Intrinsic gate	f = 1 MHz open drain		TBD		Ω
	resistance
Qg	Total gate charge	VDD = 420 V, ID = 6.3 A,		TBD		nC
Qgs	Gate-source charge	VGS = 10 V		TBD		nC
Qgd	Gate-drain charge	(see Figure 3)		TBD		nC

1.Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS

Table 7.	Switching times
Symbol	Parameter	Test conditions	Min.	Typ.	Max	Unit
td(on)	Turn-on delay time	VDD = 262 V, ID = 3.1 A,		TBD		ns
tr	Rise time			TBD		ns
		RG = 4.7 Ω, VGS = 10 V
td(off)	Turn-off-delay time			TBD		ns
		(see Figure 2)
tf	Fall time			TBD		ns

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STB7N52K3 - STD7N52K3 - STF7N52K3 - STP7N52K3				Electrical characteristics
	Table 8.	Source drain diode
	Symbol	Parameter	Test conditions		Min.	Typ.	Max.	Unit
	ISD	Source-drain current					6.3	A
	(1)	Source-drain current (pulsed)					25	A
	ISDM
	(2)	Forward on voltage	ISD = 6.3 A, VGS = 0				1.6	V
	VSD
	trr	Reverse recovery time	ISD = 6.3 A, di/dt = 100 A/µs			TBD		ns
	Qrr	Reverse recovery charge				TBD		nC
			VDD = 30 V (see Figure 7)
	IRRM	Reverse recovery current				TBD		A
	trr	Reverse recovery time	ISD = 6.3 A, di/dt = 100 A/µs			TBD		ns
	Qrr	Reverse recovery charge	VDD = 30 V, Tj = 150 °C			TBD		nC
	IRRM	Reverse recovery current	(see Figure 7)			TBD		A

1.Pulse width limited by safe operating area

2.Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

Table 9.	Gate-source Zener diode
Symbol	Parameter	Test conditions	Min	Typ	Max	Unit
(1)	Gate-source breakdown	Igs=± 1 mA (open drain)	30			V
BVGSO	voltage

1.The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components

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