ST STP6NK50Z, STF6NK50Z, STD6NK50Z User Manual

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N-CHANNEL 500V - 0.93Ω - 5.6A TO-220/TO-220FP/DPAK

STP6NK50Z - STF6NK50Z

STD6NK50Z

Zener-Protected SuperMESH™ MOSFET

TYPE V

STP6NK50Z
STF6NK50Z
STD6NK50Z

■ TYPICAL R

■ EXTREMELY HIGHdv/dt CAPABILITY

■ 100% AVALANCHE TESTED

■ GATE CHARGE MINIMIZED

■ VERY LOW INTRINSIC CAPACITANCES

■ VERY GOOD MANUFACTURING

500 V
500 V
500 V

(on) = 0.93 Ω

DS

DSS

R

DS(on)

<1.2Ω
<1.2Ω
<1.2Ω

I

D

5.6 A

5.6 A

5.6 A

Pw

90 W
25 W
90 W

REPEATIBILITY

DESCRIPTION

The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established strip­based PowerMESH™ layout. In addition to pushing
on-resistance significantly down,specialcareis tak­en to ensure a very good dv/dt capability for the
most dem anding applications. Such series comple­ments ST full range of high voltage MOSFETs i n­cluding revolutionary MDm es h™ products.

TO-220 TO-220FP

3

1

DPAK

INTERNAL SCHEMATIC DIAGRAM

3

2

1

APPLICATIONS

■ HIGH CURRENT, HIGH SPEED SWITCHING

■ IDEAL FOR OFF-LINE POWER SUPPLIES,

ADAPTORS AND PFC

■ LIGHTING

ORDER CODES

PART NUMBER MARKING PACKAGE PACKAGING

STP6NK50Z P6NK50Z TO-220 TUBE
STF6NK50Z F6NK50Z TO-220FP TUBE

STD6NK50ZT4 D6NK50Z DPAK TAPE & REEL

1/12April 2004

STP6NK50Z - STF6NK50Z - STD6NK50Z

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

STP6NK50Z
STD6NK50Z

V

DS

V

DGR

V

GS

I

D

I

D

IDM()

P

TOT

Drain-source Voltage (VGS=0)
Drain-gate Voltage (RGS=20kΩ)
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC=25°C
Drain Current (continuous) at TC= 100°C

5.6 5.6 (*) A

3.5 3.5 (*) A
Drain Current (pulsed) 22.4 22.4 (*) A
Total Dissipation at TC=25°C

90 25 W

Derating Factor 0.72 0.2 W/°C

V

ESD(G-S)

Gate source ESD(HBM-C=100pF, R=1.5KΩ) 3000 V

dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns

V

ISO

T

j

T

stg

() Pulse width limited by safe operating area
(1) I

≤ 5.6A, di/dt ≤ 200 A/µs, VDD≤ V

SD

(*) Limited only by maximum temperature allowed

Insulation Withstand Voltage (DC) - 2500 V
Operating Junction Temperature

Storage Temperature

(BR)DSS,Tj

≤ T

JMAX.

-55to150 °C

STF6NK50Z

500 V
500 V

THERMAL DATA

TO-220

DPAK

Rthj-case Thermal Resistance Junction-case Max 1.38 5 °C/W

Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W

T

l

Maximum Lead Temperature For Soldering Purpose

TO-220FP

300 °C

AVALANCHE CHARACTERISTICS

Symbol Parameter Max Value Unit

I

AR

E

AS

Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T

max)

j

Single Pulse Avalanche Energy
(starting T

=25°C, ID=IAR,VDD=50V)

j

5.6 A

180 mJ

GATE-SOURCE ZENER DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

BV

GSO

Gate-SourceBreakdown

Igs=± 1mA (Open Drain) 30 V

Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes hav e specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this r es pect the Zener v olt age is appropriate to achieve an efficient and
cost-effective intervention to prote ct the device’s integrity. These integrated Z ener diodes thus avoid the
usage of external components.

2/12

STP6NK50Z - STF6NK50Z - STD6NK50Z

ELECTRICAL CHARACTERISTICS (T

=25°C UNLESS O THERWISE SPECIFIED)

CASE

ON/OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

(BR)DSS

Drain-source

ID=1mA,VGS= 0 500 V

Breakdown Voltage

I

DSS

I

GSS

V

GS(th)

R

DS(on)

Zero Gate Voltage
Drain Current (V

GS

=0)

Gate-body Leakage
Current (V

DS

=0)
Gate Threshold Voltage
Static Drain-source On

V

=MaxRating

DS

=MaxRating,TC= 125 °C

V

DS

V

= ± 20V ±10 µA

GS

V

DS=VGS,ID

= 50µA

3 3.75 4.5 V

1

50

VGS=10V,ID= 2.8 A 0.93 1.2 Ω

Resistance

DYNAMIC

Symbol Parameter Test Conditions Min. Typ. Max. Unit

g

(1) Forward Transconductance VDS=8V,ID=2.8A 4.3 S

fs

C

oss eq.

C

C

C

t

d(on)

t

d(off)

Q
Q
Q

iss
oss
rss

t

r

t

gs
gd

f

g

Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

(3) Equivalent Output

Capacitance
Turn-on Delay Time

Rise Time
Turn-off Delay Time
Fall Time

Total Gate Charge
Gate-Source Charge
Gate-Drain Charge

=25V,f=1MHz,VGS= 0 690

V

DS

100

20

VGS=0V,VDS= 0V to 400V 52 pF

=250V,ID=2.8A

V

DD

R

=4.7Ω VGS=10V

G

(Resistive Load see, Figure 3)

12

23.5
31
23

=400V,ID=5.6A,

V

DD

VGS=10V

24.6

4.9

13.3

µA
µA

pF
pF
pF

ns
ns
ns
ns

nC
nC
nC

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

SD

I

SDM

VSD(1)

t

rr

Q

rr

I

RRM

t

rr

Q

rr

I

RRM

Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.

2. Pulse width limited by safe operating area .

3. C

Source-drain Current

(2)

Source-drain Current (pulsed)
ForwardOnVoltage
Reverse Recovery Time

Reverse Recovery Charge
Reverse Recovery Current

Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current

is defined as a constant equivalent capacitance giving the same charging time as C

oss eq.

.

V

DSS

ISD=5.6A,VGS=0
I

SD

V

DD

(see test circuit, Figure 5)
ISD= 5.6 A, di/dt = 100 A/µs

VDD=48V,Tj= 150°C
(see test circuit, Figure 5)

= 5.6 A, di/dt = 100 A/µs

=48V,Tj=25°C

254

1.2
10

360

1.9
11

when VDSincreases from 0 to 80%

oss

5.6

22.4

1.6 V

A
A

ns

µC

A

ns

µC

A

3/12

STP6NK50Z - STF6NK50Z - STD6NK50Z

Thermal Impedance for TO-220Safe Operating Area for TO-220

Thermal Impedance for TO-220FPSafe Operating Area for TO-220FP

4/12

Thermal Impedance for DPAKSafe Operating Area for DPAK