This Power MOSFET is the latest development of
STMicroelectronics unique “single feature size”™
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a
remarkable manufacturing reproducibility.
Figure 7.Gate charge vs gate-source voltage Figure 8.Capacitance variations
Figure 9.Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Figure 10. Normalized on resistance vs
temperature
7/14
Test circuitSTD65NF06 - STP65NF06
3 Test circuit
Figure 12. Switching times test circuit for
resistive load
Figure 14. Test circuit for inductive load
switching and diode recovery times
Figure 13. Gate charge test circuit
Figure 15. Unclamped Inductive load test
circuit
Figure 16. Unclamped inductive waveformFigure 17. Switching time waveform
8/14
STD65NF06 - STP65NF06Package mechanical data
4 Package mechanical data
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packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at : www.st.com
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