The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS
(#) When mount ed on 1inch² FR-4, 2 Oz c opper board.
Maximum Lead Temperature For Soldering Purpose300
°C
Table 4: Avalanche Characteristics
SymbolParameterMax ValueUnit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
5A
(pulse width limited by Tj max)
E
AS
Single Pulse Avalanche Energy
220mJ
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
Table 5: Gate-Source Zener Diode
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)30V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZEN E R DIODES
The built-in back-to-back Zener diodes have sp ecifically been desig ned to enhance not only the dev ice’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an ef ficient and
cost-effective intervention t o protec t t he d ev ice’s i ntegrity. T hese integrated Zener d iodes thu s av oid the
usage of external components.
2/14
STP5NK60Z - STP5NK60Z FP- STD5NK60Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 6: On/Off
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain-source
ID = 1 mA, VGS = 0600V
Breakdown Voltage
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (VGS = 0)
Gate-body Leaka ge
VDS = Max Rating
VDS = Max Rating, TC = 125 °C
1
50
VGS = ± 20V±10µA
Current (VDS = 0)
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
VDS = VGS, ID = 50µA
33.754.5V
VGS = 10V, ID = 2.5 A1.21.6Ω
Resistance
Table 7: Dynamic
SymbolParameterTest ConditionsMin.Typ.Max.Unit
g
(1)Forward TransconductanceVDS = 8 V, ID = 2.5 A 4S
fs
C
oss eq.
C
iss
C
oss
C
rss
t
d(on)
t
t
d(off)
t
t
r(Voff)
t
t
Q
Q
Q
r
r
f
c
g
gs
gd
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3)Equivalent Outpu t
Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Off-voltage Rise Time
Fall Time
Cross-over Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDS = 25V, f = 1 MHz, VGS = 0690
90
20
VGS = 0V, VDS = 0V to 480V40pF
VDD = 300 V, ID = 2.5 A
RG = 4.7Ω VGS = 10 V
(see Figure 20)
16
25
36
25
VDD = 480V, ID = 5 A,
RG = 4.7Ω, V
GS
= 10V
(see Figure 20)
VDD = 400V, ID = 5 A,
VGS = 10V
(see Figure 23)
12
10
24
26
20
34nC
6
µA
µA
pF
pF
pF
ns
ns
ns
ns
ns
ns
ns
nC
nC
Table 8: Source Drain Diode
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SD
I
(2)
SDM
VSD (1)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: P ul se duration = 300 µs, d ut y cy cle 1.5 %.
2. Pulse wi dt h l i m ited by safe op erating area.
3. C
Source-drain Current
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
oss eq.
.
V
DSS
ISD = 5 A, VGS = 0
ISD = 5 A, di/dt = 100A/µs
VDD = 30V, Tj = 150°C
(see Figure 21)
485
2.7
11
when VDS increases from 0 to 80%
oss
5
20
1.6V
A
A
ns
µC
A
3/14
STP5NK60Z - STP5NK60ZFP- STD5NK60Z
Figure 3: Safe Operating Area For TO-220/
DPAK
Figure 4: Safe Operating Area For TO-220FP
Figure 6: Thermal Impedance For TO-220/
DPAK
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Output Characteristics
4/14
Figure 8: Transfer Characteristics
STP5NK60Z - STP5NK60Z FP- STD5NK60Z
Figure 9: Transconductance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 12: Static Drain-source On Resistance
Figure 13: Capacitance Variations
Figure 11: Normalized Gate Threshold Voltage
vs Tem pera tur e
Figure 14: Normal ized On R esistance vs Temperature
Figure 15:
5/14
STP5NK60Z - STP5NK60ZFP- STD5NK60Z
Figure 16: S ource-Drain Forward Char acteristics
Figure 17: Maximum Avalanche Energy vs
Temperature
Figure 18: Normalized BVdss vs Temperature
6/14
STP5NK60Z - STP5NK60Z FP- STD5NK60Z
Figure 19: Unclamped Inductive Load Test Circuit
Figure 20: Switching Times Test Circuit For
Resistive Load
Figure 22: Unclamped Inductive Wafeform
Figure 23: Gate Charge Test Circuit
Figure 21: Test Circuit For Inductive Load
Switching and Diode Recovery Times
7/14
STP5NK60Z - STP5NK60ZFP- STD5NK60Z
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the package and on the inner box label, i n compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark. ECOPACK specifications are available at:
05-Apr-20051First issue
29-Apr-20052Modified value in Table 7.
06-Sep-20053Inserted Ecopack indication
14-Oct-20054Modified value on Table 1
28-Oct-20055Tape & Reel info added
14-Nov-20056Modified value on Table 6
15-Dec-20057Various corrections
STP5NK60Z - STP5NK60Z FP- STD5NK60Z
13/14
STP5NK60Z - STP5NK60ZFP- STD5NK60Z
I
s
o
d
b
t
t
t
a
nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequence
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