High power white LED driver with I²C interface
Features
■ Buck-boost DC-DC converter
■ Drives one power white LED up to 800 mA from
2.7 V to 5.5 V in QFN
■ Drives one power white LED up to 800 mA from
3.3 V to 5.5 V in BGA
■ Efficient up to 92%
■ Output current control
■ 1.8 MHz typ. fixed frequency PWM
■ Synchronous rectification
■ Full I²C control
■ Operational modes:
– Shutdown mode
– Shutdown + NTC
– Ready mode + auxiliary red LED
– Flash mode: up to 800 mA
– Torch mode: up to 200 mA
■ Soft and hard triggering of flash
■ Flash and torch dimming with 16 exponential
values
■ Dimmable red LED indicator auxiliary output
■ Internally or externally timed flash operation
■ Digitally programmable safety time-out in flash
mode
■ LED overtemperature detection and protection
with external NTC resistor
■ Opened and shorted LED failure detection and
protection
■ Chip over temperature detection and protection
■ < 1 µA shutdown current
STCF03
QFN20 (4 x 4)
■ Packages:
–QFN20 (4 x 4)
– TFBGA25 (3 x 3)
Applications
■ Cell phone and smart phone
■ Camera flashes/strobe
■ PDAs and digital still cameras
Description
The STCF03 is a high efficiency power supply
solution to drive a single flash LED in camera
phone, PDAs and other hand-held devices. It is a
buck - boost converter to guarantee a proper LED
current control over all possible conditions of
battery voltage and output voltage; the output
current control ensure a good current regulation
over the forward voltage spread characteristics of
the flash LED. Thanks to the high efficiency of the
converter allows having the input current taken
from the battery remain under 1.5 A.
TFBGA25 (3 x 3)
Table 1. Device summary
Order codes Packages Packaging
STCF03PNR QFN20 (4 x 4 mm) 4500 parts per reel
STCF03TBR TFBGA25 (3 x 3 mm) 3000 parts per reel
February 2011 Doc ID 13169 Rev 7 1/35
www.st.com
35
Contents STCF03
Contents
1 Description (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Buck-boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2 Logic pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.1 SCL, SDA pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.2 TRIG pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.3 ATN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.4 ADD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.2.5 TMSK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.3 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.4 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.5 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.6 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.7 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.8 Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.9 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.10 Writing to multiple registers with incremental addressing . . . . . . . . . . . . 18
7.11 Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.12 Reading from multiple registers with incremental addressing . . . . . . . . . 19
8 Description of internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.1 PWR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/35 Doc ID 13169 Rev 7
STCF03 Contents
8.2 TRIG_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.3 TCH_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.4 NTC_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.5 FTIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.6 TDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.7 FDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.8 AUXI_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.9 AUXT_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.10 F_RUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.11 LED_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.12 NTC_W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.13 NTC_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.14 OT_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.15 VOUTOK_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.1 PowerON reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2 Shutdown, shutdown with NTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.3 Ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.4 Single or multiple Flash using external (microprocessor) temporization . 25
9.5 External (microprocessor) temporization using TRIG_EN bit . . . . . . . . . 26
9.6 Single Flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . . 26
9.7 Multiple Flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . 26
10 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 13169 Rev 7 3/35
List of tables STCF03
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. List of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. I²C register mapping function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Dimming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Auxiliary LED dimming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Torch mode and flash mode dimming registers settings . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Status register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. QFN20 (4 x 4 mm.) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4/35 Doc ID 13169 Rev 7
STCF03 List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Pin connections (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Procedure for assigning a non-default I²C address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Data validity on the I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Timing diagram on I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Acknowledge on I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Writing to multiple register with incremental addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Reading from multiple registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Flash and Torch current vs. dimming value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. VOUTOK_N behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. I
Figure 17. I
OTORCH
OFLASH
Figure 18. IOAUX vs. AUXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 19. I
OFLASH
Figure 20. VFB2 vs. temp. at I
Figure 21. I
Q
Figure 22. Start-up in flash mode 800 mA at V
Figure 23. Line transient in flash mode 800 mA, change of V
Figure 24. QFN20 (4 x 4 mm.) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
vs. T_DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
vs. F_DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
vs. temp. VI = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
= 800 mA,VI = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
O
vs. temp. VI = 5.5 V ready-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
= 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
I
from 2.7 V to 3.3 V in 10 µs . . . . . . . . 28
I
Doc ID 13169 Rev 7 5/35
Description (continued) STCF03
1 Description (continued)
All the functions of the device are controlled through the I²C which helps bus that allows to
reduce logic pins on the package and to save PCB tracks on the board. Hard and softtriggering of flash are both supported. The device includes many functions to protect the
chip and the power LED such as: a soft start control, chip over temperature detection and
protection as well as opened and shorted LED detection and protection. Besides, a digital
programmable time out function protects the LED in case of a wrong command from the
microprocessor. An optional external NTC resistor is supported to protect the LED against
over heating.
In mobile phone applications it is possible to reduce immediately the flash LED current
during the signal transmission using the TMSK pin. This saves battery life and gives more
priority to supply RF transmission instead of flash function.
It is possible by I²C to separately program the current intensity in flash and torch mode using
exponential steps. An auxiliary output can control an optional red LED to be used as a
recording indicator.
The device is packaged in QFN (4 x 4 mm) 20L with a height less than 1 mm and in
TFBGA25 (3 x 3 mm).
6/35 Doc ID 13169 Rev 7
STCF03 Diagram
2 Diagram
Figure 1. Block diagram
Doc ID 13169 Rev 7 7/35
Pin configuration STCF03
3 Pin configuration
Figure 2. Pin connections (bottom view)
QFN20 (4x4)
Table 2. Pin description
Pin n° for
QFN20
Pin n° for
TFBGA25
Symbol Name and function
1 E1, D2 VLX2 Inductor connection
2B3RXR
resistor connection
X
3 A4 NTC NTC resistor connection
4 D1, C2 VOUT Output voltage
5 B5 FB1 Feedback pin [I
6A5FB2R
bypass
TR
7 B4 FB2S Feedback sensing pin [I
8 E2 GND Signal ground
9 D4 ADD I²C address selection
10 D5 AUXL Auxiliary LED output
11 C5 TMSK TX mask input.
12 B1, C1 PVBAT Power supply voltage
13 A3 VBAT Supply voltage
*(RFL+RTR)]
LED
LED*RFL
TFBGA25 (3x3)
]
14 A2 VLX1A Inductor connection
15 A1, B2 VLX1B Inductor connection
16 E5 SCL I²C clock signal
17 E3 SDA I²C data
18 C3, D3 PGND Power ground
19 E4 ATN Attention (open drain output, active LOW)
20 C4 TRIG Flash trigger input
Exposed pad PGND
To be connected to the PCB ground plane for optimal electrical and
thermal performance
8/35 Doc ID 13169 Rev 7
STCF03 Maximum ratings
4 Maximum ratings
Table 3. Absolute maximum ratings
(1)
Symbol Parameter Value Unit
VBAT Signal supply voltage -0.3 to 6 V
PVBAT Power supply voltage -0.3 to 6 V
VLX1A, VLX1B Inductor connection 1 –0.3 to V
VLX2 Inductor connection 2 –0.3 to V
+0.3 V
I
+0.3 V
O
VOUT Output voltage -0.3 to 6 V
AUXL Auxiliary LED –0.3 to VI+0.3 V
FB1, FB2, FB2S Feedback and sense voltage -0.3 to 3 V
SCL, SDA, TRIG,
ATN, ADD TMSK
R
X
Logic pin -0.3 to V
Connection for reference resistor -0.3 to 3 V
+0.3 V
I
NTC Connection for LED temperature sensing -0.3 to 3 V
ESD Human body model ±2kV
(2)
(BGA)
P
TOT
T
OP
T
J
T
STG
1. Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under
these condition is not implied.
2. Power dissipation is related parameter to used PCB. The recommended PCB design is included in the application note.
Continuous power dissipation (at TA=70°C) 800 mW
Operating junction temperature range -40 to 85 °C
Junction temperature -40 to 150 °C
Storage temperature range -65 to 150 °C
Table 4. Thermal data
Symbol Parameter QFN20 TFBGA25 Unit
R
thJA
Thermal resistance junction-ambient 59 150 °C/W
Doc ID 13169 Rev 7 9/35
Application STCF03
5 Application
Figure 3. Application schematic
**: Connect to VI, or GND or SDA or SCL to choose one of the 4 different I²C Slave Addresses.
***: Optional components to support auxiliary functions.
Table 5. List of external components
Component Manufacturer Part number Value Size
L (I
L (I
C
I
C
O
= 0.5A) TDK VLF3012ST-4R7MR91 4.7 µH 2.6 x 2.8 x 1.2 mm
FLASH
= 0.8A) TDK VLF4012AT-4R7M1R1 4.7 µH 3.7 x 3.5 x 1.2 mm
FLASH
TDK X5R0J106M 10 µF 0603
TDK X5R0J105M 1 µF 0603
NTC Murata NCP21WF104J03RA 100 kΩ 0805
R
FL
R
TR
R
X
0.27 Ω 0603
1.8 Ω 0402
15 kΩ 0402
Note: All of the above listed components refer to typical application. Operation of the STCF03 is
not limited to the choice of these external components.
10/35 Doc ID 13169 Rev 7
STCF03 Electrical characteristics
6 Electrical characteristics
TJ = 25 °C, VI = 3.6 V, 2 x CI = 10 µF, CO = 1 µF, L = 4.7 µH, RFL = 0.27 Ω, R
R
= 15 kΩ, Typ. values @ 25 °C, unless otherwise specified.
X
Table 6. Electrical characteristics
= 1.8 Ω,
TR
Symbol Parameter Test condition Min. Typ. Max. Unit
V
Input operation supply voltage 2.7 5.5 V
I
V
PW_ON
RESET
V
Power ON reset threshold VI rising 2.3 V
Flash mode for VI = 2.7 V to 5.5 V
(STCF03PNR)
Output current adjustment
range I
FLASH
I
O
Output current adjustment
range I
TORC H
Auxiliary LED output current
adjustment range I
Regulated voltage range 2.5 5.3 V
O
AUXLED
Flash mode for V
= 2.7 V to 3.3 V
I
(STCF03TBR)
Flash mode for V
=3.3 V to 5.5 V
I
(STCF03TBR)
Torch mode VI = 2.7 V to 5.5 V 15 200
Ready mode, VI = 3.3 V to 5.5 V 0 20
60 800
60 600
60 800
FB1 Feedback voltage Torch mode 30 250 mV
FB2 Feedback voltage Flash mode 30 250 mV
mA
ΔI
R
Output current tolerance Flash mode, IO = 160 mV/R
O
FB1-FB2 ON resistance Torch mode, IO = 200 mA 90 mΩ
ON_
Quiescent current in
SHUTDOWN mode
I
Q
NTC_ON=0 1
NTC_ON=1 1
FL
Quiescent current in ready mode
Frequency VI = 2.7 V 1.8 MHz
f
s
= 3.2 to 4.2 V, flash mode,
V
Efficiency of the chip itself
ν
Efficiency of the whole
application
I
= 800 mA
I
O
V
= 3.2 to 4.2 V, flash mode,
I
IO = 800 mA, VO=V
fLED_max
+ V
FB2
5.02 V
See the typical application schematic
-10 10 %
1.8 mA
87
=
76
It is included losses of inductor and
sensing resistor
OVP Output over voltage protection V
OV
Over voltage hysteresis VI = 5.5 V, No Load 0.3 V
HYST
OTP Over temperature protection V
OT
R
ON
Over temperature hysteresis VI = 5.5 V 20 °C
HYST
T1 RX-NTC switch ON resistance Ready mode 25 Ω
= 5.5 V, No Load 5.3 V
I
= 5.5 V 140 °C
I
µA
%
Doc ID 13169 Rev 7 11/35
Electrical characteristics STCF03
Table 6. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
NTC
V
I
V
V
T
RX-NTC switch OFF leakage
LEAK
Output logic signal level low
OL
AT N
Output logic leakage current
OZ
AT N
IL
Input logic signal level SCL,
SDA, TRIG, TEST, ADD
IH
LED current rise time I
ON
to I
= max
LED
LED
Shutdown mode, V
= GND
V
RX
I
= 10 mA 0.2 V
OL
= 3.3 V 1 mA
V
OZ
= 2.7 V to 5.5 V 0 0.4 V
V
I
= 0
Note: Typical value, not production tested.
NTC
= 2 V
1 µA
1.4 3
2ms
12/35 Doc ID 13169 Rev 7
STCF03 Introduction
7 Introduction
The STCF03 is a buck-boost converter, dedicated to power and control the current of a
power white LED in a camera cell phone. The device operates at a constant switching
frequency of 1.8 MHz typ. It provides an output voltage down to 2.5 V and up to 5.3 V, from
a 2.7 V to 5.5 V supply voltage. This supply range allows operation from a single cell
Lithium-Ion battery. The I²C bus is used to control the device operation and for diagnostic
purposes. The current in torch mode is adjustable from 15 mA to 200 mA. Flash mode
current is adjustable up to 800 mA, BGA version is able to deliver 600 mA at battery range
2.7 V to 3.3 V. The Aux LED current can be adjusted from 0 to 20 mA. The device uses an
external NTC resistor to sense the temperature of the white LED. These two last functions
may not be needed in all applications, and in these cases the relevant external components
can be omitted.
7.1 Buck-boost converter
The regulation of the PWM controller is done by sensing the current of the LED through
external sensing resistors (R
forward voltage of the flash LED, the device automatically can change the operation mode
between buck (step down) and boost (step up) mode.
and RTR, see application schematic). Depending on the
FL
Three cases can occur: boost region (V
cases, as the output voltage V
< V
); buck - boost region (VO ~ V
BAT
O
7.2 Logic pin description
7.2.1 SCL, SDA pins
These are the standard clock and data pins as defined in the I²C bus specification. External
pull-up is required according to I²C bus specifications. The recommended maximum voltage
of these signals should be 3.0 V.
7.2.2 TRIG pin
This input pin is internally AND-ed with the TRIG_EN bit to generate the internal signal that
activates the flash operation. This gives to the user the possibility to accurately control the
flash duration using a dedicated pin, avoiding the I²C bus latencies (hard-triggering). No
internal pull-up nor pull-down is provided.
7.2.3 ATN pin
This output pin (open-drain, active LOW) is provided to better manage the information
transfer from the STCF03 to the microprocessor. Because of the limitations of a single
master I²C bus configuration, the microprocessor should regularly poll the STCF03 to verify
if certain operations have been completed, or to check diagnostic information. Alternatively,
the microprocessor can use the ATN pin to be advised that new data are available in the
STAT_REG, thus avoiding continuous polling. Then the information can be read in the
STAT_REG by a read operation via I²C that, besides, automatically resets the ATN pin. The
STAT_REG bits affecting the ATN pin status are mapped in Ta b le 1 6 . No internal pull-up is
provided.
= V
fLED
BAT
O
+ I
).
> V
): this configuration is used in most of the
BAT
x RFL) is higher than V
LED
; buck region (VO
BAT
Doc ID 13169 Rev 7 13/35
Introduction STCF03
7.2.4 ADD pin
With this pin it is possible to select one of the 4 possible I²C slave addresses. No internal
pull-up nor pull-down is provided. The pin has to be connected either GND, V
to select the desired I²C slave address (see Ta b le 6 )
Table 7. Address table
ADD pin A7 A6 A5 A4 A3 A2 A1 A0
GND0110000R/W
VBAT0110001R/W
SDAL0110010R/W
SCL0110011R/W
When ADD is connected to GND the I²C address is assigned automatically while in the
other three configurations in which ADD pin is connected to VBAT or SDA or SCL, the
following procedure must be activated in order that the right address is assigned.
After applying VBAT to the chip, the VBAT voltage must be pulled down to GND for a time
longer than 100 ms. After that time the right I²C address is assigned to the chip. This
procedure must be repeated every time the VBAT voltage is disconnected (see Figure 4
below)
, SCL or SDA
I
Figure 4. Procedure for assigning a non-default I²C address
Address is assigned.
Address is assigned.
The new I²C address
The new I²C address
can be used for SCL
can be used for SCL
and SDA
and SDA
SCL LINE
….
….
W
W
R
R
I
I
T
T
E
E
L
R
L
R
S
/
S
/
B
W
B
W
SCL LINE
ADDRESS OF
ADDRESS OF
REGISTER
REGISTER
A
M
A
M
C
S
C
S
K
B
K
B
SDA LINE
SDA LINE
A
A
M
L
A
A
M
L
C
C
S
S
C
C
S
S
K
K
B
B
K
K
B
B
100ms
100ms
S
S
T
T
A
A
R
R
T
T
VBAT
VBAT
M
M
S
S
B
B
DEVICE
DEVICE
ADDRESS
ADDRESS
7 bits
7 bits
7.2.5 TMSK pin
DATA
DATA
S
S
T
T
O
O
P
P
A
L
A
L
C
S
C
S
K
B
K
B
This pin can be used to implement the TX masking function. This function has effect only for
flash current settings higher than 200 mA (bit FDIM_3 = 1). Under this condition, when this
pin is pulled high by the P, the current flowing in the LED is forced at 200 mA typ. No internal
pull-up nor pull-down is provided: to be externally wired to GND if TX masking function is not
used.
14/35 Doc ID 13169 Rev 7
STCF03 Introduction
7.3 I²C bus interface
Data transmission from the main microprocessor STCF03 and vice versa takes place
through the 2 wires I²C bus interface wires, consisting of the two lines SDA and SCL (pull-up
resistors to a positive supply voltage must be externally connected). The recommended
maximum voltage of these signals should be 3.0 V.
7.4 Data validity
As shown in Figure 5, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
Figure 5. Data validity on the I²C Bus
7.5 Start and stop conditions
Both DATA and CLOCK lines remain HIGH when the bus is not busy. As shown in Figure 6 a
start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition
must be sent before each START condition.
Figure 6. Timing diagram on I²C Bus
Doc ID 13169 Rev 7 15/35
Introduction STCF03
7.6 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock
pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse. Any change in the SDA line at this time will be interpreted as a control signal.
Figure 7. Bit transfer
7.7 Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 8). The peripheral (STCF03) that acknowledges has to
pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed has to
generate an acknowledge pulse after the reception of each byte, otherwise the SDA line
remains at the HIGH level during the ninth clock pulse duration. In this case the master
transmitter can generate the STOP information in order to abort the transfer. The STCF03
won't generate the acknowledge if the V
Figure 8. Acknowledge on I²C Bus
supply is below the undervoltage lockout threshold.
I
16/35 Doc ID 13169 Rev 7
STCF03 Introduction
Table 8. Interface protocol
Device address + R/W bit Register address Data
76543210 76543210 76543210
S
T
M
A
S
R
B
L
S
B
W
A
R
M
C
S
K
B
L
A
M
S
C
S
B
K
B
L
S
B
T
S
A
T
C
O
K
P
7.8 Writing to a single register
Writing to a single register starts with a START bit followed by the 7 bit device address of
STCF03. The 8
th
bit is the R/W bit, which is 0 in this case. R/W = 1 means a reading
operation. Then the master waits for an acknowledge from STCF03. Then the 8 bit address
of register is sent to STCF03. It is also followed by an acknowledge pulse. The last
transmitted byte is the data that is going to be written to the register. It is again followed by
an acknowledge pulse from STCF03. Then master generates a STOP bit and the
communication is over. See Figure 9 below.
Figure 9. Writing to a single register
W
W
DEVICE
DEVICE
DEVICE
ADDRESS
ADDRESS
ADDRESS
7 bits
7 bits
7 bits
S
S
S
M
M
M
T
T
T
S
S
S
A
A
A
B
B
B
R
R
R
T
T
T
W
R
R
R
I
I
I
T
T
T
E
E
E
R
R
R
A
L
A
L
A
L
/
/
/
C
S
C
S
C
S
W
W
W
K
B
K
B
K
B
M
M
M
S
S
S
B
B
B
SDA LINE
SDA LINE
ADDRESS OF
ADDRESS OF
ADDRESS OF
REGISTER
REGISTER
REGISTER
DATA
DATA
DATA
A
M
L
A
M
L
A
M
L
A
A
A
C
S
S
C
S
S
C
S
S
C
C
C
K
B
B
K
B
B
K
B
B
K
K
K
L
L
L
A
S
A
S
A
S
S
S
S
C
T
C
T
C
T
B
B
B
K
O
K
O
K
O
P
P
P
7.9 Interface protocol
The interface protocol is composed:
– A start condition (START)
– A Device address + R/W bit (read =1 / write =0)
– A Register address byte
– A sequence of data n* (1 byte + acknowledge)
– A stop condition (STOP)
Doc ID 13169 Rev 7 17/35
Introduction STCF03
The register address byte determines the first register in which the read or write operation
takes place. When the read or write operation is finished, the register address is
automatically increased.
7.10 Writing to multiple registers with incremental addressing
It would be unpractical to send several times the device address and the address of the
register when writing to multiple registers. STCF03 supports writing to multiple registers with
incremental addressing. When the data is written to a register, the address register is
automatically increased, so the next data can be sent without sending the device address
and the register address again. See Figure 10 below.
Figure 10. Writing to multiple register with incremental addressing
W
W
7 bits
7 bits
7 bits
W
R
R
R
ADDRESS OF
ADDRESS OF
ADDRESS OF
I
I
I
REGISTER i
REGISTER i
REGISTER i
T
T
T
E
E
E
DATA i
DATA i
DATA i
DATA i+1
DATA i+1
DATA i+1
DATA i+2
DATA i+2
DATA i+2
DATA i+2
DATA i+2
DATA i+2
DATA i+n
DATA i+n
DATA i+n
DEVICE
DEVICE
DEVICE
ADDRESS
ADDRESS
ADDRESS
M
M
M
A
A
S
S
S
M
M
M
T
T
T
S
S
S
A
A
A
B
B
B
R
R
R
T
T
T
A
R
R
R
L
L
L
S
S
S
C
C
C
/
/
/
S
S
S
B
B
B
K
K
K
W
W
W
B
B
B
A
M
L
A
M
L
A
M
L
A
M
A
M
A
M
C
S
S
C
S
S
C
S
S
C
S
C
S
C
S
K
B
B
K
B
B
K
B
B
K
B
K
B
K
B
A
L
A
L
A
L
M
M
M
C
S
C
S
C
S
S
S
S
K
B
K
B
K
B
B
B
B
SDA LINE
SDA LINE
L
L
L
S
S
S
B
B
B
7.11 Reading from a single register
The reading operation starts with a START bit followed by the 7 bit device address of
STCF03. The 8
the address + R/W bit by an acknowledge pulse. The address of the register which should
be read is sent afterwards and confirmed again by an acknowledge pulse of STCF03 again.
Then the master generates a START bit again and sends the device address followed by the
R/W bit, which is 1 now. STCF03 confirms the receiving of the address + R/W bit by an
acknowledge pulse and starts to send the data to the master. No acknowledge pulse from
the master is required after receiving the data. Then the master generates a STOP bit to
terminate the communication. See Figure 11.
th
bit is the R/W bit, which is 0 in this case. STCF03 confirms the receiving of
A
A
A
M
M
M
C
C
C
S
S
S
K
K
K
B
B
B
A
L
A
L
A
L
M
M
M
C
S
C
S
C
S
S
S
S
K
B
K
B
K
B
B
B
B
L
L
L
M
A
M
A
M
A
S
S
S
S
C
S
C
S
C
B
B
B
B
K
B
K
B
K
S
S
S
A
L
A
L
A
L
T
T
T
C
S
C
S
C
S
O
O
O
K
B
K
B
K
B
P
P
P
18/35 Doc ID 13169 Rev 7
STCF03 Introduction
Figure 11. Reading from a single register
W
DEVICE
DEVICE
ADDRESS
ADDRESS
7 bits
7 bits
W
R
R
I
I
T
T
E
E
ADDRESS
ADDRESS
OF
OF
REGISTER
REGISTER
DEVICE
DEVICE
ADDRESS
ADDRESS
7 bits
7 bits
R
R
E
E
A
A
D
D
DATA
DATA
L
M
M
S
S
S
S
T
T
B
B
A
A
R
R
T
T
L
M
M
A
A
R
R
S
S
S
S
C
C
/
/
B
B
B
B
K
K
W
W
L
L
A
A
S
S
S
S
C
C
T
T
B
B
K
K
A
A
R
R
T
T
SDA LINE
SDA LINE
R
R
A
A
/
/
C
C
W
W
K
K
S
N
S
N
L
L
T
O
T
O
S
S
O
O
B
B
P
A
P
A
C
C
K
K
7.12 Reading from multiple registers with incremental addressing
Reading from multiple registers starts in the same way like reading from a single register. As
soon as the first register is read, the register address is automatically increased. If the
master generates an acknowledge pulse after receiving the data from the first register, then
reading of the next register can start immediately without sending the device address and
the register address again. The last acknowledge pulse before the STOP bit is not required.
See the Figure 12.
Figure 12. Reading from multiple registers
W
DEVICE
DEVICE
ADDRESS
ADDRESS
7 bits
7 bits
W
R
R
ADDRESS OF
ADDRESS OF
I
I
REGISTER i
REGISTER i
T
T
E
E
DEVICE
DEVICE
ADDRESS
ADDRESS
7 bits
7 bits
R
R
E
E
DATA i
DATA i
A
A
D
D
DATA i+1
DATA i+1
DATA i+2
DATA i+2
DATA i+2
DATA i+2
DATA i+n
DATA i+n
L
L
M
M
S
S
S
S
T
T
B
B
A
A
R
R
T
T
L
A
A
M
M
R
R
S
S
C
C
S
S
/
/
B
B
K
K
B
B
W
W
L
L
A
A
S
S
S
S
C
C
T
T
B
B
K
K
A
A
R
R
T
T
R
R
A
A
/
/
C
C
W
W
K
K
L
L
S
S
B
B
SDA LINE
SDA LINE
L
A
A
M
M
C
C
S
S
K
K
B
B
L
A
A
M
M
S
S
C
C
S
S
B
B
K
K
B
B
L
L
M
M
A
A
S
S
S
S
C
C
B
B
B
B
K
K
A
A
M
M
L
L
C
C
S
S
S
S
K
K
B
B
B
B
L
S
S
N
N
S
S
T
T
O
O
B
B
O
O
P
P
A
A
C
C
K
K
Doc ID 13169 Rev 7 19/35
Description of internal registers STCF03
8 Description of internal registers
Table 9. I²C register mapping function
Register name SUB ADDRESS (hex) Operation
CMD_REG 00 R / W
DIM_REG 01 R / W
AUX_REG 02 R / W
STAT_REG 03 R only
Table 10. Command register
CMD_REG
(write mode)
SUB ADD=00 PWR_ON TRIG_EN TCH_ON NTC_ON FTIM_3 FTIM_2 FTIM_1 FTIM_0
Power ON
RESET Value
MSB LSB
0 0 000000
8.1 PWR_ON
When set, it activates all analog and power internal blocks including the NTC supporting
circuit, and the device is ready to operate (ready mode). As long as PWR_ON=0, only the
I²C interface is active, minimizing stand-by mode power consumption.
8.2 TRIG_EN
This bit is AND-ed with the TRIG pin to generate the internal signal FL_ON that activates
flash mode. By this way, both soft-triggering and hard-triggering of the flash are made
possible. If soft-triggering (through I²C) is chosen, the TRIG pin is not used and must be
kept HIGH (VI). If hard-triggering is chosen, then the TRIG pin has to be connected to a
microprocessor I/O devoted to flash timing control, and the TRIG_EN bit must be set in
advance. Both triggering modes can benefit of the internal flash time counter, that uses the
TRIG_EN bit and can work either as a safety shut-down timer or as a flash duration timer.
Flash mode can start only if PWR_ON=1. LED current is controlled by the value set by the
FDIM_0~3 of the DIM_REG.
8.3 TCH_ON
When set from ready mode, the STCF03 enters the torch mode. The LED current is
controlled by the value set by the TDIM_0~3 of the DIM_REG.
8.4 NTC_ON
In ready mode, the comparators that monitor the LED temperature are activated if NTC_ON
bit is set. NTC-related blocks are always active regardless of this bit in torch mode and flash
mode.
20/35 Doc ID 13169 Rev 7
STCF03 Description of internal registers
8.5 FTIM_0~3
This 4bit register defines the maximum flash duration. It is intended to limit the energy
dissipated by the LED to a maximum safe value or to leave to the STCF03 the control of the
flash duration during normal operation. Values from 0~15 correspond to 0~1.5 s (100 ms
steps). The timing accuracy is related to the internal oscillator frequency that clocks the
flash time counter (+/- 20 %). Entering flash mode (either by soft or hard triggering) activates
the flash time counter, which begins counting down from the value loaded in the F_TIM
register. When the counter reaches zero, flash mode is stopped by resetting TRIG_EN bit,
and simultaneously the ATN pin is set to true (LOW) to alert the microprocessor that the
maximum time has been reached. FTIM value remains unaltered at the end of the count.
Table 11. Dimming register
DIM_REG
(write mode)
SUB ADD=01 TDIM_3 TDIM_2 TDIM_1 TDIM_0 FDIM_3 FDIM_2 FDIM_1 FDIM_0
Power ON, SHUTDOWN
RESET Value
MODE
MSB LSB
00000000
8.6 TDIM_0~3
These 4 bits define the LED current in torch mode with 16 values fitting an exponential law.
Max torch current value is 25% of max flash current. (Figure 13)
8.7 FDIM_0~3
These 4 bits define the LED current in flash mode with 16 values fitting an exponential law.
The max value of the current is set by the external resistors R
Figure 13. Flash and Torch current vs. dimming value
and RTR. (Figure 13)
FL
Note: LED current values refer to RFL=0.27 Ω, RTR=1.8 Ω
Doc ID 13169 Rev 7 21/35
Current Step Coefficient - 1.19
Description of internal registers STCF03
Table 12. Auxiliary register
AUX_RE G
(write mode)
MSB LSB
SUB ADD=02 AUXI_3 AUXI_2 AUXI_1 AUXI_0 AUXT_3 AUXT_2 AUXT_1 AUXT_0
Power ON,
SHUTDOWN MODE
00 000 000
RESET Value
8.8 AUXI_0~3
This 4 bits register defines the AUX LED current from 0 to 20 mA. See AUX LED dimming
table for reference. Loading any value between 1 and 15 also starts the AUX LED current
source timer, if enabled. The AUX LED current source is active only in Ready Mode, and is
deactivated in any other mode.
8.9 AUXT_0~3
This 4 bit register controls the timer that defines the ON-time of the AUX LED current
source. ON-time starts when the AUXI register is loaded with any value other than zero, and
stops after the time defined in the AUXT register. Values from 1 to 14 of the AUXT register
correspond to an ON-time of the AUX LED ranging from 100 to 1400 ms in 100 ms steps.
The value 15 puts the AUX LED to the continuous light mode. The activation/deactivation of
the AUX LED current source is controlled using only the AUXI register.
Table 13. Auxiliary LED dimming table
(1)
AUXI (hex) 0123456789ABCDEF
AUX LED
current [mA]
1. 20 mA output current is achievable only if the supply voltage is higher than 3.3 V.
Table 14. Torch mode and flash mode dimming registers settings
T_DIM
F_DIM
current
Internal
V
Sense
Resist.
0 1 2 3 4 5 6 7 8 9 A B C D E F
(hex)
(hex)
LED
16 19 23 27 32 39 46 55 65 77 92 109 124 147 175 209 248 296 352 418 498 592 705 840
[mA]
123456789101112131415161718192021222324
step
REF1
33 40 47 56 67 80 95 113 134 160 190 227 33 40 47 56 67 79 95 113 134 160 190 227
[mV]
R
+
R
Note: LED current values refer to R
0.0 1.3 2.6 4.0 5.3 6.6 8.0 9.3 10.6 12.0 13.3 14.6 16.0 17.3 18.6 20.0
0 1 2 3 4 5 6 7 8 9 A B C D E F
R
R
R
R
R
R
R
R
R
R
FL
FL
FL
FL
FL
FL
FL
FL
FL
+
+
+
+
+
+
R
R
R
R
TR
TR
TR
TR
R
TR
TR
+
R
R
TR
TR
FL
+
+
R
R
TR
TR
= 0.27 Ω, R
FL
R
FL
FL
+
+
R
TR
RFLRFLRFLRFLRFLRFLRFLRFLRFLRFLRFLR
R
TR
= 1.8 Ω.
TR
FL
22/35 Doc ID 13169 Rev 7
STCF03 Description of internal registers
Table 15. Status register
STAT_REG
(read mode)
SUB ADD=03 N/A F_RUN LED_F NTC_W NTC_H OT_F N/A VOUTOK_N
Power ON,
SHUTDOWN MODE
RESET Value
MSB LSB
0000000 0
8.10 F_RUN
This bit is kept HIGH by the STCF03 during flash mode. By checking this bit, the
microprocessor can verify if the flash mode is running or has been terminated by the time
counter.
8.11 LED_F
This bit is set by the STCF03 when the voltage seen on the LED pin is V
a torch or flash operation. This condition can be caused by an open LED, indicating a LED
failure. The device automatically goes into ready mode to avoid damage. Internal high
frequency filtering avoids false detections. This bit is reset by the STCF03 following a read
operation of the STAT_REG.
8.12 NTC_W
This bit is set HIGH by the STCF03 and the ATN pin is pulled down, when the voltage seen
on the pin R
value at the LED measured by the NTC. The device is still operating, but a warning is sent to
the microprocessor. This bit is reset by the STCF03 following a read operation of the
STAT_REG.
8.13 NTC_H
This bit is set HIGH by the STCF03 and the ATN pin is pulled down, when the voltage seen
on the pin R
value at the LED measured by the NTC. The device is put in Ready mode to avoid damaging
the LED. This bit is reset by the STCF03 following a read operation of the STAT_REG.
8.14 OT_F
exceeds V
X
exceeds V
X
> 5.3 V during
REF2
= 0.56 V. This threshold corresponds to a warning temperature
REF4
. This threshold (1.2V) corresponds to an excess temperature
REF5
This bit is set HIGH by the STCF03 and the ATN pin is pulled down, when the chip overtemperature protection (~140 °C) has put the device in ready mode. This bit is reset by the
STCF03 following a read operation of the STAT_REG.
Doc ID 13169 Rev 7 23/35
Description of internal registers STCF03
8.15 VOUTOK_N
This bit is set by the STCF03. It is used to protect the device, if the output is shorted. The
VOUTOK_N bit is set to HIGH at the start-up. Then a current generator of 20 mA charges
the output capacitor for 360 µs typ. and it detects when the output capacitor reaches 100
mV. If this threshold is reached the bit is set to LOW. If the output is shorted to ground or the
LED is shorted this threshold is never reached: the bit stays HIGH, ATN pin is pulled down
and the device will not start. This bit is reset following a read operation of the STAT_REG.
Figure 14. VOUTOK_N behavior
Table 16. Status register details
Bit Name
Default value 00 0 0 0 0
Latched
Ready mode
when set
Sets ATN
LOW when
1. YES means that the bit is set by internal signals and is reset to default by an I²C read operation of STAT_REG NO means
that the bit is set and reset by internal signals in real-time.
(1)
Forces
set
F_RUN
(STAT_REG)
NO YES YES YES YES YES
NO YES NO YES YES YES
NO YES YES YES YES YES
LED_F
(STAT_REG)
NTC_W
(STAT_REG)
NTC_H
(STAT_REG)
OT_F
(STAT_REG)
VOUTOK_ N
(STAT_REG)
24/35 Doc ID 13169 Rev 7
STCF03 Detailed description
9 Detailed description
9.1 PowerON reset
This mode is initiated by applying a supply voltage above the V
value. An internal timing (~1 µs) defines the duration of this status. The logic blocks are
powered, but the device doesn't respond to any input. The registers are reset to their default
values, the ATN and SDA pins are in high-Z, and the I²C slave address is internally set by
reading the ADD pin configuration. After the internally defined time has elapsed, the
STCF03 automatically enters the Stand-by mode.
9.2 Shutdown, shutdown with NTC
In this mode only the I²C interface is alive, accepting I²C commands and register settings.
The device enters this mode: automatically from Power ON reset status; by resetting the
PWR_ON bit from other operation modes. Power consumption is at the minimum (1 µA max)
if NTC is not activated (NTC_ON=0). If PWR_ON and NTC_ON is set, the T1 is switched
ON (see the block diagram), allowing the microprocessor to measure the LED temperature
through its A/D converter. When NTC circuits are active and the V
typ. current consumption is increased to 1 µA, then it is recommended not to leave the
STCF03 in this status if battery drain has to be minimized.
9.3 Ready mode
In this mode all internal blocks are turned ON, but the DC-DC converter is disabled and the
White LED is disconnected. The NTC circuit can be activated to monitor the temperature of
the LED and I²C commands and register settings are allowed to be executed immediately.
Only in this mode the auxiliary LED is operational and can be turned ON and set at the
desired brightness using the AUX REGISTER. The device enters this mode: from Stand-by
by setting the PWR_ON bit; from flash operation by resetting the TRIG pin or the TRIG_EN
bit or automatically from flash operation when the time counter reaches zero; from torch
operation by resetting the TCH_ON bit. The device automatically enters this mode also
when an overload or an abnormal condition has been detected during flash or torch
operation (Table 16: Status register details:).
PW_ON RESET
REF-EXT
is present, the
threshold
9.4 Single or multiple Flash using external (microprocessor)
temporization
To avoid the I²C bus time latency, it is recommended to use the dedicated TRIG pin to define
the flash duration (hard-triggering). The TRIG_EN bit of CMD_REG should be set before
starting each flash operation, because it could have been reset automatically in the previous
flash operation. Flash duration is determined by the pulse length that drives the TRIG pin.
As soon as the flash is activated, the system needs typically 1.2 ms to ramp up the output
current on the power LED. The internal time counter will time-out flash operation and keep
the LED dissipated energy within safe limits in case of software deadlock; FTIM register has
to be set first, either in stand-by or in ready mode. Multiple flashes are possible by strobing
the TRIG pin. Time out counter will cumulate every flash on-time until the defined time out is
reached unless it is reloaded by updating the CMD_REG. If single or multiple flash
operation is timed-out, the device automatically goes in Ready mode by resetting the
Doc ID 13169 Rev 7 25/35
Detailed description STCF03
TRIG_EN bit, and also resets the F_RUN bit. The ATN pin is pulled down to inform the
microprocessor that the STAT_REG has been updated.
9.5 External (microprocessor) temporization using TRIG_EN bit
Even if it is possible, it is not recommended to use the TRIG_EN bit to start and stop the
flash operation, because of I²C bus latencies: this would result in inaccurate flash timing.
Nevertheless, if this operation mode is chosen, the TRIG pin has to be kept High (logic level
or wired to V
the time counter will time-out flash operation and keep the LED dissipated energy dissipated
by the LED within safe limits in case of SW deadlock.
), leaving the whole flash control to the I²C bus. Also in this operation mode
BAT
9.6 Single Flash using internal temporization
Flash triggering can be obtained either by TRIG pin (hard-triggering) or by I²C commands
(soft-triggering). The first solution is recommended for an accurate start time, while the
second is less accurate because of the I²C bus time latency. Stop time is defined by the
STCF03 internal temporization and its accuracy is determined by the internal oscillator. For
hard-triggering it is necessary to set the TRIG_EN bit in advance. For soft-triggering the
TRIG pin has to be kept High (logic level or wired to V
setting the FTIM and the TRIG_EN through I²C (both are located in the CMD REG). There is
a delay time between the moment the flash is triggered and when it appears. This delay is
caused by the time necessary to charge up the output capacitor, which is around 1.2 ms
depending on battery voltage and output current value. Once triggered, the flash operation
will be stopped when the time counter reaches zero. As soon as the flash is finished, the
F_RUN bit is reset, the ATN pin is pulled down for 11 µs to inform the microprocessor that
the STAT_REG has been updated and the device goes back to ready mode. If it is
necessary to make a flash longer than the internal timer allows or a continuous flash, then
the FTIM must be reloaded through I²C bus every time, before the internal timer reaches
zero. For example: To get a continuous flash, set FTIM to 1.5 s and every 1 s reload the
CMD_REG.
) and the flash can be started by
BAT
9.7 Multiple Flash using internal temporization
This operation has to be processed as a sequence of single flashes using internal
temporization starting from hard or soft triggering. Since the TRIG_EN bit is reset at the end
of each flash, it is necessary to reload the CMD_REG to start the next one.
26/35 Doc ID 13169 Rev 7
STCF03 Typical performance characteristics
10 Typical performance characteristics
Figure 15. Efficiency Figure 16. I
Efficiency of the application at I o=800mA
Efficiency of the application at I o=800mA
Efficiency of the application at Io=55mA
100
100
90
90
80
80
70
70
60
60
50
50
eff [%]
eff [%]
40
40
30
30
20
20
10
10
0
0
2 2.5 3 3.5 4 4.5 5 5.5 6
2 2.5 3 3.5 4 4.5 5 5.5 6
Figure 17. I
900
900
800
800
700
700
600
600
500
500
mA
mA
400
400
300
300
200
200
100
100
0
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Efficiency of the application at Io=55mA
OFLASH
vs. F_DIMM Figure 18. I
V
V
[V]
[V]
I
I
VI3.3V
VI3.3V
VI5.5V
VI5.5V
step
step
250
250
200
200
150
150
mA
mA
100
100
50
50
0
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
25
25
20
20
15
15
mA
mA
10
10
5
5
0
0
12345678910111213141516
12345678910111213141516
OTORCH
vs. AUXI
OAUX
vs. T_DIMM
VI= 2.7V
VI= 2.7V
VI= 3.6V
VI= 3.6V
VI=5.5V
VI=5.5V
step
step
Step
Step
Figure 19. I
900
900
800
800
700
700
600
600
500
500
mA
mA
400
400
300
300
200
200
100
100
0
0
OFLASH
-40°C 25°C 80°C
-40°C 25°C 80°C
vs. temp. VI = 3.3V Figure 20. VFB2 vs. temp. at IO = 800mA,
temp.
temp.
Doc ID 13169 Rev 7 27/35
mV
mV
260
260
240
240
220
220
200
200
180
180
160
160
140
140
120
120
100
100
V
= 3.3V
I
-40°C 25°C 80°C
-40°C 25°C 80°C
temp.
temp.
Typical performance characteristics STCF03
Figure 21. IQ vs. temp. VI = 5.5 V ready-mode Figure 22. Start-up in flash mode 800 mA at
V
= 3.6 V
3
3
2.5
2.5
2
2
1.5
1.5
mA
mA
1
1
0.5
0.5
0
0
-40°C 25°C 85°C
-40°C 25°C 85°C
Temp.
Temp.
TRIG
I
Io
I_IN
Figure 23. Line transient in flash mode
800 mA, change of V
3.3 V in 10 µs
Io
from 2.7 V to
I
VI
I_IN
28/35 Doc ID 13169 Rev 7
STCF03 Package mechanical data
11 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
Table 17. QFN20 (4 x 4 mm.) mechanical data
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Dim.
Min. Typ. Max.
A 0.80 0.90 1.00
A1 0.02 0.05
b 0.18 0.25 0.30
D 3.85 4.00 4.15
D2 2.55 2.70 2.80
E 3.85 4.00 4.15
E2 2.55 2.70 2.80
e 0.45 0.50 0.55
L 0.30 0.40 0.50
mm.
ddd 0.08
Doc ID 13169 Rev 7 29/35
Package mechanical data STCF03
Figure 24. QFN20 (4 x 4 mm.) drawing
30/35 Doc ID 13169 Rev 7
7169619_F
STCF03 Package mechanical data
TFBGA25 mechanical data
mm. mils.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 1.0 1.1 1.16 39.4 43.3 45.7
A1 0.25 9.8
A2 0.78 0.86 30.7 33.9
b 0.25 0.300.35 9.8 11.8 13.8
D2.93.0 3.1 114.2 118.1 122.0
D1 2 78.8
E2.93.0 3.1 114.2 118.1 122.0
E1 2 78.8
e0.5 19.7
SE 0.25 9.8
7539979/A
Doc ID 13169 Rev 7 31/35
Package mechanical data STCF03
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 99 101 3.898 3.976
T 14.4 0.567
Ao 4.35 0.171
Bo 4.35 0.171
Ko 1.1 0.043
Po 4 0.157
P 8 0.315
32/35 Doc ID 13169 Rev 7
STCF03 Package mechanical data
Tape & reel TFBGA25 mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N60 2.362
T 14.4 0.567
Ao 3.3 0.130
Bo 3.3 0.130
Ko 1.60 0.063
Po 3.9 4.1 0.153 0.161
P7.98.1 0.311 0.319
Doc ID 13169 Rev 7 33/35
Revision history STCF03
12 Revision history
Table 18. Document revision history
30-Jan-2007 1 First release.
27-Mar-2007 2 The OVP min. value on table 5 is changed: 5.5 V ==> 5.3 V.
28-Aug-2007 3 Modified Ta b l e 5 .
12-Sep-2007 4 Modified Figure 2.
10-Sep-2008 5 Added Figure 4 on page 14.
24-Aug-2010 6 Updated mechanical data.
23-Feb-2011 7 Updated mechanical data Table 17 on page 29 and Figure 24 on page 30.
Date Revision Changes
34/35 Doc ID 13169 Rev 7
STCF03
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