ST STB25NM50N-1, STF25NM50N, STP25NM50N, STW25NM50N, STB25NM50N User Manual
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查询STB25NM50N供应商
STP25NM50N - STF25NM50N
STB25N M50N/-1 - STW25NM50N
N-CH A NNEL 500V 0.11 Ω - 22 A TO-220/FP/D²/I²PAK/TO-247
SECOND GENERATION MDmesh™ MOSFET
Table 1: Gener al Featur es
TYPE V
STB25NM50N-1
STF25NM50N
STP25NM50N
STW25NM50N
STB25NM50N
■ HIGH dv/dt AND AVALANCHE CAPABILITIES
■ 100% AVALANCHE TESTED
■ LOW INPUT CAPACITANCE AND GATE
DSS
(@Tj
550V
550V
550V
550V
550V
MAX
) I
22 A(*)
D
22 A
22 A
22 A
22 A
R
DS(on)
0.140 Ω
0.140 Ω
0.140 Ω
0.140 Ω
0.140 Ω
CHARGE
■ LOW GATE INPUT RESISTANCE
DESCRIPTION
The STx25NM50N is realized with the second
generation of MDmesh Techno logy. This revolu
tionary MOSFET associates a new vertical structure to the Comp any's strip layout to yield one of
the world's lowest on-resistance and gate charge.
It is therefore suitable for the most demanding high
efficiency converters
APPLICATIONS
The MDmesh™ II family is very suitable for increasing power density of high voltage converters
allowing system miniaturization and higher effi
ciencies.
Figure 1: Package
2
TO-220
1
I²PAK
D²PAK
2
TO-247
TO-220FP
Figure 2: Internal Schematic Diagram
2
1
2
Table 2: Order Codes
SALES TYPE MARKING PACKAGE PACKAGING
STP25NM50N P25NM50N TO-220 TUBE
STF25NM50N F25NM50N TO-220FP TUBE
STB25NM50N-1 B25NM50N I²PAK TUBE
STW25NM50N W25NM50N TO-247 TUBE
STB25NM50N B25NM50N D²PAK TAPE & REEL
Rev. 9
1/16October 2005
STP25NM50N - STF25NM50N - STB25NM 50N/-1 - STW25NM50N
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
TO-220/D²PAK/I²PAK/
TO-247
V
DS
V
DGR
V
GS
I
D
I
D
IDM ()
P
TOT
Drain-source Voltage (VGS = 0) 500 V
Drain-gate Voltage (RGS = 20 kΩ) 500 V
Gate- source Voltage ±25 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
22 22(*) A
14 14 (*) A
Drain Current (pulsed) 88 88 (*) A
Total Dissipation at TC = 25°C
160 40 W
Derating Factor 1.28 0.32 W/°C
dv/dt(1) Peak Diode Recovery voltage slope 15 V/ns
T
stg
T
Storage Temperature –55 to 150 °C
Max. Operating Junction Temperature 150 °C
j
() Pulse width l i mited by safe operating area
(1) ISD ≤ 22 A, di/dt ≤ 400 A /µs, VDD =80% V
(*) Limited only by maximum temperature allowed
(BR)DSS
.
Table 4: Thermal Data
TO-220/D²PAK/I²PAK/
TO-247
Rthj-case Thermal Resistance Junction-case Max 0.78 3.1 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
Maximum Lead Temperature For Soldering
l
Purpose
300 °C
TO-220FP
TO-220FP
Table 5: Avalanche Characteristics
Symbol Parameter Max Value Unit
I
AS
Avalanche Current, Repetitive or Not-Repetitive
10 A
(pulse width limited by Tj max)
E
AS
Single Pulse Avalanche Energy
350 mJ
(starting Tj = 25 °C, ID = IAS, VDD = 50 V)
2/16
STB25NM50N/-1 - STW25NM50N - STP25NM50N - STF25NM50N
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 6: On/Off
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
V
(BR)DSS
Drain-source
ID = 1mA, VGS = 0 500 V
Breakdown Voltage
dv/dt(2) Drain Source Voltage
Slope
I
DSS
Zero Gate Voltage
Drain Current (VGS = 0)
I
GSS
Gate-body Leaka ge
Vdd=400V, Id=25A,
44 V/ns
Vgs=10V
VDS = Max Rating
VDS = Max Rating,
TC = 125 °C
1
10
VGS = ± 20V 100 nA
Current (VDS = 0)
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
VDS = VGS, ID = 250 µA
2 3 4 V
VGS = 10V, ID = 11 A 0.110 0.140 Ω
Resistance
(2) Cha rac teristic val ue at turn off on in ductive load
Table 7: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
(1) Forward Transconductance VDS=15 V, ID =11 A
fs
C
oss eq.
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(*) Equivalent Outpu t
VDS = 25V, f = 1 MHz, VGS = 0 2565
VGS = 0V, VDS = 0V to 400V 315 pF
Capacitance
t
d(on)
t
d(off)
Q
Q
Q
R
t
r
t
f
g
gs
gd
g
Turn-on Delay Time
Rise Time
Off-voltageRise Time
VDD =250 V, ID = 11A
RG = 4.7Ω VGS = 10 V
(see Figure 19)
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 400V, ID =22 A,
VGS = 10V,
(see Figure 23)
Gate Input Resistance f=1MHz Gate DC Bias=0
Test Signal Level=20mV
Open Drain
19 S
511
77
23
23
75
22
84
11
35
1.6 Ω
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
Table 8: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
(1) Pulsed: Pulse durati on = 300 µs, duty cycle 1.5 %.
(*) C
oss eq.
Source-drain Current
()
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a co nstant equivalent capacit ance giving the same charging time as C
ISD = 22 A, VGS = 0
ISD = 22A, di/dt = 100 A/µs
VDD = 100 V, Tj = 25°C
(see Figure 21)
ISD = 22 A, di/dt = 100 A/µs
VDD = 100 V, Tj = 150°C
(see Figure 21)
460
6.9
30
532
8.25
31
when VDS increases from 0 to 80% V
oss
22
88
1.3 V
A
A
ns
µC
A
ns
µC
A
DS
3/16
STP25NM50N - STF25NM50N - STB25NM 50N/-1 - STW25NM50N
Figure 3: Safe Operating Area For TO-220/
I²PAK/D²PAK
Figure 4: Safe Operating Area For TO-220FP
Figure 6: Thermal Impedance TO-220/I²PAK/
D²PAK
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Safe Operating Area For TO-247
4/16
Figure 8: Thermal Impedance For TO-247
STB25NM50N/-1 - STW25NM50N - STP25NM50N - STF25NM50N
Figure 9: Output Characteristics
Figure 10: Transconductance
Figure 12: Transfer Characteristics
Figure 13: Static Drain-Source On Resistance
Figure 11: Gate Charge vs Gate-source Voltage
Figure 14: Capacitance Variations
5/16
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