ST STB20NK50Z, STB20NK50Z-S, STP20NK50Z, STW20NK50Z User Manual
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STP20NK50Z - STW20NK50Z
STB20NK50Z - STB20NK50Z-S
N-CHANNEL 500V -0.23Ω- 17A TO-220/D2PAK/I2SPAK/TO-247
Zener-Protected SuperMESH™ MOSFET
TYPE V
STB20NK50Z
STB20NK50Z-S
STP20NK50Z
STW20NK50Z
■ TYPICAL R
■ EXTREMELY HIGHdv/dt CAPABILITY
■ 100% AVALANCHE TESTEDGATE CHARGE
500 V
500 V
500 V
500 V
(on) = 0.23 Ω
DS
DSS
R
DS(on)
<0.27Ω
<0.27Ω
<0.27Ω
<0.27Ω
I
D
17 A
17 A
17 A
17 A
Pw
190 W
190 W
190 W
190 W
MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing
on-resistance significantly down,specialcareis taken to ensure a very good dv/dt capability for the
most dem anding applications. Such series complements ST ful l range of high voltage MOSFETs including revolutionary MDm es h™ products.
3
2
1
TO-220
I2SPAK
3
2
1
TO-247
D2PAK
INTERNAL SCHEMATIC DIAGRAM
3
2
1
3
1
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
ORDERING INFORMATION
SALES TYPE MARKING PACKAGE PACKAGING
STB20NK50ZT4 B20NK50Z
STB20NK50Z-S B20NK50Z
STP20NK50Z P20NK50Z TO-220 TUBE
STW20NK50Z W20NK50Z TO-247 TUBE
2
D
2
I
SPAK
PAK
TAPE & REEL
TUBE
1/13May 2004
STP20NK50Z - STB20NK50Z - ST W20N K 50Z - STB20NK50Z-S
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
IDM()
P
TOT
V
ESD(G-S)
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
T
j
T
stg
() Pulse width limited by safe operating area
≤17A, di/dt ≤200A/µs, VDD≤ V
(1) I
SD
(*) Limited only by m aximum temperature allowed
THERMAL DATA
Rthj-case Thermal Resistance Junction-case Max 0.66 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 50 °C/W
T
l
Drain-source Voltage (VGS=0)
Drain-gate Voltage (RGS=20kΩ)
500 V
500 V
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC=25°C
Drain Current (continuous) at TC= 100°C
17 A
10.71 A
Drain Current (pulsed) 68 A
Total Dissipation at TC=25°C
190 W
Derating Factor 1.51 W/°C
Gate source ESD(HBM-C=100 pF, R=1.5 KΩ) 6000 V
Operating Junction Temperature
Storage Temperature
(BR)DSS,Tj
≤ T
JMAX.
-55 to 150 °C
TO-220/D2PAK TO-247
Maximum Lead Temperature For Soldering Purpose 300
°C
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
=25°C, ID=IAR,VDD=50V)
j
17 A
850 mJ
GATE-SOURCE ZENER DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain) 30 V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make t hem s afely absorb pos sible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to prote ct the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/13
STP20NK50Z - STB20NK50Z - STW20NK50Z - STB20NK50Z-S
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS O THERWISE SPECIFIED)
CASE
ON/OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
ID=1mA,VGS= 0 500 V
Breakdown Voltage
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Zero Gate Voltage
Drain Current (V
GS
=0)
Gate-body Leakage
Current (V
DS
=0)
Gate Threshold Voltage
Static Drain-source On
V
=MaxRating
DS
=MaxRating,TC= 125 °C
V
DS
V
= ± 20 V ±10 µA
GS
V
DS=VGS,ID
= 100 µA
3 3.75 4.5 V
1
50
VGS=10V,ID= 8.5 A 0.23 0.27 Ω
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
(1) Forward Transconductance VDS=15V,ID=8.5A 13 S
fs
C
oss eq.
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3) Equivalent Output
=25V,f=1MHz,VGS= 0 2600
V
DS
328
72
VGS=0V,VDS= 0V to 640V 187 pF
Capacitance
SWITCHING ON/OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
Q
Q
Q
t
r
t
f
g
gs
gd
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
=250V,ID=8.5A
V
DD
RG=4.7Ω , VGS=10V
(Resistive Load see, Figure 3)
=400V,ID=17A,
V
DD
V
=10V
GS
28
20
70
15
85
15.5
42
119
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
Source-drain Current
(2)
Source-drain Current (pulsed)
(1)
ForwardOnVoltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
oss eq.
.
V
DSS
ISD=17A,VGS=0
I
SD
V
R
(see test circuit, Figure 5)
I
SD
V
R
(see test circuit, Figure 5)
=17A,di/dt=100A/µs
= 100 V, Tj=25°C
=17A,di/dt=100A/µs
= 100 V, Tj=150°C
355
3.90
22
440
5.72
26
when VDSincreases from 0 to 80%
oss
17
68
1.6 V
A
A
ns
µC
A
ns
µC
A
3/13
STP20NK50Z - STB20NK50Z - ST W20N K 50Z - STB20NK50Z-S
Safe Operating A rea for TO-220 / D2PAK/ I2SPAK Thermal Impedance fo r TO -220 / D2PAK/I2SPAK
Thermal Impedance for TO-247Safe Operating Area for TO-247
Output Characteristics
4/13
Transfer Characteristics
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