ST STP16NK65Z, STB16NK65Z-S User Manual

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N-CHANNEL 650V - 0.38Ω - 13A TO-220 / I2SPAK

STP16NK65Z

STB16NK65Z-S

Zener - Protected SuperMESH™ MOSFET

Table 1: Ge neral Features

TYPE V

STP16NK65Z
STB16NK65Z-S

■ TYPICAL R

■ EXTREMELY HIGH dv/d t C APABILITY

■ 100% AVALANCHE TESTED

■ GATE CHARGE MINIMIZED

■ VERY LOW INTRINSIC CAPACITANCES

■ VERY GOOD MANUFACTURING

DSS

650 V
650 V

(on) = 0.38Ω

DS

R

DS(on)

< 0.50 Ω
< 0.50 Ω

I

D

13 A
13 A

Pw

190 W
190 W

REPEATIBILITY

DESCRIPTION

The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significant ly down , spe cial
care is taken to ensure a very good dv/dt capabil­ity for the most demanding applications. Such se­ries complements ST full range of high voltage
MOSFETs including revolutionary MDmesh™
products.

APPLICATIONS

■ HIGH CURRENT, HIGH SPEED SWITCHING

■ IDEAL FOR OFF-L INE POWER SUPPL IES

Figure 1: Package

3

2

1

TO-220

I²SPAK

Figure 2: Internal Schematic Diagram

3

2

1

Table 2: Order Codes

SALES TYPE MARKING PACKAGE PACKAGING

STP16NK65Z P16NK65Z TO-220 TUBE

STB16NK65Z-S B16NK65Z I²SPAK TUBE

Rev. 3

1/12September 2005

STP16NK65Z - STB16NK65Z-S

Table 3: Absolute Maximum ratings

Symbol Parameter Value Unit

V

DS

V

DGR

V

GS

I

D

I

D

I

DM

P

TOT

V

ESD(G-S)

dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns

T

j

T

stg

(*) Pulse width limited by safe operating area

≤ 13 A, di/dt ≤ 20 0 A/µs, VDD ≤ V

(1) I

SD

Table 4: Thermal Data

Rthj-case Thermal Resistance Junction-case Max 0.66 °C/W

Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W

T

l

Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)

650 V

650 V
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C

(*)

Drain Current (pulsed) 52 A

13

8.19 A

Total Dissipation at TC = 25°C 190
Derating Factor 1.51 W/°C
Gate source EDS (HBM-C=10 0pF, R=1.5kΩ) 6000 V

Operating Junction Temperature
Storage Temperature

(BR)DSS,Tj

≤ T

JMAX

-55 to 150 °C

Maximum Lead Temperature For Soldering Purpose 300 °C

A

W

Table 5: Avalanche Characteristics

Symbol Parameter Max. Value Unit

I

AR

E

AS

Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T

max)

j

Single Pulse Avalanche Energy
(starting T

= 25 °C, ID = IAR, VDD = 50 V)

j

13 A

350 mJ

Table 6: Gate-Source Zener Diode

Symbol Parameter Test Condition Min. Typ. Max. Unit

BV

GSO

Gate-Source Breakdown

Igs=± 1mA (Open Drain) 30 V

Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have s pecifically bee n des igned to enha nce not on ly the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied fromgate to source. In this respect the Zener voltage ia a ppropriate to achie ve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus av oid the
usage of external components.

2/12

STP16NK65Z - STB16NK65Z-S

ELECTRICAL CHARACTERISTICS (T

=25°C UNLESS OTHERWISE SPECIFIED)

CASE

Table 7: On/Off

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

(BR)DSS

Drain-source

ID = 1 mA, VGS = 0 650 V

Breakdown Voltage

I

DSS

I

GSS

V

GS(th)

R

DS(on)

Zero Gate Voltage
Drain Current (V

GS

= 0)

Gate-body Leaka ge
Current (V

DS

= 0)
Gate Threshold Voltage VDS = VGS, ID = 100 µA
Static Drain-source On

V

= Max Rating

DS

V

= Max Rating, TC = 125 °C

DS

V

= ± 20 V ±10 µA

GS

33.75

1

50

4.5 V

VGS = 10V, ID = 6.5 A 0.38 0.50 Ω

Resistance

Table 8: Dynamic

Symbol Parameter Test Conditions Min. Typ. Max. Unit

(1) Forward Transconductance VDS = 15 V, ID = 6.5 A 12 S

g

fs

C

oss eq.

t

t

C

iss

C

oss

C

rss

d(on)

t

d(off)

t

Q
Q
Q

r

f

g
gs
gd

Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

(*) Equivalent Outpu t

Capacitance
Turn-on Delay Time

Rise Time
Turn-off Delay Time
Fall Time

Total Gate Charge
Gate-Source Charge
Gate-Drain Charge

= 25 V, f = 1 MHz, VGS = 0 2750

V

DS

275

60

VGS = 0V, VDS = 6.5 V to 520 V 188 pF

= 325 V, ID = 6.5 A

V

DD

R

= 4.7Ω VGS = 10 V

G

(see Figure 17)

25
25
68
17

VDD = 520 V, ID = 13 A,
V

= 10 V

GS

(see Figure 20)

89
18
45

µA
µA

pF
pF
pF

ns
ns
ns
ns

nC
nC
nC

Table 9: Source Drain Diode

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

SD

I

(2)

SDM

(1)

V

SD

t

rr

Q

rr

I

RRM

t

rr

Q

rr

I

RRM

(1) Pulsed: Pulse duration = 300µs, duty cycle 1.5%
(2) Pulse width limited by safe operating area
(*) C

oss eq.

Source-drain Current
Source-drain Current (pulsed)

Forward On Voltage
Reverse Recovery Time

Reverse Recovery Charge
Reverse Recovery Current

Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current

is defined as a co nstant equi valent capac i t ance giving the same charg in g time as C

ISD = 13 A, VGS = 0

= 13 A, di/dt = 100 A/µs,

I

SD

= 100 V, Tj = 25°C

V

DD

(see Figure 18)
ISD = 13 A, di/dt = 100 A/µs,

V

= 100 V, Tj = 150°C

DD

(see Figure 18)

500

5.2
21

615

7

22.5

when VDS increases from 0 to 80% V

oss

13
52

1.6 V

A
A

ns

µC

A

ns

µC

A

DSS

3/12

STP16NK65Z - STB16NK65Z-S

Figure 3: Safe Operating Area

Figure 4: Output Characteristics

Figure 6: Thermal Impedance

Figure 7: Transfer Characteristics

Figure 5: Transconductance

4/12

Figure 8: Static Drain-source On Resistance