The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, spec ial
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Outp u t C a pacita nce
Rev er se Trans fer Capacita n ce
Equivalent Ouput Capacitance
g
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
=15V, ID = 5.25A
DS
=25V, f=1 MHz, VGS=0
V
DS
=0, V
V
GS
=640V, ID = 10.5 A
V
DD
=10V
V
GS
=0V to 640V
DS
(see Figure 17)
12S
2620
250
53
100pF
87
14
44
µA
µA
pF
pF
pF
nC
nC
nC
Table 6.Switching times
SymbolParameterTest ConditionsMin.Typ.Max.Unit
=400 V, ID=5.25 A,
V
t
d(on)
t
t
d(off)
t
t
r(Voff)
t
t
Tur n-on Delay Time
r
Rise Time
Turn-off Delay Time
f
Fall Ti me
Off-vol tage Rise Ti me
f
c
Fall Ti me
Cross-over T ime
DD
R
=4.7Ω, VGS=10V
G
(see Figure 18)
=400 V, ID=5.25A,
V
DD
R
=4.7Ω, VGS=10V
G
(see Figure 18)
=640 V, ID=10.5A,
V
DD
R
=4.7Ω, VGS=10V
G
(see Figure 18)
30
18
70
20
16
15
28
ns
ns
ns
ns
ns
ns
ns
3/15
2 Electric al characteristicsSTB12NK80Z - STP12NK80Z - STW12NK80Z
Table 7.Source drain diode
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SDM
V
SD
I
I
SD
Note 2
Note 4
t
rr
Q
rr
RRM
Source-drain Current
Source-drain Current (pulsed)
Forward on Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD=10.5 A, VGS=0
=10.5A, di/dt = 100A/µs,
I
SD
V
=100 V, Tj=150°C
DD
10.5
42
1.6V
635
5.9
18.5
Table 8.Gate-source zener diode
SymbolParameterTest ConditionsMin.Ty p.Max.Unit
BV
GSO
Note 6
(1) ISD ≤10.5 A, di/dt ≤200A/µs, VDD ≤ V
(2) Pul s e width limited by safe operat ing area
(3) Limited only by maximu m temperat ure allowed
(4) Pulsed: pulse duration = 300µs, duty cycle 1.5%
(5) C
oss eq.
to 80%V
(6)The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but
also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this
respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. Th ese integrated Z ener diodes thus avoid the usage of external components.
Gate-Source
Breakdown Voltage
is defined as a constant equivalent capacitance giving the same charging time as C
3 Test circuitsSTB12NK80Z - STP12NK80Z - STW12NK80Z
3 Test circuits
Figure 16. Switching Times Test Circuit For
Resistive Load
Figure 18. Test Circuit For Indictive Load
Switching and Diode Recovery
Times
Figure 17. Gate Charge Test Circuit
Figure 20. Unclamped Inductive Load Test
Circuit
Figure 19. Unclamped Inductive Waveform
8/15
STB12NK80Z - STP12NK80Z - STW12NK80Z4 Package mechani cal data
4 P ack age mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOP ACK specifications are
available at: www.st.com
9/15
4 Package mechani cal dataSTB12NK80Z - STP12NK80Z - STW12NK80Z
STB12NK80Z - STP12NK80Z - STW12NK80Z6 Revision History
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