PAK (TO-263)
POWER PACKAG E IN TU BE (NO SU FFIX) OR
IN TAPE & REEL (SUFFIX “T4”)
DESCRIPTION
This Power MOSFET is the latest dev elo pment of
STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a remarkable manufacturing reproducibility.
3
1
D2PAK
TO-263
(Suffix “T4”)
3
2
1
TO-220
INTERNAL SCHEMATIC DIAGRAM
1
I2PAK
TO-262
(Suffix “-1”)
3
2
APPLICATIONS
■ HIGH CURRENT, HIGH SWITCHING SPEED
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DC & DC-AC CONVERTERS
■ SOLENOID AND RELAY DRIVERS
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
DS
V
DGR
V
GS
I
(1)Drain Current (continuous) at T
D
(1)Drain Current (continuous) at T
I
D
(
I
DM
P
tot
E
AS
T
stg
T
j
(
Pulse widt h l i m i ted by safe operating area
•)
(1) Current Limited by Package
.
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
30V
30V
Gate- source Voltage± 16V
= 25°C
C
= 100°C
C
•)
Drain Current (pulsed)400A
Total Dissipation at TC = 25°C
100A
100A
300W
Derating Factor2W/°C
(2)
Single Pulse Avalanche Energy1.9J
Storage Temperature
Operating Junction Temperature
(2) Starting Tj = 25 oC, IAR = 50A, VDD = 50V
-55 to 175°C
1/11February 2003
STB100NF03L-03 STP100NF03L-03 STB100NF03L-03-1
THERMA L D ATA
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
0.5
62.5
300
°C/W
°C/W
°C
ELECTRICAL CHARACTERISTICS (T
= 25 °C unless otherwise specified)
case
OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
= 250 µA, VGS = 0
V
(BR)DSS
Drain-source
I
D
30V
Breakdown Voltage
= Max Rating
V
DS
= Max Rating TC = 125°C
V
DS
= ± 16V
V
GS
1
10
±100nA
ON
(*)
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
Resistance
= V
DS
GS
= 10 V ID = 50 A
V
GS
= 4.5 VID = 50 A
V
GS
ID = 250 µA
11.72.5V
0.0026
0.0032
0.0032
0.0045
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
(*)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS>I
D(on)xRDS(on)max ID
= 25V f = 1 MHz VGS = 0
V
DS
=10 A
10S
6200
1720
300
µA
µA
Ω
Ω
pF
pF
pF
2/11
STB100NF03L-03 STP100NF03L-03 STB100NF03L-03-1
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
= 15 VID = 50 A
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
SWITCHING OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(off)
t
t
r(Voff)
t
t
f
f
c
Turn-off Delay Time
Fall Time
Off-Voltage Rise Time
Fall Time
Cross-over Time
V
DD
= 4.7
R
Ω
G
VGS = 4.5 V
(Resistive Load, Figure 3)
= 24V ID= 100A VGS= 5V
V
DD
= 20 VID = 50 A
V
DD
= 4.7Ω, V
R
G
GS
= 4.5 V
(Resistive Load, Figure 3)
V
= 24 VID = 100 A
clamp
= 4.7
R
Ω
G
V
GS
= 4.5 V
(Inductive Load, Figure 5)
35
315
88
22.5
36
115
95
110
55
100
ns
ns
nC
nC
nC
ns
ns
ns
ns
ns
SOURCE DRAIN DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(*)
Pulsed: P ul se duration = 300 µs, duty cycle 1. 5 %.
(
•)Pulse width limited by saf e operating ar ea.
Safe Operating Area
Source-drain Current
(•)
Source-drain Current (pulsed)
(*)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
= 100 A VGS = 0
SD
= 100 Adi/dt = 100A/µs
I
SD
= 20 VTj = 150°C
V
DD
(see test circuit, Figure 5)
Thermal Impedance
100
400
1.3V
75
150
4
A
A
ns
nC
A
3/11
STB100NF03L-03 STP100NF03L-03 STB100NF03L-03-1
Output CharacteristicsTransfer Characteristics
TransconductanceStatic Drain-source On Resistance
Gate Charge vs Gate-source VoltageCapacitance Variations
4/11
STB100NF03L-03 STP100NF03L-03 STB100NF03L-03-1
Normalized Gate Threshold Voltage vs TemperatureNormalized on Resistance vs Temperature
Source-drain Diode Forward CharacteristicsNormalized Breakdown Voltage Temperature
..
5/11
STB100NF03L-03 STP100NF03L-03 STB100NF03L-03-1
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test CircuitFig. 2: Unclam ped I nduct ive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Information furnishe d is bel i eved to be accurate and reliable. However, STMicroelectroni cs assumes no responsibility for t he consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or oth erwise unde r any patent or patent rights of STMi croelectronics. Speci fications me ntioned in th i s publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as crit i cal component s i n l i f e support devices or systems wi thout expre ss written appr oval of STMicroelectronics.
The ST log o i s registered trademark of STM i croelectronics
2002 STMi croelectroni cs - All Right s Reserved
All other names are the property of their respectiv e owners.
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11/11
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