ST STA369BW User Manual
2.1-channel high-efficiency digital audio system
Features
■ Wide-range supply voltage
– 5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
■ Four power output configurations
– 2 channels of ternary PWM (stereo mode)
(2 x 30 W into 8 Ω at 22 V)
– 3 channels - left, right using binary and LFE
using ternary PWM (2.1 mode) (2 x 15 W +
1x30W into 2x4Ω, 1 x 8 Ω at 22 V)
– 2 channels of ternary PWM (2 x 30 W) +
stereo lineout ternary)
■ FFX
■ Selectable 32 to 192 kHz input sampling rates
■ I
■ Digital gain/attenuation +42 dB to -80 dB with
■ Soft-volume update with programmable ratio
■ Individual channel and master gain/attenuation
■ Two independent DRCs configurable as a
■ EQ-DRC for DRC based on filtered signals
■ Dedicated LFE processing for bass boosting
■ Audio presets:
■ Individual channel and master soft/hard mute
■ Independent channel volume and DSP bypass
■ Automatic zero-detect mute
■ Automatic invalid input-detect mute
■ I
■ Input and output channel mapping
®
100 dB SNR and dynamic range
2
C control with selectable device address
0.125 dB/step resolution
dual-band anti-clipper (B
2
DRC) or independent
limiters/compressors
with 0.125 dB/step resolution
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset nighttime listening mode
2
S input data interface
STA369BW
Sound Terminal
PowerSSO-36
with exposed pad down (EPD)
■ Up to 8 user-programmable biquads per
channel
■ 3 coefficient banks for EQ presets storing with
fast recall via I
■ Extended coefficient dynamic up to -4..4 for
easy implementation of high shelf filters
■ Bass/treble tones and de-emphasis control
■ Selectable high-pass filter for DC blocking
■ Advanced AM interference frequency
switching and noise suppression modes
■ Selectable high- or low-bandwidth
noise-shaping topologies
■ Selectable clock input ratio
■ 96 kHz internal processing sampling rate with
quantization error noise shaping for very low
cutoff frequency filters
■ Thermal overload and short-circuit protection
embedded
■ Video apps: 576 x Fs input mode supported
■ Fully compatible with STA339BW,
STA369BWS and STA350BW
Table 1. Device summary
Order code Package Packing
STA369BW Power SSO-36 Tube
STA369BWTR Power SSO-36 Tape and reel
2
C interface
®
July 2011 Doc ID 022033 Rev 1 1/88
www.st.com
1
Contents STA369BW
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 15
3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 16
4 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Mono parallel BTL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6I
2
C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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6.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.5 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.6 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.3 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.4 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.5 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.1 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.2 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.3 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.4 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2.5 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3.1 FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3.2 FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3.3 Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . 40
7.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4.1 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4.2 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4.3 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4.4 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4.5 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4.6 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 41
7.4.7 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.4.8 Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.5.1 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.5.2 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.5.3 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.5.4 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.5.5 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.5.6 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 43
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Contents STA369BW
7.5.7 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.5.8 Soft-volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.6.1 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.6.2 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6.3 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6.4 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6.5 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6.6 IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6.7 External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.7 Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 51
7.7.1 Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.7.2 Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.7.3 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.7.4 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.7.5 Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.8 Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 53
7.8.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.8.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.8.3 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.8.4 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.9 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 55
7.9.1 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.9.2 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.9.3 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.9.4 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.9.5 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.9.6 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.10 Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.10.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.11 Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 57
7.11.1 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.11.2 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.11.3 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.11.4 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.11.5 Limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 61
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7.11.6 Limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 61
7.11.7 Limiter 2 extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . . ) 62
7.11.8 Limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 62
7.12 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 62
7.12.1 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.12.2 Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.12.3 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.12.4 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.12.5 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.12.6 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.12.7 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.12.8 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.12.9 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.12.21 Overcurrent post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.13 Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 69
7.14 Variable distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . 69
7.15 Fault-detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 70
7.16 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.17 EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 71
7.18 Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 72
7.18.1 Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.18.2 EQ DRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.18.3 Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.18.4 Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.18.5 Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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Contents STA369BW
7.19 EQ soft-volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . . 75
7.20 DRC RMS filter coefficients (addr 0x39-0x3E) . . . . . . . . . . . . . . . . . . . . . 76
7.21 Extra volume resolution configuration registers (address 0x3F) . . . . . . . 77
7.22 Quantization error noise correction (address 0x48) . . . . . . . . . . . . . . . . . 78
7.23 Extended coefficient range up to -4...4 (address 0x49, 0x4A) . . . . . . . . . 79
7.24 Miscellaneous registers (address 0x4B, 0x4C) . . . . . . . . . . . . . . . . . . . . 80
7.24.1 Rate powerdown enable (RPDNEN) bit (address 0x4B, bit D7) . . . . . . 80
7.24.2 Noise-shaping on DC cut filter enable (NSHHPEN) bit (address 0x4B,
bit D6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.24.3 Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . . . 80
7.24.4 Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2) . . . . . . . . 81
7.24.5 Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,
D3, D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.1 Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.2 PLL filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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STA369BW List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12. IR bit settings as a function of input sampling rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 13. Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 16. Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 18. Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 37
Table 20. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 21. Channel input mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22. FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23. Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24. FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 25. Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 26. Overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 27. High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 28. De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 29. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 30. Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 31. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 32. Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 33. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 34. Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 35. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 36. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 37. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 38. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 39. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 40. Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 41. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 42. Soft-volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 43. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 44. Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 45. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 46. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 47. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 48. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Doc ID 022033 Rev 1 7/88
List of tables STA369BW
Table 49. IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 50. External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 51. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 52. Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 53. Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 54. Audio preset gain compression/limiters selection for AMGC[3:2] = 00. . . . . . . . . . . . . . . . 53
Table 55. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 56. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 57. Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 58. Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 59. Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 60. EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 61. Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 62. Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 63. Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 64. Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 65. Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 66. Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 67. Limiter attack threshold as a function of LxAT bits (AC-mode). . . . . . . . . . . . . . . . . . . . . . 60
Table 68. Limiter release threshold as a function of LxRT bits (AC-mode) . . . . . . . . . . . . . . . . . . . . 60
Table 69. Limiter attack threshold as a function of LxAT bits (DRC -mode). . . . . . . . . . . . . . . . . . . . 61
Table 70. Limiter release threshold as a as a function of LxRT bits (DRC-mode) . . . . . . . . . . . . . . . 61
Table 71. RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 68
Table 72. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 73. EQ RAM select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 74. Anti-clipping and DRC preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 75. Anti-clipping selection for AMGC[3:2] = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 76. Biquad filter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 77. PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 78. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8/88 Doc ID 022033 Rev 1
STA369BW List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. Demonstration board, 2.0 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Mono parallel BTL schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. THD+N vs. output power (V
Figure 7. THD+N vs. output power (V
Figure 8. Output power vs. V
Figure 9. Output power vs. V
(load = 6 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CC
(load = 8 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CC
Figure 10. Efficiency vs. output power (V
Figure 11. Efficiency vs. output power (V
Figure 12. THD+N vs. output power (V
Figure 13. Output power vs. V
(load = 3 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CC
Figure 14. Efficiency vs. output power (V
Figure 15. Efficiency vs. output power (V
Figure 16. Left and right processing - part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. Processing - part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. Write mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 20. OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21. OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22. OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23. OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24. Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 25. 2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 26. 2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 27. 2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 28. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 29. B
2
DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 30. EQDRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 31. Extra resolution volume scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 32. Biquad filter structure with quantization error noise-shaping . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 33. Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 34. Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 35. Double-layer PCB with 2 copper ground areas and 24 via holes . . . . . . . . . . . . . . . . . . . 84
Figure 36. PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 37. PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
= 25 V, load = 6 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CC
= 18 V, load = 8 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CC
= 25 V, load = 6 Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CC
= 25 V, load = 8 Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CC
= 25 V, load = 3 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CC
= 26 V, load = 3 Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CC
= 18 V, load = 3 Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CC
Doc ID 022033 Rev 1 9/88
Description STA369BW
1 Description
The STA369BW is an integrated solution of digital audio processing, digital amplifier control,
and FFX-power output stage, thereby creating a high-power single-chip FFX
®
solution
comprising high-quality, high-efficiency, and all-digital amplification.
The STA369BW is based on an FFX (fully flexible amplification) processor, a proprietary
technology from STMicroelectronics. FFX is the evolution and the enlargement of ST’s
ternary technology: the new processor can be configured to work in ternary, binary, binary
differential and phase-shift PWM modulation schemes.
The STA369BW contains the ternary, binary and binary differential implementations, a
subset of the full capability of the FFX processor.
The STA369BW is part of the Sound Terminal
®
family that provides full digital audio
streaming to the speaker, offering cost effectiveness, low power dissipation and sound
enrichment.
The STA369BW power section consists of four independent half-bridges. These can be
configured via digital control to operate in different modes. 2.1 channels can be provided by
two half-bridges and a single full-bridge, providing up to 2 x 15 W + 1 x 30 W of music output
power, by using standard 4 and 8 Ω speakers. Two channels can be provided by two fullbridges, providing up to 2 x 30 W, by using standard 8 Ω speaker at 22 V. The IC can also be
configured as 2.1 channels with 2 x 30 W provided by the device and external power for FFX
power drive. Please refer to the package thermal characteristics and application
suggestions for more details.
Also provided in the STA369BW are a full assortment of digital processing features. This
includes up to 8 programmable biquads (EQ) per channel. Special digital signal processing
techniques are available in order to manage low-frequency quantization noise in case of
very low frequency cutoff filter thresholds. The coefficient range -4..4 allows the easy
implementation of high shelf filters. Available presets allow the advantage of earlier time-tomarket by substantially reducing the amount of software development needed for certain
functions. This includes audio preset volume loudness, preset volume curves and preset EQ
settings. There are also new advanced AM radio interference reduction modes. The dualband DRC dynamically equalizes the system to provide speaker linear frequency response
regardless of output power level. This feature independently processes the two bands,
controlling dynamically the output power level in each band, thus providing better sound
clarity.
The serial audio data input interface accepts all possible formats, including the popular I
2
S
format. Three channels of FFX processing are provided. This high-quality conversion from
PCM audio to FFX PWM switching waveform provides over 100 dB SNR and dynamic
range.
10/88 Doc ID 022033 Rev 1
STA369BW Description
1.1 Block diagram
Figure 1. Block diagram
I2S
in t er face
Vo lu me
contr ol
PLL
FFX
I2C
Power
control
Protection
cur re nt/the rm al
Log ic
Regulators
Bias
PowerDigita l DSP
Channel
1A
Chann el
1B
Ch anne l
2A
Chann el
2B
AM045167v1
Doc ID 022033 Rev 1 11/88
Pin connections STA369BW
2 Pin connections
2.1 Connection diagram
Figure 2. Pin connection PowerSSO-36 (top view)
GND_SUB
SA
TEST_MODE
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A
GND_REG
VDD
CONFIG
OUT3B/FFX3B
OUT3A/FFX3A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
D05AU1638
VDD_DIG
GND_DIG
SCL
SDA
INT_LINE
RESET
SDI
LRCKI
BICKI
XTI
GND_PLL
FILTER_PLL
VDD_PLL
PWRDN
GND_DIG
VDD_DIG
TWARN/OUT4A
EAPD/OUT4B
AM045168v1
2.2 Pin description
Table 2. Pin description
Pin Type Name Description
1 GND GND_SUB Substrate ground
2I SA I
3 I TEST_MODE This pin must be connected to ground (pull-down)
4 I/O VSS Internal reference at Vcc-3.3 V
5 I/O VCC_REG Internal Vcc reference
6 O OUT2B Output half-bridge 2B
7 GND GND2 Power negative supply
8 Power VCC2 Power positive supply
9 O OUT2A Output half-bridge 2A
10 O OUT1B Output half-bridge 1B
12/88 Doc ID 022033 Rev 1
2
C select address (pull-down)
STA369BW Pin connections
Table 2. Pin description (continued)
Pin Type Name Description
11 Power VCC1 Power positive supply
12 GND GND1 Power negative supply
13 O OUT1A Output half-bridge 1A
14 GND GND_REG Internal ground reference
15 Power VDD Internal 3.3 V reference voltage
16 I CONFIG Parallel mode command
17 O OUT3B/FFX3B PWM out CH3B / external bridge driver
18 O OUT3A/FFX3A PWM out CH3A / external bridge driver
19 O EAPD/OUT4B Power-down for external bridge / PWM out CH4B
20 I/O TWARN/OUT4A
21 Power VDD_DIG Digital supply voltage
22 GND GND_DIG Digital ground
23 I PWRDN Power down (pull-up)
24 Power VDD_PLL Positive supply for PLL
Thermal warning from external bridge (pull-up when input)
/ PWM out CH4A
25 I FILTER_PLL Connection to PLL filter
26 GND GND_PLL Negative supply for PLL
27 I XTI PLL input clock
2
28 I BICKI I
29 I LRCKI I
30 I SDI I
S serial clock
2
S left/right clock
2
S serial data channels 1 and 2
31 I RESET Reset (pull-up)
32 O INT_LINE Fault interrupt
2
33 I/O SDA I
34 I SCL I
C serial data
2
C serial clock
35 GND GND_DIG Digital ground
36 Power VDD_DIG Digital supply voltage
Doc ID 022033 Rev 1 13/88
Electrical specifications STA369BW
3 Electrical specifications
3.1 Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Min Typ Max Unit
V
VDD_DIG Digital supply voltage -0.3 4 V
VDD_PLL PLL supply voltage -0.3 4
T
T
Power supply voltage (VCCxA, VCCxB) -0.3 30 V
cc
Operating junction temperature -20 150 °C
op
Storage temperature -40 150 °C
stg
Warning: Stresses beyond those listed in Tabl e 3 above may cause
permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any
other conditions beyond those indicated under
“Recommended operating conditions” are not implied.
Exposure to AMR conditions for extended periods may affect
device reliability. In the real application, power supplies with
nominal values rated within the recommended operating
conditions, may rise beyond the maximum operating
conditions for a short time when no or very low current is
sunk (amplifier in mute state). In this case the reliability of the
device is guaranteed, provided that the absolute maximum
ratings are not exceeded.
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Min Typ Max Unit
R
th j-case
T
th-sdj
T
th-w
T
th-sdh
R
th j-amb
1. See Section 9: Package thermal characteristics on page 84 for details.
14/88 Doc ID 022033 Rev 1
Thermal resistance junction-case (thermal pad) 1.5 °C/W
Thermal shutdown junction temperature 150 °C
Thermal warning temperature 130 °C
Thermal shutdown hysteresis 20 °C
Thermal resistance junction-ambient
(1)
STA369BW Electrical specifications
3.3 Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter Min Typ Max Unit
V
Power supply voltage (VCCxA, VCCxB) 5 26 V
cc
VDD_DIG Digital supply voltage 2.7 3.3 3.6 V
VDD_PLL PLL supply voltage 2.7 3.3 3.6 V
Ambient temperature -20 +85 °C
T
amb
3.4 Electrical specifications for the digital section
Table 6. Electrical specifications - digital section
Symbol Parameter Conditions Min Typ Max Unit
Low-level input current without
I
il
pull-up/down device
I
V
V
V
V
I
R
High-level input current without
ih
pull-up/down device
Low-level input voltage
il
High-level input voltage
ih
Low-level output voltage Iol=2 mA
ol
High-level output voltage Ioh=2 mA
oh
Pull-up/down current 25 66 125 µA
pu
Equivalent pull-up/down
pu
resistance
Vi = 0 V 1 5 µA
Vi = VDD_DIG
= 3.6 V
0.8 *
VDD_DIG
0.8 *
VDD_DIG
15µA
0.2 *
VDD_DIG
V
V
0.4 *
VDD_DIG
V
V
50 kΩ
Doc ID 022033 Rev 1 15/88
Electrical specifications STA369BW
3.5 Electrical specifications for the power section
The specifications given in this section are valid for the operating conditions: VCC=22V,
f=1kHz, f
Table 7. Electrical specifications - power section
Symbol Parameter Conditions Min Typ Max Unit
= 384 kHz, T
sw
= 25° C and RL = 8 Ω, unless otherwise specified.
amb
Continuous output power, BTL, ternary
mode
THD = 1% 20
THD = 10% 30
Po
THD = 1% 12
THD = 10% 15
l
= 1.5 A 180 250 mΩ
d
R
dsON
Continuous output power SE, binary
RL = 4 Ω
mode,
Power Pchannel/Nchannel MOSFET (total
bridge)
Idss Power Pchannel/Nchannel leakage VCC = 20 V 10 μA
I
LDT
I
HDT
V
Low current dead time (static) Resistive load
High current dead time (dynamic) I load
Rise time Resistive load
t
r
Fall time Resistive load
t
f
Supply voltage operating voltage 5 26 V
cc
(1)
(1)
8 15 ns
= 1.5 A 15 30 ns
(1)
(1)
10 18 ns
10 18 ns
Supply current from Vcc in power-down PWRDN = 0 1 μA
PCM input signal
I
vcc
Supply current from Vcc in operation
= -60 dBfs,
Switching frequency
52 60 mA
= 384 kHz,
No LC filters
I
vdd
Supply current FFX processing (reference
only)
Ilim Overcurrent limit
Internal clock =
49.152 MHz
(2)
55 70 mA
2.6 2.8 A
W
W
Isc Short-circuit protection Hi-Z output 3.1 3.3 A
UVL Undervoltage protection 4.3 V
OVP Overvoltage protection 29 V
t
min
Output minimum pulse width No load 100 ns
DR Dynamic range 100 dB
Signal-to-noise ratio, ternary mode A-Weighted 100 dB
SNR
Signal-to-noise ratio binary mode 90 dB
FFX stereo mode,
THD+N Total harmonic distortion + noise
Po = 1 W
0.09 %
f=1kHz
16/88 Doc ID 022033 Rev 1
STA369BW Electrical specifications
Table 7. Electrical specifications - power section (continued)
Symbol Parameter Conditions Min Typ Max Unit
FFX stereo mode,
<5 kHz
X
TA L K
Crosstalk
PSRR Power Supply Rejection Ratio
Peak efficiency, FFX mode
η
Peak efficiency, binary modes
1. Refer to Figure 3: Test circuit.
2. Limit current if the register (OCRB Section 7.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled
refer to the Isc.
One channel driven
at 1 W
Other channel
measured
FFX stereo mode,
<5 kHz
VRipple01V RMS
Audio input = dither
only
Po = 2 x 25 W
into 8 Ω
Po = 2 x 10W into 4Ω
+ 1 x 20W into 8 Ω
80 dB
80 dB
90
%
86
Figure 3. Test circuit
Doc ID 022033 Rev 1 17/88
Characterization curves STA369BW
4 Characterization curves
The following characterization curves were made using the STA369BW demonstration
board with 2.0 channels (refer to the schematic in Figure 6) under the following test
conditions:
V
= 22 V, f = 1 kHz, fSW = 384 kHz, Tamb = 25 °C and RL = 8 Ω, unless otherwise
CC
specified.
Figure 4. Demonstration board, 2.0 channels
18/88 Doc ID 022033 Rev 1
AM045290v1
STA369BW Characterization curves
Figure 5. Mono parallel BTL schematic
AM045170v1
Doc ID 022033 Rev 1 19/88
Characterization curves STA369BW
Figure 6. THD+N vs. output power (VCC = 25 V, load = 6 Ω)
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
1m 1002m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50
Figure 7. THD+N vs. output power (V
10
5
Vcc=25V , Load = 6Ω,
Freq= 1KHz
W
= 18 V, load = 8 Ω)
CC
AM045171v1
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
1m 502m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10 20
Vcc=18V , Load = 8Ω,
Freq= 1KHz
W
AM045172v1
20/88 Doc ID 022033 Rev 1
STA369BW Characterization curves
Figure 8. Output power vs. V
60
55
50
45
40
35
W
30
25
20
15
10
5
+6 +26+8 +10 +12 +14 +16 +18 +20 +22 +24
Load= 6 Ω,
Freq=1KHz
Figure 9. Output power vs. V
(load = 6 Ω)
CC
(load = 8 Ω)
CC
THD = 10%
Vdc
THD = 1%
AM045173v1
50
45
40
Load= 8 Ω,
Freq=1KHz
35
30
W
25
20
15
THD = 10%
THD = 1%
10
5
+6 +26+8 +10 +12 +14 +16 +18 +20 +22 +24
Vdc
AM045174v1
Doc ID 022033 Rev 1 21/88
Characterization curves STA369BW
Figure 10. Efficiency vs. output power (VCC = 25 V, load = 6 Ω)
+1
+0.9
+0.8
+0.7
+0.6
η %
+0.5
+0.4
Vcc= 25V,
Load= 6 Ω,
Freq=1KHz
+0.3
+0.2
+0.1
+0
5 5510 15 20 25 30 35 40 45 50
Figure 11. Efficiency vs. output power (V
+1
+0.9
+0.8
+0.7
+0.6
η %
+0.5
+0.4
Vcc= 25V,
Load= 8 Ω,
Freq=1KHz
+0.3
+0.2
+0.1
+0
5 4510 15 20 25 30 35 40
W
= 25 V, load = 8 Ω)
CC
W
AM045175v1
AM045176v1
22/88 Doc ID 022033 Rev 1
STA369BW Characterization curves
4.1 Mono parallel BTL characteristics
Figure 12. THD+N vs. output power (VCC = 25 V, load = 3 Ω)
10
5
2
Vcc=25V
Load= 3 Ω,
1
0.5
%
0.2
0.1
0.05
0.02
0.01
1m 1002m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50
Figure 13. Output power vs. V
110
100
90
80
Load= 3 Ω,
Freq=1KHz
(load = 3 Ω)
CC
Freq=1KHz
W
THD=10%
AM045177v1
70
60
W
50
40
30
20
10
+6 +26+8 +10 +12 +14 +16 +18 +20 +22 +24
Vdc
THD=1%
AM045178v1
Doc ID 022033 Rev 1 23/88
Characterization curves STA369BW
Figure 14. Efficiency vs. output power (VCC = 26 V, load = 3 Ω)
+1
+0.9
+0.8
+0.7
+0.6
+0.5
η %
+0.4
+0.3
Vcc= 26V
Load= 3 Ω,
Freq=1KHz
+0.2
+0.1
+0
10 11020 30 40 50 60 70 80 90 100
Figure 15. Efficiency vs. output power (V
+1
+0.9
+0.8
+0.7
+0.6
+0.5
η %
+0.4
+0.3
Vcc=18V
Load= 3 Ω,
Freq=1KHz
+0.2
+0.1
+0
5 5010 15 20 25 30 35 40 45
W
= 18 V, load = 3 Ω)
CC
W
AM045179v1
AM045180v1
24/88 Doc ID 022033 Rev 1
STA369BW Processing data paths
5 Processing data paths
Figure 16 and 17 illustrate the data processing paths inside the STA369BW.
The whole processing chain is composed of two consecutive sections. In the first one, dualchannel processing is implemented, as described below, and then each channel is fed into
the post-mixing block allowing to generate either a third channel (typically used in 2.1 output
configuration and with crossover filters enabled) or to have the channels processed by the
dual-band DRC block (2.0 output configuration with crossover filters used to define the cutoff
frequency of the two bands).
The first section begins with a 2x oversampling FIR filter allowing for 2*Fs audio processing.
Then a selectable high-pass filter removes the DC level (enabled if HFB=0).
The channel 1 and 2 processing chain can include up to 8 filters, depending on the selected
configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]).
By default 4 independent filters per channel are enabled, plus the pre-configured DeEmphasis, Bass and Treble controls (BQL=0, BQ5=0, BQ6=0, BQ7=0).
If the coefficient sets are linked (BQL=1) it’s then possible to use De-Emphasis, Bass and
Treble filters in a user-defined configuration (provided the relevant BQx bits are set). In other
words, both channels will use the same processing coefficients and can have up to 7 filters
each. Note that if BQL=0 the BQx bits are ignored and the 5th, 6th and 7th filters are
configured as, respectively, De-Emphasis, Bass and Treble controls.
Moreover the common 8th filter, from the subsequent processing section, can be available
on both channels (provided the pre-defined crossover frequencies are not used, XO[3:0]=0,
and the dual-band DRC is not used).
In the second section mixing and crossover filters are available. If B
(Figure 17), they are fully user-programmable and allow generating a third channel (2.1
outputs). Alternatively, in B
2
DRC mode, those blocks will be used to split the sub-band and
2
DRC is not enabled
define the cutoff frequencies of the two bands. A prescaler and a final post-scaler allow full
control over the signal dynamic respectively before and after the filtering stages. A mixer
function is also available.
Figure 16. Left and right processing - part 1
Sampling
Sampling
frequency=Fs
frequency=Fs
From
From
I2S input
I2S input
interface
interface
x2
FIR
x2
over
FIR
sampling
over
x2
FIR
x2
over
FIR
sampling
over
Sampling
Sampling
frequency=2xFs
frequency=2xFs
PreScale
PreScale
PreScale
PreScale
Hi-Pass
Hi-Pass
Filter
Filter
If HPB=0
Hi-Pass
Hi-Pass
Filter
Filter
If HPB=0
Biquad#1Biquad#2Biquad#3Biquad
Biquad#1Biquad#2Biquad#3Biquad
User Defined Filters
If DSPB=0 and C1EQBP=0
Biquad#1Biquad#2Biquad#3Biquad
Biquad#1Biquad#2Biquad#3Biquad
User Defined Filters
If DSPB=0 and C2EQBP=0
#4
#4
#4
#4
If BQ5=1
and BQL=1
Biquad
#5
De-Emph.
If DEMP=0
If BQ5=1
and BQL=1
Biquad
#5
De-Emph.
If DEMP=0
IF BQ7=1
If BQ6=1
and BQL=1
and BQL=1
Biquad
Biquad
#7
#6
Bass Treble
If C1TCB=0
BTC: Bass Boost/Cut
TTC: Treble Boost/Cut
If BQ6=1
IF BQ7=1
and BQL=1
and BQL=1
Biquad
Biquad
#6
#7
Bass Treble
If C2TCB=0
BTC: Bass Boost/Cut
TTC: Treble Boost/Cut
L
L
L
R
AM045181v1
Doc ID 022033 Rev 1 25/88
Processing data paths STA369BW
Figure 17. Processing - part 2
Dual-band DRC enabled
C1Mx1
C1Mx1=
L
L
R
R
0x7fffff
+
+
C1Mx2
C1Mx2=
0x00000
C2Mx1
C2Mx1=
0x000000
+
+
C2Mx2
C2Mx2=
0x7fffff
C3Mx1
C3Mx1=
0x40000
+
+
C3Mx2
C3Mx2=
0x400000
User-Defined Mix Coefficients
User-Defined Mix Coefficients
Dual-band DRC disabled
C1Mx1
L
L
R
R
C1Mx1
+
+
C1Mx2
C1Mx2
Hi-Pass XO
B2DRC
Filter
Hi-pass
Hi-Pass XO
B2DRC
Hi-pass
Crossover Frequency determined by XO Setting
User Defined If XO=0000
User Defined If XO=0000
filter
Filter
filter
Channel ½
Hi-Pass XO
Biquad#5
Filter
--------------
Hi-pass XO
filter
+
+
CH3
Volume
CH1
Volume
CH2
Volume
CH3
Volume
DRC2
DRC1
DRC1
Vol
Vol
And
And
Limiter
Limiter
Vol
And
Limiter
DRC2
+
+
Post scale
Post scale
Post scale
Post scale
Post scale
Post scale
C2Mx1
C2Mx1
+
+
C2Mx2
C2Mx2
C3Mx1
C3Mx1
+
+
C3Mx2
C3Mx2
User-Defined Mix Coefficients
User-Defined Mix Coefficients
Channel ½
Hi-Pass XO
Biquad#5
Filter
--------------
Hi-pass XO
filter
Channel 3
Lo-Pass XO
Biquad
Filter
--------------
Low-pass XO
filter
Crossover Frequency determined by XO Setting
User Defined If XO=0000
User Defined If XO=0000
26/88 Doc ID 022033 Rev 1
Vol
Vol
And
And
Limiter
Limiter
Vol
Vol
And
And
Limiter
Limiter
Post scale
Post scale
Post scale
Post scale
B2DRC Disabled
AM045182v1
STA369BW I2C bus specification
6 I2C bus specification
The STA369BW supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master). This protocol defines any device that
sends data to the bus as a transmitter and any device that reads the data as a receiver. The
device that controls the data transfer is known as the master and the other as the slave. The
master always starts the transfer and provides data to the serial clock for synchronization.
The STA369BW is always a slave device in all of its communications. It supports up to
400 kb/sec rate (fast-mode bit rate). The STA369BW I
interface works properly only in the case that the master clock generated by the PLL has a
frequency 10 times higher compared to the frequency of the applied SCL signal.
6.1 Communication protocol
6.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition
while the clock is high is used to identify a START or STOP condition.
2
C is a slave-only interface. The I2C
6.1.2 Start condition
START is identified by a high-to-low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
6.1.3 Stop condition
STOP is identified by a low-to-high transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A STOP condition terminates communication between
the STA369BW and the bus master.
6.1.4 Data input
During data input the STA369BW samples the SDA signal on the rising edge of clock SCL.
For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.
6.2 Device addressing
To start communication between the master and the STA369BW, the master must initiate a
start condition. Following this, the master sends 8 bits (MSB first), corresponding to the
device select address and read or write mode, to the SDA line.
The seven most significant bits are the device address identifiers, corresponding to the I
bus definition. In the STA369BW the I
the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
2
C interface has two device addresses depending on
2
C
The eighth bit (LSB) identifies the read or write operation RW. This bit is set to 1 in read
mode and to 0 for write mode. After a START condition the STA369BW identifies on the bus
the device address and if a match is found, it acknowledges the identification on the SDA
Doc ID 022033 Rev 1 27/88
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