ST STA326 User Manual

2.1-channel high-efficiency digital audio system

Features

■ Wide supply voltage range (10 V - 36 V)

■ Three power output configurations

–2x40W + 1x80W –2x80W –1x160W

■ PowerSO-36 package (exposed pad up (EPU))

■ 2.1 channels of 24-bit DDX

100-dB SNR and dynamic range

■

■ 32 kHz to 192 kHz input sample rates

■ Digital gain/attenuation +48 dB to -80 dB in

0.5-dB steps

■ Four 28-bit user-programmable biquads (EQ)

per channel

■ I

C control

■ 2-channel I

■ Individual channel and master gain/attenuation

■ Individual channel and master soft/hard mute

■ Individual channel volume and EQ bypass

■ Bass/treble tone control

■ Dual independent programmable

S input data interface

limiters/compressors

■ Automodes

– 32 preset EQ curves – 15 preset crossover settings – Auto volume-controlled loudness – 3 preset volume curves – 2 preset anti-clipping modes – Preset nighttime listening mode – Preset TV AGC

Table 1. Device summary

STA326

PowerSO-36 with exposed pad up

■ Input and output channel mapping

■ AM noise-reduction and PWM

frequency-shifting modes

■ Software volume update and muting

■ Auto zero detect and invalid input detect

muting

■ Selectable DDX

output + variable PWM speeds

■ Selectable de-emphasis

■ Post-EQ user-programmable mix with default

2.1 bass-management settings

■ Variable max power correction for lower full-

power THD

■ Four output routing configurations

■ Selectable clock input ratio

■ 96 kHz internal processing sample rate, 24 to

28-bit precision

■ Video application supports 576 * fs input mode

ternary or binary PWM

Order code Package Packaging

STA326 PowerSO-36 EPU Tube

STA32613TR PowerSO-36 EPU Tape and reel

January 2012 Doc ID 11531 Rev 5 1/58

www.st.com

Contents STA326

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 EQ processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Output configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Package pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 General interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 DC electrical specifications (3.3 V buffers) . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3 Power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.3.1 DDX® power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.3.2 DDX

variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 26

7.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/58 Doc ID 11531 Rev 5

STA326 Contents

7.7 Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7.1 Master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7.2 Channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7.3 Volume description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.8 Automode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.8.1 Automodes EQ, volume, GC (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . 35

7.8.2 Automode AM/prescale/bass management scale (addr 0x0C) . . . . . . . 36

7.8.3 Preset EQ settings (addr 0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.9 Channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.9.1 Channel 1 configuration (addr 0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.9.2 Channel 2 configuration (addr 0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.9.3 Channel 3 configuration (addr 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.10 Tone control (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.11 Dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.11.1 Limiter 1 attack/release threshold (addr 0x12) . . . . . . . . . . . . . . . . . . . . 41

7.11.2 Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . . 41

7.11.3 Limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 41

7.11.4 Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . . 41

7.11.5 Dynamics control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.11.6 Anti-clipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.11.7 Dynamic range compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8 User programmable processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1 EQ - biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.2 Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.3 Postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.4 Mix/bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.5 Calculating 24-bit signed fractional numbers from a dB value . . . . . . . . . 47

8.6 User defined coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.6.1 Coefficient address register 1 (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . 47

8.6.2 Coefficient b1data register bits 23:16 (addr 0x17) . . . . . . . . . . . . . . . . . 47

8.6.3 Coefficient b1data register bits 15:8 (addr 0x18) . . . . . . . . . . . . . . . . . . 47

8.6.4 Coefficient b1data register bits 7:0 (addr 0x19) . . . . . . . . . . . . . . . . . . . 47

8.6.5 Coefficient b2 data register bits 23:16 (addr 0x1A) . . . . . . . . . . . . . . . . 47

8.6.6 Coefficient b2 data register bits 15:8 (addr 0x1B) . . . . . . . . . . . . . . . . . 48

8.6.7 Coefficient b2 data register bits 7:0 (addr 0x1C) . . . . . . . . . . . . . . . . . . 48

Doc ID 11531 Rev 5 3/58

Contents STA326

8.6.8 Coefficient a1 data register bits 23:16 (addr 0x1D) . . . . . . . . . . . . . . . . 48

8.6.9 Coefficient a1 data register bits 15:8 (addr 0x1E) . . . . . . . . . . . . . . . . . 48

8.6.10 Coefficient a1 data register bits 7:0 (addr 0x1F) . . . . . . . . . . . . . . . . . . 48

8.6.11 Coefficient a2 data register bits 23:16 (addr 0x20) . . . . . . . . . . . . . . . . 48

8.6.12 Coefficient a2 data register bits 15:8 (addr 0x21) . . . . . . . . . . . . . . . . . 48

8.6.13 Coefficient a2 data register bits 7:0 (addr 0x22) . . . . . . . . . . . . . . . . . . 48

8.6.14 Coefficient b0 data register bits 23:16 (addr 0x23) . . . . . . . . . . . . . . . . 49

8.6.15 Coefficient b0 data register bits 15:8 (addr 0x24) . . . . . . . . . . . . . . . . . 49

8.6.16 Coefficient b0 data register bits 7:0 (addr 0x25) . . . . . . . . . . . . . . . . . . 49

8.6.17 Coefficient write control register (addr 0x26) . . . . . . . . . . . . . . . . . . . . . 49

8.7 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.8 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.9 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.10 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.11 Variable max power correction (addr 0x27, 0x28) . . . . . . . . . . . . . . . . . . 53

8.12 Fault detect recovery (addr 0x2B, 0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . 53

9 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4/58 Doc ID 11531 Rev 5

STA326 Description

1 Description

The STA326 comprises digital audio processing, digital amplifier control and DDX® power output stage to create a high-power single-chip DDX

solution for high-quality,

high-efficiency, all-digital amplification.

The STA326 power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge to give up to 2 x 40 W plus 1 x 80 W of power output. Two channels can be provided by two full-bridges to give up to 2 x 80 W of power. The IC can also be configured as a single parallel full-bridge capable of high-current operation and 1 x 160 W output.

Also provided in the STA326 is a full assortment of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel and bass/treble tone control. Automodes enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. This includes auto volume loudness, preset volume curves, preset EQ settings and new advanced AM radio-interference reduction modes.

The serial audio data input interface accepts all possible formats, including the popular I

format.

Three channels of DDX audio to patented DDX

processing are provided. This high-quality conversion from PCM

3-state PWM switching provides over 100 dB of SNR and dynamic

range.

Figure 1. Block diagram

SDA SCL

DDX-SPIRIT

Processing

Power-Down

DDX

FAULTTWARN

Half-Bridge

Half-Bridge Power Stage

Power Stage

LRCKI

BICKI

SDI_12

I2C

Serial Data

Mapping &

Mapping & Resampling

Resampling

Input,

Channel

PLL

CLK

System Contro

System Timing

Audio EQ, Mix,

Crossver,

Volume, Limiter

Processing

Figure 2. Channel signal flow diagram through the digital core

I2S Input

Channel

Mapping

Re-sampling

Processing

Mix

Crossover

Filter

Volu me Limiter

Interp

Quad

EAPD

DDX

OUT1A

OUT1B

OUT2A

OUT2B

DDX Output

Doc ID 11531 Rev 5 5/58

Description STA326

1.1 EQ processing

Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In this block, up to four user-defined biquads can be applied to each of the two channels.

Prescaling, DC-blocking, high-pass, de-emphasis, bass, and tone control filters can also be applied based on various configuration parameter settings.

The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. And the CxEQBP bits can be used to bypass the EQ function on a per channel basis. Figure 3 shows the internal signal flow through the EQ block.

Figure 3. Channel signal flow through the EQ block

Re-s amp led Input

Pre

Scale

High-Pass

Filter

BQ#1 BQ#2

BQ#4BQ#3

De-

Emphasis

Bass

Filter

Treble

Filter

To Mix

If HPB = 0

1.2 Output configurations

Figure 4. Output power-stage configurations

OUT1A

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

OUT1A

OUT1B

OUT2A

OUT2B

4 Biquads User defined if AMEQ = 00 Preset EQ if AMEQ = 01 Auto Lo udness if AMEQ = 10

If DSPB = 0 & CxEQB = 0

Channel 1

Channel 2

Channel 1

Channel 2

Channel 3

If Cx TCB = 0

If DEMP = 1

BT C: Bass Boo st/Cut TT C: Treble Boost/Cut

2-channel (full-bridge) configuration, register bits OCFG[1:0] = 00

2.1-channel configuration, register bits OCFG[1:0] = 01

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

Channel 3

OUT2A

OUT2B

6/58 Doc ID 11531 Rev 5

1-channel mono-parallel configuration, register bits OCFG[1:0] = 11

The setup register is Configuration register

F (addr 0x05) on page 31

STA326 Pin out

2 Pin out

2.1 Package pins

Figure 5. Pin connections

2.2 Pin list

Table 2. Pin list

Number Type Name Description

1 I/O SUB_GND Ground

2 N.C. N.C. Not connected

VCC_SIGN

VSS VDD

GND

BICKI

LRCKI

SDI

VDDA

GNDA

XTI

PLL_FILTER

RESERVED

SDA

SCL

RESET

CONFIG

VDD_REG

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

10 11 12 13 14 15 16 17 18

1 2 3 4 5 6 7 8 9

SUB_GND N.C. OUT2B 2B N.C. GND2B GND2A 2A OUT2A OUT1B 1B GND1B GND1A N.C. 1A OUT1A GND_CLEAN GND_REG

3 O OUT2B Output half bridge 2B

4 I/O 2B Positive supply

5 N.C. N.C. Not connected

6 I/O GND2B Negative supply

7 I/O GND2A Negative supply

8 I/O 2A Positive supply

9 O OUT2A Output half bridge 2A

10 O OUT1B Output half bridge 1B

11 I/O 1B Positive supply

12 I/O GND1B Negative supply

13 I/O. GND1A Negative supply

14 N.C. N.C. Not connected

Doc ID 11531 Rev 5 7/58

Pin out STA326

Table 2. Pin list

Number Type Name Description

15 I/O 1A Positive supply

16 O OUT1A Output half bridge 1A

17 I/O GND_CLEAN Logical ground

18 I/O GND_REG Substrate ground

19 I/O VDD_REG Logic supply

20 I/O VL Logic supply

21 I CONFIG Logic levels

22 I RESET Reset

23 I SCL I

24 I/O SDA I

25 - RESERVED This pin must be connected to GND

26 I PLL_FILTER Connection to PLL filter

27 I XTI PLL input clock

28 I/O GNDA Analog ground

29 I/O VDDA Analog supply, nominally 3.3 V

C serial clock

C serial data

30 I SDI I2S serial data channels 1 & 2

31 I/O LRCKI I

32 I BICKI I

S left/right clock,

S serial clock

33 I/O GND Digital ground

34 I/O VDD Digital supply, nominally 3.3 V

35 I/O VSS 5 V regulator referred to +

36 I/O _SIGN 5 V regulator referred to ground

8/58 Doc ID 11531 Rev 5

STA326 Pin out

2.3 Pin description

OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3)

Output half bridge PWM outputs 1A, 1B, 2A and 2B provide the input signals to the speakers.

CONFIG (pin 21)

The configuration input pin is normally connected to ground. Using the mono high power BTL configuration requires the CONFIG input pin to be shorted to VREG1

RESET (pin 22)

Driving RESET low sets all outputs low and returns all register settings to their default (reset) values. The reset is asynchronous to the internal clock.

C signals (pins 23 and 24)

The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification (Chapter 6 on page 16 gives more information). Fast-mode (400 kB/s) I supported.

C communication is

GNDA and VDDA (pins 28 and 29)

This is the 3.3 V analog supply for the phase locked loop. It must be well decoupled and filtered for good noise immunity since the audio performance of the device depends upon the PLL circuit.

CLK (pin 27)

This is the master clock in used by the digital core. The master clock must be an integer multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256 * fs) for a 48 kHz sample rate; it is the default setting at power-up. Care must be taken to provide the device with the nominal system clock frequency; over-clocking the device may result in anomalous operation, such as inability to communicate.

FILTER_PLL (pin 26)

This is the connection for external filter components for the PLL loop compensation. The schematic diagram in Figure 20 on page 54 shows the recommended circuit.

BICKI (pin 32)

The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64 * fs using I

S serial format.

SDI_12 (pin 30)

This is the serial data input where PCM audio information enters the device. Six format choices are available including I of 16, 18, 20 and 24 bits.

S, left or right justified, LSB or MSB first, with word widths

LRCKI (pin 31)

The left/right clock input is for data word framing. The clock frequency is at the input sample rate, fs.

Doc ID 11531 Rev 5 9/58

Electrical specifications STA326

3 Electrical specifications

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

amb

DD33

stg

3.3 V I/O power supply (pins VDDA, VDD) -0.5 to 4 V

Voltage on input pins -0.5 to (V

Voltage on output pins -0.5 to (V

DD33

+0.5) V

Storage temperature -40 to +150 °C

Ambient operating temperature -20 to +85 °C

DC supply voltage (pins nA, nB) 40 V

MAX

Table 4. Thermal data

Maximum voltage on VL (pin 20) 5.5 V

Symbol Parameter Min Typ Max Unit

thj-case

j-SD

WARN

h-SD

Table 5. Recommended operating conditions

Thermal resistance junction to case (thermal pad) - - 2.5 °C/W

Thermal shut-down junction temperature - 150 - °C

Thermal warning temperature - 130 - °C

Thermal shut-down hysteresis - 25 - °C

Symbol Parameter Value Unit

DD33

I/O power supply 3.0 to 3.6 V

Operating junction temperature -20 to +125 °C

3.1 General interface specifications

Operating conditions V

Table 6. General interface electrical characteristics

Symbol Parameter Test Condition Min. Typ. Max. Unit

esd

1. The leakage currents are generally very small (< 1 nA). The values given here are the maximum values after an electrostatic stress on the pin.

10/58 Doc ID 11531 Rev 5

Low level input no pull-up Vi = 0 V

High level input no pull-down Vi = V

3-state output leakage without pull-up/down

Electrostatic protection (human-body model)

= 3.3 V ±0.3 V, T

DD33

amb

DD33

= V

DD33

Leakage current < 1 μA2000 - - V

= 25° C unless otherwise specified

(1)

--1μA

--2μA

STA326 Electrical specifications

3.2 DC electrical specifications (3.3 V buffers)

Operating conditions V

Table 7. DC electrical specifications

= 3.3 V ±0.3 V, T

DD33

Symbol Parameter Test condition Min. Typ. Max. Unit

hyst

Low level input voltage - - - 0.8 V

High level input voltage - 2.0 - - V

Schmitt trigger hysteresis - 0.4 - - V

Low level output IoI = 2 mA - - 0.15 V

High level output Ioh = -2 mA

3.3 Power electrical specifications

Operating conditions V otherwise specified.

Table 8. Power electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

dsON

Power Pchannel/Nchannel MOSFET RdsON

= 3.3 V ±0.3 V, VL= 3.3 V, = 30 V, T

DD33

Id = 1A - 200 270 mΩ

= 25° C unless otherwise specified

amb

DD33

- 0.15

--V

= 25° C unless

amb

dss

Power Pchannel/Nchannel leakage Idss

Power Pchannel RdsON matching

Power Nchannel RdsON matching

Dt_s Low current dead time (static)

d ON

d OFF

Turn-on delay time Resistive load - - 100 ns

Turn-off delay time Resistive load - - 100 ns

Rise time

Fall time

Supply voltage - 10 - 36 V

-PWRDN

-hiz

Low logical state voltage VL VL = 3.3 V 0.8 - - V

High logical state voltage VH VL = 3.3V --1.7V

Supply current from in PWRDN

Supply current from in 3-state

= 35V --50μA

Id = 1 A 95 - - %

See test circuits,

Figure 6 and Figure 7

Resistive load, Figure 6 and Figure 7

-1020ns

--25ns

Pin PWRDN = 0 V - - 3 mA

= 30 V, 3-state - 22 - mA

Doc ID 11531 Rev 5 11/58

Electrical specifications STA326

Table 8. Power electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Input pulse width = 50% duty,

switching

-80-mA

frequency = 384 kHz, no LC filters

-4.56-A

out-sh

Supply current from in operation

(both channel switching)

Overcurrent protection threshold (short circuit current limit)

pw-min

Undervoltage protection threshold

Output minimum pulse width No load 70 150 ns

Output power (refer to test circuit

Figure 6. Test circuit 1

Low current dead time = MAX(DTr, DTf)

Duty cycle = 50%

INxY

M58

M57

--7-V

THD = 10% RL = 4Ω, = 21 V

= 8Ω, = 36 V

50 80

THD = 1% RL = 4Ω, = 21 V

RL = 8Ω, = 36 V

OUTxY

gnd

OUTxY

DTr DTf

R 8 W

V67

vdc = /2

(3/4)

(1/2)

(1/4)

40 62

Figure 7. Test circuit 2

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

Duty cycle=A Duty cycle=B

M58

DTin(A)

INA

M57

Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure

12/58 Doc ID 11531 Rev 5

DTout(A)

OUTA

Iout=1.5A

C69

470nF

Rload=4Ω

C71 470nF

M64

OUTB

M63

DTout(B) DTin(B)

L68 10μL67 10μ

Iout=1.5A

C70

470nF

INB

D06AU1651

STA326 Power supply and control sequencing

4 Power supply and control sequencing

To guarantee correct operation and reliability, the recommended power-on/off sequence as shown in Figure 8 should be followed.

Figure 8. Recommended power-on/off sequence

Vcc > V

PWRDN

should be turned on before VL. This prevents uncontrolled current flowing through the

internal protection diode connected between V

(logic supply) and VCC (high power supply)

which could result in damage to the device.

PWRDN must be released after V

is switched on. An input signal can then be sent to the

power stage.

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Characterization curves STA326

5 Characterization curves

Figure 9. Channel separation vs. frequency

+10

dBr A

-10

-20

-30

-40

-50

-60

-70

-80

-90

-90 20 20k50 100 200 500 1k 2k 5k 10k

20 20k50 100 200 500 1k 2k 5k 10k

Figure 10. THD vs. output power - single ended

THD (%)

Vcc = 36 V

0.5

0.2

0.1

0.05

0.02

0.01

0.01 100m 60200m 500m 1 2 5 10 20 50

100m 60200m 500m 1 2 5 10 20 50

Vcc = 36 V

= 4 Ω

f= 1 kHz

Po (W)

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STA326 Characterization curves

Figure 11. THD vs. output power - BTL

THD (%)

Vcc = 36 V

0.5

0.2

0.1

0.05

0.02

0.01

0.01 100m 100200m 500m 1 2 5 10 20 50

100m 100200m 500m 1 2 5 10 20 50

Vcc = 36 V

Rl = 8 Ω

f= 1 kHz

Po (W)

Figure 12. THD vs. frequency - BTL

0.5

THD (%)

0.2

0.1

0.05

0.02

0.01

0.01 20 20k50 100 200 500 1k 2k 5k 10k

20 20k50 100 200 500 1k 2k 5k 10k

Vcc = 36 V

RL = 8 Ω

f= 1 kHz

Doc ID 11531 Rev 5 15/58

I2C bus specification STA326

6 I2C bus specification

The STA326 supports the I2C protocol. This protocol defines any device that sends data on to the I that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA326 is always a slave device in all of its communications.

C bus as a transmitter and any device that reads the data as a receiver. The device

6.1 Communication protocol

Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition.

Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.

Stop condition

STOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA326 and the bus master.

Data input

During the data input the STA326 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

6.2 Device addressing

To start communication between the master and the STA326, the master must initiate with a start condition. Following this, the master sends 8 bits (MSB first) onto the SDA line corresponding to the device select address and read or write mode.

The 7 MSBs are the device address identifiers, corresponding to the I STA326 device address is 0x34.

The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write mode. After a START condition the STA326 identifies the device address on the bus. If a match is found, it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.

C bus definition. The

16/58 Doc ID 11531 Rev 5

STA326 I2C bus specification

6.3 Write operation

Following the START condition the master sends a device select code with the RW bit set to 0. The STA326 acknowledges this and then the master writes the internal address byte.

After receiving the internal byte address the STA326 again responds with an acknowledgement.

Figure 13. I

C write procedure

BYTE

WRITE

MULTIBYTE

WRITE

DEV-ADDR

START

DEV-ADDR

START

Byte write

In the byte write mode the master sends one data byte. This is acknowledged by the STA326. The master then terminates the transfer by generating a STOP condition.

Multi-byte write

The multi-byte write modes can start from any internal address. Sequential data byte writes will be written to sequential addresses within the STA326.

The master generating a STOP condition terminates the transfer.

6.4 Read operation

ACK

SUB-ADDR

ACK

SUB-ADDR

ACK

DATA IN

STOP

DATA IN

STOP

Figure 14. I2C read procedure

CURRENT ADDRESS

READ

RANDOM

ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

START

DEV-ADDR

ACK

RW=

ACK

HIGH

ACK

DATA

SUB-ADDR

DATA

SUB-ADDR

NO ACK

STOP

ACK

DEV-ADDR

START RW

ACK

DATA

ACK

DEV-ADDR

START RW

ACK

NO ACK

DATA

STOP

NO ACK

DATA

STOP

DATA

CK NO ACK

DATA

STOP

Current address byte read

Following the START condition the master sends a device select code with the RW bit set to

1. The STA326 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

Doc ID 11531 Rev 5 17/58

I2C bus specification STA326

Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes will be read from sequential addresses within the STA326. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.

Random address byte read

Following the START condition the master sends a device select code with the RW bit set to 0. The STA326 acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA326 again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA326 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

Random address multi-byte read

The multi-byte read modes could start from any internal address. Sequential data bytes will be read from sequential addresses within the STA326. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.

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