ST STA323W User Manual

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Features

STA323W

2.1-channel high-efficiency digital audio system

! Wide supply voltage range (10 V - 36 V)

! Three power output configurations

– 2x10W + 1 x20W –2x20W –1x40W

! Thermal protection

! Under-voltage protection

! Short-circuit protection

! PowerSO-36 slug down package

! 2.1 channels of 24-bit DDX

100-dB SNR and dynamic range

! 32 kHz to 192 kHz input sample rates

! Digital gain/attenuation +48 dB to -80 dB in

0.5-dB steps

! Four 28-bit user programmable biquads (EQ)

per channel

! I

C control

! 2-channel I

! Individual channel and master gain/attenuation

! Individual channel and master soft and hard

S input data interface

mute

! Individual channel volume and EQ bypass

! DDX

! Bass/treble tone control

! Dual independent programmable

POP free operation

limiters/compressors

! AutoModes™ settings for:

– 32 preset EQ curves – 15 preset crossover settings – Auto volume controlled loudness – 3 preset volume curves – 2 preset anti-clipping modes – Preset night-time listening mode – Preset TV AGC

PowerSO-36 (slug down)

! Input and output channel mapping

! AM noise-reduction and PWM frequency

shifting modes

! Soft volume update and muting

! Auto zero detect and invalid input detect

muting selectable DDX

ternary or binary

PWM output plus variable PWM speeds

! Selectable de-emphasis

! Post-EQ user programmable mix with default

2.1 bass-management settings

! Variable max power correction for lower

full-power THD

! Four output routing configurations

! Selectable clock input ratio

! 96 kHz internal processing sample rate, 24 to

28-bit precision

! Video application supports 576 * fs input mode

Table 1. Device summary

Order code Package

STA323W PowerSO-36 (slug down)

STA323W13TR PowerSO-36 in tape & reel

May 2008 Rev 6 1/77

www.st.com

Contents STA323W

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1 EQ processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2 Output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 General interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 DC electrical specifications (3.3 V buffers) . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3 Power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.4 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.5 Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1 Output power against supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2 Audio performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2.1 Stereo mode, operation with VCC = 26 V, 8 Ω load . . . . . . . . . . . . . . . . 23

5.2.2 Stereo mode, operation with V

5.2.3 Half-bridge binary mode, operation with Vcc = 18.5 V . . . . . . . . . . . . . 28

C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

= 18.5 V . . . . . . . . . . . . . . . . . . . . . . 24

7 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 Configuration register A (address 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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STA323W Contents

7.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1.3 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1.4 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1.5 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.2 Configuration register B (address 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2.1 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2.2 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2.3 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.3 Configuration register C (address 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.1 DDX® power-output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.2 DDX

variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 43

7.4 Configuration register D (address 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.4.1 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.4.2 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.4.3 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.4.4 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4.5 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4.6 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 45

7.4.7 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.5 Configuration register E (address 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5.1 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5.2 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5.3 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5.4 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5.5 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.5.6 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.6 Configuration register F (address 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6.1 Output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.7 Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.7.1 Master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.7.2 Channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.7.3 Volume description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.8 AutoModes™ registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.8.1 AutoModes™ EQ, volume, GC (address 0x0B) . . . . . . . . . . . . . . . . . . . 52

7.8.2 AutoModes™ AM/pre-scale/bass management scale (address 0x0C) . 53

7.8.3 Preset EQ settings (address 0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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Contents STA323W

7.9 Channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.9.1 Channel 1 configuration (address 0x0E) . . . . . . . . . . . . . . . . . . . . . . . . 55

7.9.2 Channel 2 configuration (address 0x0F) . . . . . . . . . . . . . . . . . . . . . . . . 55

7.9.3 Channel 3 configuration (address 0x10) . . . . . . . . . . . . . . . . . . . . . . . . 56

7.10 Tone control (address 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.11 Dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.11.1 Limiter 1 attack/release threshold (address 0x12) . . . . . . . . . . . . . . . . . 57

7.11.2 Limiter 1 attack/release threshold (address 0x13) . . . . . . . . . . . . . . . . . 57

7.11.3 Limiter 2 attack/release rate (address 0x14) . . . . . . . . . . . . . . . . . . . . . 57

7.11.4 Limiter 2 attack/release threshold (address 0x15) . . . . . . . . . . . . . . . . . 58

7.11.5 Dynamics control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.11.6 Anti-clipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.11.7 Dynamic range compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8 User-programmable settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.1 EQ - biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.2 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.3 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.4 Mix/bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.5 Calculating 24-bit signed fractional numbers from a dB value . . . . . . . . . 65

8.6 User defined coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.6.1 Coefficient address register 1 (address 0x16) . . . . . . . . . . . . . . . . . . . . 65

8.6.2 Coefficient b1data register bits 23:16 (address 0x17) . . . . . . . . . . . . . . 65

8.6.3 Coefficient b1data register bits 15:8 (address 0x18) . . . . . . . . . . . . . . . 65

8.6.4 Coefficient b1data register bits 7:0 (address 0x19) . . . . . . . . . . . . . . . . 65

8.6.5 Coefficient b2 data register bits 23:16 (address 0x1A) . . . . . . . . . . . . . 65

8.6.6 Coefficient b2 data register bits 15:8 (address 0x1B) . . . . . . . . . . . . . . 66

8.6.7 Coefficient b2 data register bits 7:0 (address 0x1C) . . . . . . . . . . . . . . . 66

8.6.8 Coefficient a1 data register bits 23:16 (address 0x1D) . . . . . . . . . . . . . 66

8.6.9 Coefficient a1 data register bits 15:8 (address 0x1E) . . . . . . . . . . . . . . 66

8.6.10 Coefficient a1 data register bits 7:0 (address 0x1F) . . . . . . . . . . . . . . . 66

8.6.11 Coefficient a2 data register bits 23:16 (address 0x20) . . . . . . . . . . . . . 66

8.6.12 Coefficient a2 data register bits 15:8 (address 0x21) . . . . . . . . . . . . . . 66

8.6.13 Coefficient a2 data register bits 7:0 (address 0x22) . . . . . . . . . . . . . . . 67

8.6.14 Coefficient b0 data register bits 23:16 (address 0x23) . . . . . . . . . . . . . 67

8.6.15 Coefficient b0 data register bits 15:8 (address 0x24) . . . . . . . . . . . . . . 67

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8.6.16 Coefficient b0 data register bits 7:0 (address 0x25) . . . . . . . . . . . . . . . 67

8.6.17 Coefficient write control register (address 0x26) . . . . . . . . . . . . . . . . . . 67

8.7 Reading and writing coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.7.1 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.7.2 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . 68

8.7.3 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.7.4 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.8 Variable max power correction (address 0x27-0x28) . . . . . . . . . . . . . . . . 70

8.9 Fault detect recovery (address 0x2B - 0x2C) . . . . . . . . . . . . . . . . . . . . . . 71

8.10 Status indicator register (address 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.10.1 Thermal warning indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.10.2 Fault detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8.10.3 PLL unlock indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 75

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5/77

List of tables STA323W

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Component selection “Table A” - full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Component selection "Table B" - binary half-bridge operation . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Component selection "Table C" - mono operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. Power electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12. Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 13. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 14. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 15. IR and MCS settings for input sample rate and clock rate . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 16. Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 17. IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 18. Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 19. Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 20. Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 21. Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 22. Supported serial audio input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 23. Serial input data timing characteristics (fs = 32 to 192 kHz). . . . . . . . . . . . . . . . . . . . . . . . 42

Table 24. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 25. Channel input mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 26. DDX® power-output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 27. DDX® output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 28. DDX® compensating pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 29. High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 30. De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 31. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 32. Post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 33. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 34. Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 35. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 36. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 37. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 38. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 39. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 40. PWM output speed selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 41. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 42. Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 43. Output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 44. Output configuration selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 45. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 46. Binary clock loss detection enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 47. Auto-EAPD on clock loss enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 48. Software power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6/77

STA323W List of tables

Table 49. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 50. Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 51. Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 52. AutoModes™ EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 53. AutoModes™ volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 54. AutoModes™ gain compression/limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 55. AMPS - AutoModes™ auto pre scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 56. AutoModes™ AM switching enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 57. AutoModes™ AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 58. AutoModes™ crossover setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 59. Crossover frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 60. Preset EQ selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 61. Channel Limiter Mapping Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 62. Channel PWM output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 63. Tone control boost/cut selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 64. Limiter attack rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 65. Limiter release rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 66. Limiter attack - threshold selection (AC-mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 67. Limiter release threshold selection (AC-mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 68. Limiter attack - threshold selection (DRC-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 69. Limiter release threshold selection (DRC-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 70. RAM block for biquads, mixing, and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 71. Thermal warning indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 72. Fault detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 73. PLL unlock indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 74. PowerSO-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 75. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7/77

List of figures STA323W

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. Channel signal flow diagram through the digital core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 3. Channel signal flow diagram through the EQ block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. Output power stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Schematic for 2 (half-bridge) channels + 1 (full-bridge) channel . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Power schematic for 2 (full-bridge) channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Power schematic for 1 mono parallel channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Package pins (viewed from top of device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Recommended power up and power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. Stereo mode - output power vs. supply voltage, THD+N = 10% . . . . . . . . . . . . . . . . . . . . 21

Figure 13. Output power vs. supply for stereo bridge, THD+N=1% . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14. Half-bridge binary mode output power vs. supply, THD+N=10% . . . . . . . . . . . . . . . . . . . 22

Figure 15. Half-bridge binary mode output power vs. supply voltage, THD+N=1% . . . . . . . . . . . . . . 22

Figure 16. Typical efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 17. Typical frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 18. FFT -60 dB, 1 kHz output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 19. FFT inter-modulation distortion 19 kHz and 20 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 20. Frequency response, 1 W, BTL, 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 21. Channel separation, 1 W, BTL stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 22. THD vs. output power, BTL, 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 23. THD vs. frequency, 1 W output, stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 24. THD vs. frequency, BTL, 16 W output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 25. FFT 0 dBFS 1 kHz, 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 26. FFT 0 dBFS 1 kHz, 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 27. FFT 0 dBFS 1 kHz, 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 28. FFT -60 dBFS 1 kHz, 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 29. FFT -60 dBFS 1 kHz, 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 30. FFT -60 dBFS 1 kHz, 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 31. PSRR BTL, 500 mV ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 32. Frequency response, 1 W, binary half-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 33. Channel separation, 1 W, half bridge binary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 34. THD+N vs. output power, single ended, 1 kHz, half-bridge binary . . . . . . . . . . . . . . . . . . . 29

Figure 35. THD vs. frequency, single ended, 1 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 36. THD vs. frequency, single ended, 8 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 37. FFT 0 dB, 1 kHz, single ended, 2 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 38. FFT 0 dB, 1 kHz, single ended, 3 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 39. FFT 0 dB, 1 kHz, single ended, 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 40. FFT -60 dB, single ended, 1 kHz, 2 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 41. FFT -60 dB, single ended, 1 kHz, 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 42. FFT -60 dB, single ended, 1 kHz, 3 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 43. PSRR single ended, 500 mV ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 44. I Figure 45. I

Figure 46. General serial input and output formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 47. Serial input and data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 48. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

C write procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

C read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8/77

STA323W List of figures

Figure 49. Biquad filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 50. Mix/bass management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 51. PowerSO-36 slug down outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

9/77

Description STA323W

1 Description

The STA323W is a single-chip audio system comprising digital audio processing, digital amplifier control and a DDX

power-output stage. The STA323W uses all-digital

amplification to provide high-power, high-quality and high-efficiency.

The STA323W power section consists of four independent half-bridges. These can be configured, by digital control, to operate in the following modes.

" Tw o channels, provided by two half-bridges, and a single full-bridge giving up to

2 x 10 W + 1 x 20 W of power output.

" Two channels, provided by two full-bridges, giving up to 2 x 20 W of power.

" A single, parallel, full-bridge channel capable of high-current operation and giving

1 x 40W output.

The STA323W also provides a full set of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel, and bass and treble tone control. AutoModes™ enable a time-to-market advantage by substantially reducing the amount of software development needed for specific functions. These includes auto volume loudness, preset volume curves and preset EQ settings. New advanced AM radio-interference reduction modes are also provided.

The serial audio data input interface accepts all existing formats, including the I

Three channels of DDX

processing are provided. This high-quality conversion from PCM

audio to DDX patented 3-state PWM switching provides over 100 dB of SNR and dynamic range.

Figure 1. Block diagram

SDA

LRCKI

BICKI

SDI_12

SCL

I2C

Serial data

input, channel

mapping and

resampling

Power d own

System control

System timing

CLK

Audio EQ, mix,

crossover,

volume, limiter

processing

DDX

processing

TWARN

Powe r d own

power stage

FAU LT

Figure 2. Channel signal flow diagram through the digital core

input

Channel mapping

Re-sampling

processing

Mix

Crossover

filter

Vol um e

limiter

Interpol

Quad

half-bridge

EAPD

DDX

OUT1A

OUT1B

OUT2A

OUT2B

DDX output

10/77

STA323W Description

1.1 EQ processing

Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In these blocks, up to four user-defined Biquads can be applied to each of the two channels.

Pre-scaling, DC-blocking high-pass, de-emphasis, bass, and tone control filters can also be implemented by means of configuration parameter settings.

The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. The CxEQBP bits can also be used to bypass the EQ functionality on a per channel basis. Figure 3 shows the internal signal flow through the EQ block.

Figure 3. Channel signal flow diagram through the EQ block

Re-sampled input

pre-scale

High pass

If HPB= 0

1.2 Output options

Figure 4. Output power stage configurations

Half

bridge

Half

bridge

Half

bridge

Half

bridge

Half

bridge

Half

bridge

Half

bridge

Half

bridge

filter

OUT1A

OUT1B

OUT2A

OUT2B

OUT1A

OUT1B

OUT2A

OUT2B

BQ#1

BQ#2 BQ#3 BQ#4

4 biquads User defined if AMEQ = 00 Preset EQ if AMEQ = 01 Auto loudness if AMEQ = 10

If DSPB = 0 and CxEQB = 0

Channel 1

Channel 2

Channel 1

Channel 2

Channel 3

2-channel (full bridge) configuration, register bits OCFG[1:0] = 00

2.1-channel configuration, register bits OCFG[1:0] = 01

De-

emphasis

If DEMP = 1

Bass

filter

If CxTCB = 0 BTC: bass boost/cut TTC: treble boost/cut

Tr eb l e

filter

To mix

Half

bridge

Half

bridge

Half

bridge

Half

bridge

OUT1A

OUT1B

OUT2A

OUT2B

1-channel mono-parallel configuration, register bits OCFG[1:0] = 11

Channel 3

The setup register is Configuration

11/77

Applications STA323W

2 Applications

Table 2. Component selection “Table A” - full-bridge operation

Load Inductor Capacitor

4 Ω 10 µH1.0µF

6 Ω 15 µH 470 nF

8 Ω 22 µH 470 nF

Table 3. Component selection "Table B" - binary half-bridge operation

Load Inductor Capacitor

4 Ω 22 µH 680 nF

6 Ω 33 µH 470 nF

8 Ω 47 µH 390 nF

Table 4. Component selection "Table C" - mono operation

Load Inductor Capacitor

2 Ω 4.7 µH2.0µF

3 Ω 6.8 µH1.0µF

4 Ω 10 µH1.0µF

Figure 5. Schematic for 2 (half-bridge) channels + 1 (full-bridge) channel

VCC_SIGN

VSS

VDD

GND

BICKI

LRCKI

SDI

VDDA

GNDA

XTI

PLL_FILTER

RESERVED

SDA

SCL

RESET

CONFIG

VDD_REG

STA323W

SUB_GND

OUT2B

VCC2B

GND2B

GND2A

VCC2A

OUT2A

OUT1B

VCC1B

GND1B

GND1A

VCC1A

OUT1A

GND_CLEAN

GND_REG

N.C.

12/77

STA323W Applications

Figure 6. Power schematic for 2 (full-bridge) channels

VCC_SIGN

VSS

VDD

GND

BICKI

LRCKI

SDI

VDDA

GNDA

XTI

PLL_FILTER

RESERVED

SDA

SCL

RESET

CONFIG

VDD_REG

SUB_GND

OUT2B

VCC2B

GND2B

GND2A

VCC2A

OUT2A

OUT1B

VCC1B

GND1B

GND1A

VCC1A

OUT1A

GND_CLEAN

GND_REG

N.C.

STA323W

Figure 7. Power schematic for 1 mono parallel channel

VCC_SIGN

VSS

VDD

GND

BICKI

LRCKI

SDI

VDDA

GNDA

XTI

PLL_FILTER

RESERVED

SDA

SCL

RESET

CONFIG

VDD_REG

STA323W

SUB_GND

OUT2B

VCC2B

GND2B

GND2A

VCC2A

OUT2A

OUT1B

VCC1B

GND1B

GND1A

VCC1A

OUT1A

GND_CLEAN

GND_REG

N.C.

13/77

Pin out STA323W

3 Pin out

3.1 Pin numbering

Figure 8. Package pins (viewed from top of device)

Table 5. Pin list

SUB_GND

N.C. OUT2B VCC2B

N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A

N.C. VCC1A OUT1A

GND_CLEAN

GND_REG

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18

Pin Type Name Description

1 I/O SUB_GND Ground

2 N.C. N.C. Not connected

3 O OUT2B Output half bridge 2B

4 I/O VCC2B Positive supply

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

VCC_SIGN VSS VDD GND BICKI LRCKI SDI VDDA GNDA XTI PLL_FILTER RESERVED SDA SCL RESET CONFIG VL VDD_REG

5 N.C. N.C. Not connected

6 I/O GND2B Negative supply

7 I/O GND2A Negative supply

8 I/O VCC2A Positive supply

9 O OUT2A Output half bridge 2A

10 O OUT1B Output half bridge 1B

11 I/O VCC1B Positive supply

12 I/O GND1B Negative supply

13 I/O. GND1A Negative supply

14 N.C. N.C. Not connected

15 I/O VCC1A Positive supply

16 O OUT1A Output half bridge 1A

14/77

STA323W Pin out

Table 5. Pin list (continued)

Pin Type Name Description

17 I/O GND_CLEAN Reference ground

18 I/O GND_REG Substrate ground

19 I/O VDD_REG Logic supply

20 I/O VL Logic supply to power section

21 I CONFIG Logic levels

22 I RESET Reset

23 I SCL I

24 I/O SDA I

25 - RESERVED Reserved test pin must be connected to ground

26 I PLL_FILTER Connection to PLL filter

27 I XTI PLL input clock

28 I/O GNDA Analog ground

29 I/O VDDA Analog supply 3.3

30 I SDI_12 I

31 I/O LRCKI I

32 I BICKI I

33 I/O GND Digital ground

34 I/O VDD Digital supply 3.3 V

C serial clock

C serial data

S serial data channels 1 and 2

S left/right clock,

S serial clock

35 I/O VSS 5 V regulator referred to Vcc

36 I/O VCC_SIGN 5 V regulator referred to ground

3.2 Pin description

OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3)

The half-bridge PWM outputs 1A, 1B, 2A and 2B provide the inputs signals to the speakers.

RESET (pin 22)

Driving RESET low sets all outputs low and returns all register settings to their default (reset) values. The reset is asynchronous to the internal clock.

SDA, SCL (pins 24, 23)

The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification (See Chapter 6 on page 33.) Fast-mode (400 kB/s) I

VDDA, GNDA (pins 29,28)

The phase locked loop power is applied here. This +3.3V supply must be well decoupled and filtered for good noise immunity since the audio performance of the device depends upon the PLL circuit.

C communication is supported.

15/77

Pin out STA323W

CLK (pin 27)

This is the master clock input used by the digital core. The master clock must be an integer multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256 * fs) for a 48kHz sample rate; it is the default setting at power-up. Care must be taken to provide the device with the nominal system clock frequency; over-clocking the device may result in anomalous operation, such as inability to communicate.

PLL_FILTER (pin 26)

This is the connection for the external filter components for the PLL loop compensation. Refer to the schematic diagram Figure 7: Power schematic for 1 mono parallel channel on

page 13 for the recommended circuit.

BICKI (pin 32)

The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64 * fs using I

S serial format.

SDI (pin 30)

This is the serial data input where PCM audio information enters the device. Six format choices are available including I of 16, 18, 20 and 24 bits.

S, left or right justified, LSB or MSB first, with word widths

LRCKI (pin 31)

The left/right clock input is for data word framing. The clock frequency is at the input sample rate, fs.

16/77

STA323W Electrical specifications

4 Electrical specifications

Table 6. Absolute maximum ratings

Symbol Parameter Value Unit

DD_3.3

stg

amb

MAX

Table 7. Thermal data

3.3 V I/O power supply -0.5 to 4 V

Voltage on input pins -0.5 to (VDD+0.5) V

Voltage on output pins -0.5 to (VDD+0.5) V

Storage temperature -40 to +150 °C

Ambient operating temperature -40 to +85 °C

DC supply voltage 40 V

Maximum voltage on pin 20 5.5 V

Symbol Parameter Min Typ Max Unit

thj-case

j-SD

WARN

h-SD

Table 8. Recommended DC operating conditions

Thermal resistance junction to case (thermal pad) 2.5 °C/W

Thermal shut-down junction temperature 150 °C

Thermal warning temperature 130 °C

Thermal shut-down hysteresis 25 °C

Symbol Parameter Value Unit

DD_3.3

I/O power supply 3.0 to 3.6 V

Operating junction temperature -40 to +125 °C

4.1 General interface specifications

Operating conditions V

Table 9. General interface electrical characteristics

Symbol Parameter Test Condition Min. Typ. Max. Unit

esd

1. The leakage currents are generally very small < 1 nA. The values given here are maximum after an electrostatic stress on the pin.

Leakage current: low level input, no pull-up

Leakage current: high level input, no pull-down

Leakage current: 3-state output without pull-up/down

Electrostatic protection (human body model)

= 3.3 V ±0.3 V, T

DD33

amb

= 0 V

= V

DD33

= V

DD33

Leakage < 1µA2000 V

17/77

= 25° C unless otherwise specified.

(1)

1 µA

2 µA

Electrical specifications STA323W

4.2 DC electrical specifications (3.3 V buffers)

Operating conditions V

Table 10. DC electrical characteristics

= 3.3 V ±0.3 V, T

DD33

Symbol Parameter Test condition Min. Typ. Max. Unit

hyst

Low level Input voltage 0.8 V

High level Input voltage 2.0 V

Schmitt trigger hysteresis 0.4 V

Low level output IoI = 2mA 0.15 V

High level output Ioh = -2mA

4.3 Power electrical specifications

Operating conditions V otherwise specified.

Table 11. Power electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

dsON

dss

Power Pchannel/Nchannel MOSFET R

Power Pchannel/Nchannel leakage I

dss

Power Pchannel R matching

Power Nchannel R matching

= 3.3 V ±0.3 V, VL= 3.3 V, VCC=30V, T

DD33

dsON

Id = 1 A 200 270 mΩ

Vcc = 35 V 50 µA

dsON

Id = 1 A 95 %

= 25° C unless otherwise specified

amb

VDD -

0.15

= 25° C unless

amb

Dt_s Low current dead time (static)

d ON

d OFF

VCC-

PWRDN

VCC-hiz

Turn-on delay time Resistive load 100 ns

Turn-off delay time Resistive load 100 ns

Rise time

Fall time

Supply voltage 8 36 V

Low logical state voltage VL = 3.3 V 0.8 V

High logical state voltage VL = 3.3 V 1.7 V

Supply current from Vcc in PWRDN

Supply current from Vcc in 3state

18/77

See test circuits , Figure

9 and Figure 10

Resistive load, Figure 9

and Figure 10

Resistive load, Figure 9

and Figure 10

10 20 ns

25 ns

PWRDN = 0 3 mA

= 30 V, 3-state 22 mA

STA323W Electrical specifications

Table 11. Power electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Input pulse width = 50% duty,

switching frequency = 384 kHz,

no LC filters;

80 mA

46 A

VCC

out-sh

Supply current from VCC in operation

(both channel switching)

Overcurrent protection threshold (short circuit current limit)

pw-min

Under voltage protection threshold

Output minimum pulse width No Load 70 150 ns

Output power

4.4 Timing specifications

Table 12. Timing characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

RESET

VCO

Figure 9. Test circuit 1

Hold time for RESET (pin 22) Active low rest 100 ns

VCO free run frequency No clock applied to XTI 18 28 MHz

Low current dead time = MAX(DTr, DTf)

Duty cycle = 50%

INxY

M58

M57

THD = 10%,

= 8 Ω, VCC = 18 V

THD = 1%, R

= 8 Ω, VCC = 18 V

+Vcc

OUTxY

gnd

OUTxY

DTr DTf

R 8

Ω

V67

vdc = Vcc/2

20 W

16 W

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

19/77

Electrical specifications STA323W

Figure 10. Test circuit 2

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

Duty cycle=A Duty cycle=B

M58

DTin(A)

INA

M57

Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure

OUTA

Iout=1.5A

DTout(A)

C69

470nF

Rload=4Ω

C71 470nF

L68 10µL67 10µ

C70

470nF

4.5 Power supply and control sequencing

Figure 11 shows the recommended power-up and power-down sequencing. The "time zero"

reference point is taken where V

Figure 11. Recommended power up and power down sequence

crosses the under voltage lockout threshold.

M64

OUTB

INB

M63

D06AU1651

DTout(B) DTin(B)

Iout=1.5A

20/77

STA323W Electrical characteristics curves

5 Electrical characteristics curves

5.1 Output power against supply voltage

Figure 12. Stereo mode - output power vs. supply voltage, THD+N = 10%

Output power (W)

10 12 14 16 18 20 22 24 26

Power Supply Voltage (VDC)

4ohm

6ohm

8ohm

Figure 12 shows the full-scale output power (0 dBFS digital input with unity amplifier gain)

as a function of power supply voltage for 4, 6, and 8 Ω loads in either DDX

mode or binary full bridge mode. Output power is constrained for higher impedance loads by the maximum voltage limit of the STA323W and by the over-current protection limit for lower impedance loads. The minimum threshold for the over-current protection circuit of the STA323W is 4 A (at 25° C) but the typical threshold is 6 A for the device. The solid curves shows the typical output power capability of the device. The dotted curves shows the output power capability constrained to the minimum current specification of the STA323W. The output power curves assume proper thermal management of the power device's internal dissipation.

Figure 13. Output power vs. supply for stereo bridge, THD+N=1%

output power (W) - BTL 1% THD

6 ohm

4 ohm

8 ohm

16ohm

10 15 20 25 30

supply voltage (V)

21/77

Electrical characteristics curves STA323W

Figure 13 shows the mono mode output power as a function of power supply voltages for

loads of 4, 6, 8 and 16 Ω. The same current limits as those given for Figure 12 apply, except output current is 8 A minimum, with 12 A typical in the mono-bridge configuration. The solid curves show typical performance and dashed curves depict the minimum current limit. The output power curves assume proper thermal management of the power device internal dissipation.

Figure 14. Half-bridge binary mode output power vs. supply, THD+N=10%

Output power (W)

Curves measured at f = 1 kHz and using

a blocking capacitor of 330 µF

10 12 14 16 18 20 22 2 26

Power Supply Voltage (VDC)

4ohm

6ohm

8ohm

Figure 14 shows the output power as a function of power supply voltages for loads of 4, 6,

and 8 Ω when the STA323W is operated in a half-bridge binary mode. The curves depict typical performance. Minimum current limit is not reached for these combinations of voltage and load impedance. The output power curves assume proper thermal management of the power device internal dissipation.

Figure 15. Half-bridge binary mode output power vs. supply voltage, THD+N=1%

output power (W)

3 ohm

Curves measured at f = 1 kHz and using

2 ohm

a blocking capacitor of 330 µF

4 ohm

8 ohm

10 15 20 25 30

supply voltage (V)

22/77

STA323W Electrical characteristics curves

100

5.2 Audio performance

5.2.1 Stereo mode, operation with VCC = 26 V, 8 Ω load

Figure 16. Typical efficiency

010203040 50

Total Output Power (Watts)

Figure 17. Typical frequency response

60 70 80

Figure 18. FFT -60 dB, 1 kHz output

23/77

Electrical characteristics curves STA323W

Figure 19. FFT inter-modulation distortion 19 kHz and 20 kHz

5.2.2 Stereo mode, operation with VCC = 18.5 V

Figure 20. Frequency response, 1 W, BTL, 8 Ω

dBr A

+2.5

+1.5

+0.5

-0.5

-1

-1.5

-2

-2.5

-3 20 20k50 100 200 500 1 k 2k 5k 10k

6ohm

Figure 21. Channel separation, 1 W, BTL stereo mode

dBr A

+10

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 20 20k50 100 200 500 1k 2k 5k 10k

4ohm

8ohm

4 ohm

8ohm

24/77

STA323W Electrical characteristics curves

Figure 22. THD vs. output power, BTL, 1 kHz

0.5

0.2

0.1

0.05

0.02

0.01

100m 50200m 500m 1 2 5 10 20

8ohm

6ohm

4ohm

Figure 23. THD vs. frequency, 1 W output, stereo mode

0.5

0.2

0.1

0.05

0.02

0.01 20 20k50 100 200 500 1k 2k 5k 10k

4ohm

6ohm

8ohm

Figure 24. THD vs. frequency, BTL, 16 W output

0.5

0.2

0.1

0.05

0.02

0.01

6ohm

8ohm

4ohm

20 20k50 100 200 500 1k 2k 5k 10k

25/77

Electrical characteristics curves STA323W

Figure 25. FFT 0 dBFS 1 kHz, 8 Ω

dBr

+40

+20

-20

-40

-60

-80

-100

-120

-140 20 20k50 100 200 500 1k 2k 5k 10k

Figure 26. FFT 0 dBFS 1 kHz, 6 Ω

dBr

+40

+20

-20

-40

-60

-80

-100

-120

-140 20 20k50 100 200 500 1k 2k 5k 10k

Figure 27. FFT 0 dBFS 1 kHz, 4 Ω

dBr

+40

+20

-20

-40

-60

-80

-100

-120

-140 20 20k50 100 200 500 1k 2k 5 k 10k

26/77

STA323W Electrical characteristics curves

Figure 28. FFT -60 dBFS 1 kHz, 8 Ω

dBr

+40

+20

-20

-40

-60

-80

-100

-120

-140

-160 20 20k50 100 200 500 1k 2k 5k 10k

Figure 29. FFT -60 dBFS 1 kHz, 6 Ω

dBr

+40

+20

-20

-40

-60

-80

-100

-120

-140

-160 20 20k50 100 200 500 1k 2k 5k 10k

Figure 30. FFT -60 dBFS 1 kHz, 4 Ω

dBr

+40

+20

-20

-40

-60

-80

-100

-120

-140

-160 20 20k50 100 200 500 1k 2k 5k 10k

27/77

Electrical characteristics curves STA323W

Figure 31. PSRR BTL, 500 mV ripple

dBr

+10

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 20 20030 40 50 60 70 80 90 100

6ohm8 ohm

4 ohm

5.2.3 Half-bridge binary mode, operation with Vcc = 18.5 V

Figure 32. Frequency response, 1 W, binary half-bridge mode

dBr A

+2.5

+1.5

+0.5

-0.5

-1

-1.5

-2

-2.5

-3

20 20k50 10 0 200 500 1k 2k 5k 10k

3ohm

4ohm

2ohm

Frequency (Hz)

Figure 33. Channel separation, 1 W, half bridge binary

dBr A

+10

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 20 20k50 100 20 0 500 1k 2k 5k 10k

28/77

8ohm

4 ohm

STA323W Electrical characteristics curves

Figure 34. THD+N vs. output power, single ended, 1 kHz, half-bridge binary

0.5

0.2

0.1

0.05

0.02

0.01

100m 50200m 500m 1 2 5 10 20

4ohm 3 ohm

2 ohm

Figure 35. THD vs. frequency, single ended, 1 W

0.5

0.4

0.3

0.2

0.1

0.08

0.06

0.05

0.04

0.03

0.02

2ohm

3ohm

4ohm

0.01 20 20k50 100 200 500 1k 2k 5k 10k

Figure 36. THD vs. frequency, single ended, 8 W

0.5

0.2

0.1

0.05

0.02

0.01 20 20k50 100 200 500 1k 2k 5k 10k

2ohm

3ohm

4ohm

29/77

Electrical characteristics curves STA323W

Figure 37. FFT 0 dB, 1 kHz, single ended, 2 Ω

dBr

+10

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-120 20 20k50 100 200 500 1k 2k 5k 10k

Figure 38. FFT 0 dB, 1 kHz, single ended, 3 Ω

dBr

+10

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-120 20 20k50 100 200 500 1k 2k 5k 10k

Figure 39. FFT 0 dB, 1 kHz, single ended, 4 Ω

dBr

+10

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

20 20k50 100 200 500 1k 2k 5k 10k

30/77

STA323W Electrical characteristics curves

Figure 40. FFT -60 dB, single ended, 1 kHz, 2 Ω

dBr

+10

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

20 20k50 100 200 500 1k 2k 5k 10k

Figure 41. FFT -60 dB, single ended, 1 kHz, 4 Ω

dBr

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

20 20k50 100 200 500 1k 2k 5k 10k

Figure 42. FFT -60 dB, single ended, 1 kHz, 3 Ω

dBr

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140 20 20k50 100 200 500 1k 2k 5k 10k

31/77

Electrical characteristics curves STA323W

Figure 43. PSRR single ended, 500 mV ripple

dBr A

+10

-10

-20

-30

-40

-50 2 ohm

-60

-70

-80

-90

-100

3 ohm

4 ohm

20030 40 5 0 60 70 80 90100

32/77

STA323W I2C bus specification

6 I2C bus specification

The STA323W supports the I2C fast mode (400 kbit/s) protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA323W is always a slave device in all of its communications.

6.1 Communication protocol

Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition.

Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.

Stop condition

STOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA323W and the bus master.

Data input

During the data input the STA323W samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

6.2 Device addressing

To start communication between the master and the STA323W, the master must initiate with a START condition. Following this, the master sends 8 bits (MSB first) on the SDA line corresponding to the device select address and read or write mode.

The 7 MSBs are the device address identifiers, corresponding to the I the STA323W the I

The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write mode. After a START condition the STA323W identifies the device address on the bus. If a match is found, it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.

C interface uses a device address of decimal 34 (binary 00100010).

C bus definition. In

33/77

I2C bus specification STA323W

6.3 Write operation

Figure 44. I2C write procedure

BYTE WRITE

MULTIBYTE

WRITE

DEV-ADDR

START

DEV-ADDR

START

ACK

SUB-ADD R

ACK

SUB-ADD R

Following the START condition the master sends a device select code with the RW bit set to 0. The STA323W acknowledges this and then the master writes the internal address byte.

After receiving the internal byte address the STA323W again responds with an acknowledgement.

Byte write

In the byte write mode the master sends one data byte. This is acknowledged by the STA323W. The master then terminates the transfer by generating a STOP condition.

ACK

DATA IN

STOP

DATA IN

STOP

Multi-byte write

The multi-byte write modes can start from any internal address. Sequential data bytes are written to sequential addresses within the STA323W.

The master generates a STOP condition to terminate the transfer.

6.4 Read operation

Figure 45. I2C read procedure

CURRENT ADDRESS

READ

RANDOM

ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

Current address byte read

Following the START condition the master sends a device select code with the RW bit set to 1. The STA323W acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

DEV-ADDR

START

DEV-ADDR

START

DEV-ADDR

START

DEV-ADDR

START

ACK

RW=

ACK

HIGH

ACK

DATA

SUB-ADDR

DATA

SUB-ADDR

NO ACK

STOP

ACK

DEV-ADDR

START RW

ACK

DATA

ACK

DEV-ADDR

START RW

ACK

NO ACK

DATA

STOP

NO ACK

DATA

STOP

DATA

CK NO ACK

DATA

STOP

34/77

STA323W I2C bus specification

Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA323W. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer.

Random address byte read

Following the START condition the master sends a device select code with the RW bit set to 0. The STA323W acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA323W again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA323W acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

Random address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are then read from sequential addresses within the STA323W. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer.

35/77

7 Register descriptions

You must not reprogram the register bits marked “Reserved”. It is important that these bits keep their default reset values.

Table 13. Register summary

Address Name D7 D6 D5 D4 D3 D2 D1 D0

0x00 ConfA FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

0x01 ConfB C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

0x02 ConfC Reserved CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

0x03 ConfD MME ZDE DRC BQL PSL DSPB DEMP HPB

0x04 ConfE SVE ZCE DCCV PWMS AME Reserved MPC MPCV

0x05 ConfF EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0

0x06 Mmute Reserved Reserved Reserved Reserved Reserved Reserved Reserved MMute

0x07MvolMV7MV6MV5MV4MV3MV2MV1MV0

0x08 C1VolC1V7C1V6C1V5C1V4C1V3C1V2C1V1C1V0

0x09 C2VolC2V7C2V6C2V5C2V4C2V3C2V2C2V1C2V0

0x0A C3VolC3V7C3V6C3V5C3V4C3V3C3V2C3V1C3V0

0x0B Auto1 AMPS Reserved AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0

0x0C Auto2 XO3 XO2 XO1 XO1 AMAM2 AMAM1 AMAM0 AMAME

0x0D Auto3 Reserved Reserved Reserved PEQ4 PEQ3 PEQ2 PEQ1 PEQ0

0x0E C1Cfg C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB

0x1F C2Cfg C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB

0x10 C3Cfg C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP Reserved Reserved

0x11 Tone TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

0x12 L1ar L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

0x13 L1atrt L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

0x14 L2ar L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

0x15 L2atrt L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

0x16 Cfaddr2 CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

0x17 B1cf1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

0x18 B1cf2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

0x19 B1cf3C1B7C1B6C1B5C1B4C1B3C1B2C1B1C1B0

0x1A B2cf1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

0x1B B2cf2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

0x1C B2cf3C2B7C2B6C2B5C2B4C2B3C2B2C2B1C2B0

0x1D A1cf1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16

36/77

STA323W Register descriptions

Table 13. Register summary (continued)

Address Name D7 D6 D5 D4 D3 D2 D1 D0

0x1E A1cf2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

0x1F A1cf3C3B7C3B6C3B5C3B4C3B3C3B2C3B1C3B0

0x20 A2cf1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

0x21 A2cf2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

0x22 A2cf3C4B7C4B6C4B5C4B4C4B3C4B2C4B1C4B0

0x23 B0cf1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

0x24 B0cf2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

0x25 B0cf3C5B7C5B6C5B5C5B4C5B3C5B2C5B1C5B0

0x26 Cfud Reserved Reserved Reserved Reserved Reserved Reserved WA W1

0x27 MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

0x28 MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

0x29 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0x2A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0x2B FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

0x2C FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

0x2D Status PLLUL Reserved Reserved Reserved Reserved Reserved FAULT TWARN

7.1 Configuration register A (address 0x00)

D7 D6 D5 D4 D3 D2 D1 D0

FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

01100011

7.1.1 Master clock select

Table 14. Master clock select

Bit R/W RST Name Description

0RW1MCS0

1RW1MCS1

2RW0MCS2

The STA323W supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. Therefore the internal clock is:

" 32.768 MHz for 32 kHz

" 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

" 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

Master clock select: selects the ratio between the input

S sample frequency and the input clock.

37/77

The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The correlation between the input clock and the input sample rate is determined by the status of the MCSx bits and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally.

Table 15. IR and MCS settings for input sample rate and clock rate

Input sample rate

fs (kHz)

32, 44.1, 48 00 768 * fs 512 * fs 384 * fs 256 * fs 128 * fs 576 * fs

88.2, 96 01 384 * fs 256 * fs 192 * fs 128 * fs 64 * fs x

176.4, 192 1X 384 * fs 256 * fs 192 * fs 128 * fs 64 * fs x

7.1.2 Interpolation ratio select

Table 16. Interpolation ratio select

Bit R/W RST Name Description

4:3 RW 00 IR[1:0]

The STA323W has variable interpolation (re-sampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a down-sample by a factor of 2.

The IR bits determine the re-sampling ratio of this interpolation.

Table 17. IR bit settings as a function of input sample rate

Input sample rate fs (kHz) IR[1, 0] 1st stage interpolation ratio

MCS[2:0]

000 001 010 011 100 101

Selects internal interpolation ratio based on input I

S sample

frequency

32 00 2 times over-sampling

44.1 00 2 times over-sampling

48 00 2 times over-sampling

88.2 01 Pass-Through

96 01 Pass-Through

176.4 10 Down-sampling by 2

192 10 Down-sampling by 2

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STA323W Register descriptions

7.1.3 Thermal warning recovery bypass

Table 18. Thermal warning recovery bypass

Bit R/W RST Name Description

5RW1TWRB

0: thermal warning recovery enabled 1: thermal warning recovery disabled

If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery determines if the adjustment is removed when thermal warning is negative. If TWRB = 0 and TWAB = 0, then, when a thermal warning disappears, the gain adjustment determined by the thermal warning post-scale (default = -3 dB) is removed and the gain is applied to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears, the thermal warning post-scale gain adjustment remains until TWRB is changed to zero or the device is reset.

7.1.4 Thermal warning adjustment bypass

Table 19. Thermal warning adjustment bypass

Bit R/W RST Name Description

6RW1TWAB

The STA323W on-chip power output block provides feedback to the digital controller by the power control block inputs. The TWARN input is used to indicate a thermal warning condition. When TWARN is active (set to 0 for a period greater than 400 ms) the power control block forces an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning volume adjustment is applied, whether the gain is reapplied when TWARN is inactive, depends on the TWRB bit.

0: thermal warning adjustment enabled 1: thermal warning adjustment disabled

7.1.5 Fault detect recovery bypass

Table 20. Fault detect recovery bypass

Bit R/W RST Name Description

7 RW 0 FDRB

The DDX power block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is active (set to 0), the power control block attempts a recovery from the fault by activating the 3-state output (setting it to 0 which directs the power output block to begin recovery). It holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x29-0x2A), then toggles it back to 1. This sequence is repeated as long as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1.

0: fault detector recovery enabled 1: fault detector recovery disabled

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7.2 Configuration register B (address 0x01)

D7 D6 D5 D4 D3 D2 D1 D0

C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

10000000

7.2.1 Serial audio input interface format

Table 21. Serial audio input interface format

Bit R/W RST Name Description

3:0 RW 0000 SAI[3:0]

4 RW 0 SAIFB

7.2.2 Serial data interface

The STA323W serial audio input interfaces with standard digital audio components and accepts several different serial data formats. The STA323W always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI, serial clock BICKI, and serial data SDI.

The SAI register (configuration register B (address 0x01) bits D3-D0) and the SAIFB register (configuration register B (address 0x01) bit D4) are used to specify the serial data format. The default serial data format is I

Figure 46 and in Tab le 2 1 and Tab le 2 2 .

Figure 46. General serial input and output formats

I2S

LRCLK

SCLK

SDATA

Left Justified

LRCLK

SCLK

Determines the interface format of the input serial digital audio interface.

Data format: 0: MSB first 1: LSB first

S, MSB first. The formats available are shown in

Left Right

LSBMSB LSBMSB MSB

Left Right

SDATA

Right Justified

LRCLK

SCLK

SDATA

LSBMSB

Left Right

Table 22. lists the serial audio input formats supported by STA323W when

BICKI = 32 * fs, 48 * fs or 64 * fs, where the sampling rate fs = 32, 44.1, 48, 88.2, 96, 176.4 or 192 kHz.

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LSBMSB MSB

LSBMSB LSB

MSB MSB

STA323W Register descriptions

Table 22. Supported serial audio input formats

BICKI SAI[3:0] SAIFB Interface format

32 * fs 1100 X I

1110 X Left/right-justified 16-bit data

48 * fs 0100 X I

0100 X I

1000 X I

0100 0 MSB first I

1100 1 LSB first I

0001 X Left-justified 24-bit data

0101 X Left-justified 20-bit data

1001 X Left-justified 18-bit data

1101 X Left-justified 16-bit data

0010 X Right-justified 24-bit data

0110 X Right-justified 20-bit data

1010 X Right-justified 18-bit data

S 15-bit data

S 23-bit data

S 20-bit data

S 18-bit data

S 16-bit data

1110 X Right-justified 16-bit data

64 * fs 0000 X I

0100 X I

1000 X I

0000 0 MSB first I

1100 1 LSB first I

S 24-bit data

S 20-bit data

S 18-bit data

S 16-bit data

0001 X Left-justified 24-bit data

0101 X Left-justified 20-bit data

1001 X Left-justified 18-bit data

1101 X Left-justified 16-bit data

0010 X Right-justified 24-bit data

0110 X Right-justified 20-bit data

1010 X Right-justified 18-bit data

1110 X Right-justified 16-bit data

For example, SAI = 1110 and SAIFB = 1 specifies right justified 16-bit data, LSB first.

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Table 23. Serial input data timing characteristics (fs = 32 to 192 kHz)

parameter Timing

BICKI frequency (slave mode) 12.5 MHz max.

BICKI pulse width high (T1) (slave mode) 40 ns min.

BICKI active to LRCKI edge delay (T2) 20 ns min.

BICKI active to LRCKI edge delay (T3) 20 ns min.

SDI valid to BICKI active setup (T4) 20 ns min.

BICKI active to SDI hold time (T5) 20 ns min.

Figure 47. Serial input and data timing

T3T2

LRCKI

BICKI

SDI

7.2.3 Delay serial clock enable

Table 24. Delay serial clock enable

Bit R/W RST Name Description

5RW0DSCKE

Table 25. Channel input mapping

Bit R/W RST Name Description

6RW0C1IM

7RW1C2IM

Each channel received from the I2S can be mapped to any internal processing channel via the channel input mapping registers. This allows processing flexibility. The default settings of these registers map each I

S input channel to its corresponding processing channel.

0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate

anomalies in some I

0: processing channel 1 receives left I 1: processing channel 1 receives right I

0: processing channel 2 receives left I 1: processing channel 2 receives right I

S master devices

S input

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STA323W Register descriptions

7.3 Configuration register C (address 0x02)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

01000010

7.3.1 DDX® power-output mode

Table 26. DDX® power-output mode

Bit R/W RST Name Description

1:0 RW 10 OM[1:0] Selects configuration of DDX

The DDX® power output mode selects how the DDX® output timing is configured. Different power devices can use different output modes. The recommended use is OM = 10. When OM = 11 the CSZ bits determine the size of the DDX

Table 27. DDX® output modes

OM[1,0] Output stage - mode

00 Not used

01 Not used

10 Recommended

compensating pulse.

output.

11 Variable compensation

7.3.2 DDX® variable compensating pulse size

The DDX® variable compensating pulse size is intended to adapt to different power stage ICs. Contact ST for support when using this function.

Table 28. DDX® compensating pulse

CSZ[4:0] Compensating pulse size

00000 0 clock period compensating pulse size

00001 1 clock period compensating pulse size

……

10000 16 clock period compensating pulse size

……

11111 31 clock period compensating pulse size

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7.4 Configuration register D (address 0x03)

D7 D6 D5 D4 D3 D2 D1 D0

MME ZDE DRC BQL PSL DSPB DEMP HPB

01000000

7.4.1 High-pass filter bypass

Table 29. High-pass filter bypass

Bit R/W RST Name Description

0RW0HPB

The STA323W features an internal digital high-pass filter for DC blocking. The purpose of this filter is to prevent DC signals from passing through a DDX® amplifier. DC signals can cause speaker damage.

7.4.2 De-emphasis

Table 30. De-emphasis

Bit R/W RST Name Description

1RW0DEMP

By setting this bit to 1, de-emphasis is implemented on all channels. DSPB (DSP Bypass, Bit D2, CFA) bit must be set to 0 for de-emphasis to function.

7.4.3 DSP bypass

Table 31. DSP bypass

Bit R/W RST Name Description

2 RW 0 DSPB

0: AC coupling high pass filter enabled 1: AC coupling high pass filter enabled

0: no de-emphasis 1: de-emphasis

0: normal operation 1: bypass of EQ and mixing functionality

Setting the DSPB bit bypasses all the EQ and mixing functions of the STA323W core.

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STA323W Register descriptions

7.4.4 Post-scale link

Table 32. Post-scale link

Bit R/W RST Name Description

3 RW 0 PSL

0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value

Post-scale functionality is an attenuation placed after the volume control and directly before the conversion to PWM. Post-scale can also be used to limit the maximum modulation index and therefore the peak current. Setting 1, in the PSL register, causes the value stored in Channel 1 post-scale to be used for all three internal channels.

7.4.5 Biquad coefficient link

Table 33. Biquad coefficient link

Bit R/W RST Name Description

4RW0BQL

0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values

For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.

7.4.6 Dynamic range compression/anti-clipping bit

Table 34. Dynamic range compression/anti-clipping bit

Bit R/W RST Name Description

5RW0DRC

Both limiters can be used in one of two ways: anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.

7.4.7 Zero-detect mute enable

Table 35. Zero-detect mute enable

Bit R/W RST Name Description

6 RW 1 ZDE Setting of 1 enables the automatic zero-detect mute

Setting the ZDE bit enables the zero-detect automatic mute. When ZDE = 1, the zero-detect circuit looks at the input data to each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled.

0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode

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7.5 Configuration register E (address 0x04)

D7 D6 D5 D4 D3 D2 D1 D0

SVE ZCE Reserved PWMS AME Reserved MPC MPCV

11000010

7.5.1 Max power correction variable

Table 36. Max power correction variable

Bit R/W RST Name Description

0RW0MPCV

By enabling MPC and setting MPCV = 1, the max power correction becomes variable. By adjusting the MPCC registers (address 0x27-0x28) it is possible to adjust the THD at maximum unclipped power to a lower value for a particular application.

7.5.2 Max power correction

Table 37. Max power correction

Bit R/W RST Name Description

1RW1MPC

Setting the MPC bit corrects the power device at high power. This mode lowers the THD+N of the full DDX

system at, and slightly below, maximum power output.

7.5.3 AM mode enable

Table 38. AM mode enable

Bit R/W RST Name Description

3RW0AME

0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient

0: MPC disabled 1: MPC enabled

0: normal DDX 1: AM reduction mode DDX

operation

The STA323W features a DDX® processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when DDX operating in a device with an active AM tuner. The SNR of the DDX to ~83 dB in this mode, which is still greater than the SNR of AM radio.

7.5.4 PWM speed mode

Table 39. PWM speed mode

Bit R/W RST Name Description

4 RW 0 PWMS Normal or odd

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processing is reduced

STA323W Register descriptions

Table 40. PWM output speed selections

PWMS[1:0] PWM output speed

0 Normal speed (384kHz) all channels

1 Odd speed (341.3kHz) all channels

7.5.5 Zero-crossing volume enable

Table 41. Zero-crossing volume enable

Bit R/W RST Name Description

1: volume adjustments will only occur at digital zero-

6RW1ZCE

crossings 0: volume adjustments will occur immediately

The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks are audible.

7.5.6 Soft volume update enable

Table 42. Soft volume update enable

Bit R/W RST Name Description

7 RW 1 SVE

1: volume adjustments will use soft volume 0: volume adjustments will occur immediately

The STA323W includes a soft volume algorithm that steps through the intermediate volume values at a predetermined rate when a volume change occurs. By setting SVE = 0 this can be bypassed and volume changes will jump from the old to the new value directly. This feature is available only if individual channel volume bypass bit is set to 0.

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7.6 Configuration register F (address 0x05)

D7 D6 D5 D4 D3 D2 D1 D0

EAPD PWDN ECLE Reserved BCLE IDE OCFG1 OCFG0

01011100

7.6.1 Output configuration selection

Table 43. Output configuration selection

Bit R/W RST Name Description

1:0 RW 00 OCFG[1:0] 00: 2-channel (full-bridge) power, 1-channel DDX is default

Table 44. Output configuration selections

OCFG[1:0] Output power configuration

2 channel (full-bridge) power, 1 channel DDX:

1A/1B ◊ 1A/1B 2A/2B ◊ 2A/2B

2(half-bridge).1(full-bridge) on-board power: 1A ◊ 1A Binary 2A ◊ 1B Binary 3A/3B ◊ 2A/2B Binary

10 Reserved

1 channel mono-parallel:

3A ◊ 1A/1B 3B ◊ 2A/2B

Table 45. Invalid input detect mute enable

Bit R/W RST Name Description

2RW1IDE

0: disabled 1: enabled

Setting the IDE bit enables this function, which looks at the input I2S data and clocking and automatically mutes all outputs if the signals are invalid.

Table 46. Binary clock loss detection enable

Bit R/W RST Name Description

3RW1BCLE

0: disabled 1: enabled

Detects loss of input MCLK in binary mode and outputs 50% duty cycle to prevent audible noise when input clocking is lost.

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STA323W Register descriptions

Table 47. Auto-EAPD on clock loss enable

Bit R/W RST Name Description

5RW0ECLE

0: disabled 1: enabled

When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection.

Table 48. Software power down

Bit R/W RST Name Description

Software power down: 0: power down mode: initiates a power-down sequence

6RW1PWDN

Table 49. External amplifier power down

Bit R/W RST Name Description

7 RW 0 EAPD

EAPD is used to actively power down a connected DDX® power device. This register has to be written to 1 at start-up to enable the DDX

which results in a soft mute of all channels and finally asserts EAPD circa 260 ms later

1: normal operation

0: external power stage power down active 1: normal operation

power device for normal operation.

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7.7 Volume control

7.7.1 Master controls

Master mute register (address 0x06)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved MMUTE

00000000

Master volume register (Address 0x07)

D7 D6 D5 D4 D3 D2 D1 D0

MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0

11111111

Note: The value of volume derived from MV is dependent on the AMV AutoModes™ volume

settings.

7.7.2 Channel controls

Channel 1 volume (address 0x08)

D7 D6 D5 D4 D3 D2 D1 D0

C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0

01100000

Channel 2 volume (address 0x09)

D7 D6 D5 D4 D3 D2 D1 D0

C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0

01100000

Channel 3 volume (address 0x0A)

D7 D6 D5 D4 D3 D2 D1 D0

C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0

01100000

7.7.3 Volume description

The volume structure of the STA323W consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. The channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. These values are normally set at the initialization of the IC and not changed. The individual channel volumes are adjustable in

0.5-dB steps from +48 dB to -80 dB. The master volume control is normally mapped to the master volume of the system. The values of these two settings are summed to find the actual gain or volume value for any given channel.

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STA323W Register descriptions

When set to 1, the Master Mute will mute all channels, whereas the individual channel mutes (CxM) will mute only that channel. Both the Master Mute and the Channel Mutes provide a “soft mute”, that is, a gradual muting with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate of circa 96 kHz. A “hard mute” can be obtained by setting a value of 0xFF in any channel volume register or the master volume register. When volume offsets are provided, via the master volume register, any channel whose total volume is less than -100 dB is muted.

All changes in volume take place at zero-crossings when ZCE = 1 (configuration register E) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates occur immediately.

The STA323W also features a soft-volume update function. When SVE = 1 (in configuration register E) the volume ramps between intermediate values when the value is updated, This feature can be disabled by setting SVE = 0.

Each channel also contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting does not affect that channel. Also, master soft-mute does not affect the channel if CxVBP = 1.

Each channel also contains a channel mute. If CxM = 1 a soft mute is performed on that channel.

Table 50. Master volume offset as a function of MV[7:0]

MV[7:0] Volume offset from channel value

00000000 (0x00) 0 dB

00000001 (0x01) -0.5 dB

00000010 (0x02) -1 dB

……

01001100 (0x4C) -38 dB

……

11111110 (0xFE) -127 dB

11111111 (0xFF) Hard Master Mute

Table 51. Channel volume as a function of CxV[7:0]

CxV[7:0] Volume

00000000 (0x00) +48 dB

00000001 (0x01) +47.5 dB

00000010 (0x02) +47 dB

……

01100001 (0x5F) +0.5 dB

01100000 (0x60) 0 dB

01011111 (0x61) -0.5 dB

……

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Table 51. Channel volume as a function of CxV[7:0] (continued)

CxV[7:0] Volume

11111110 (0xFE) -79.5 dB

11111111 (0xFF) Hard channel mute

7.8 AutoModes™ registers

7.8.1 AutoModes™ EQ, volume, GC (address 0x0B)

D7 D6 D5 D4 D3 D2 D1 D0

AMPS Reserved AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0

10000000

Table 52. AutoModes™ EQ

AMEQ[1,0] Mode (Biquad 1-4)

00 User Programmable

01 Preset EQ - PEQ bits

10 Auto Volume Controlled Loudness Curve

11 Not used

Setting AMEQ to any value, other than 00, enables AutoModes™ EQ. When set, biquads 14 are not user programmable. Any coefficient settings for these biquads is ignored. Also when AutoModes™ EQ is used the pre-scale value for channels 1 and 2 becomes hard-set to -18 dB.

Table 53. AutoModes™ volume

AMV[1,0] Mode (MVOL)

00 MVOL 256, 0.5-dB steps (standard)

01 MVOL auto curve 30 steps

10 MVOL auto curve 40 steps

11 MVOL auto curve 50 steps

Table 54. AutoModes™ gain compression/limiters

AMGC[1:0] Mode

00 User programmable GC

01 AC no clipping

10 AC limited clipping (10%)

11 DRC night time listening mode

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STA323W Register descriptions

Table 55. AMPS - AutoModes™ auto pre scale

Bit R/W RST Name Description

AutoMode pre-scale

0 RW 0 AMPS

0: -18 dB used for pre-scale when AMEQ neq 00 1: User defined pre-scale when AMEQ neq 00

7.8.2 AutoModes™ AM/pre-scale/bass management scale (address 0x0C)

D7 D6 D5 D4 D3 D2 D1 D0

XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

00000000

Table 56. AutoModes™ AM switching enable

Bit R/W RST Name Description

0 RW 0 AMAME

0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM settings

3:1 RW 000 AMAM[2:0] Default: 000

Table 57. AutoModes™ AM switching frequency selection

AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs

000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz

001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz

010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz

011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz

100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz

101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz

110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz

When DDX® is used with an AM radio tuner, it is recommended to use the AMAM bits to automatically adjust the output PWM switching rate so that it depends on the specific radio frequency that the tuner is receiving. The values used in AMAM are also dependent upon the sample rate that is determined by the ADC used.

Table 58. AutoModes™ crossover setting

Bit R/W RST Name Description

000: user defined crossover coefficients are used

7:4 RW 0 XO[3:0]

Otherwise: preset coefficients are used for the required crossover setting

Table 59. Crossover frequency selection

XO[2:0] Bass management - crossover frequency

0000 User

0001 80 Hz

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Table 59. Crossover frequency selection (continued)

XO[2:0] Bass management - crossover frequency

0010 100 Hz

0011 120 Hz

0100 140 Hz

0101 160 Hz

0110 180 Hz

0111 200 Hz

1000 220 Hz

1001 240 Hz

1010 260 Hz

1011 280 Hz

1100 300 Hz

1101 320 Hz

1110 340 Hz

1111 360 Hz

7.8.3 Preset EQ settings (address 0x0D)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved PEQ4 PEQ3 PEQ2 PEQ1 PEQ0

00000000

Table 60. Preset EQ selection

PEQ[3:0] Setting

00000 Flat

00001 Rock

00010 Soft Rock

00011 Jazz

00100 Classical

00101 Dance

00110 Pop

00111 Soft

01000 Hard

01001 Party

01010 Vocal

01011 Hip-Hop

01100 Dialog

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STA323W Register descriptions

Table 60. Preset EQ selection (continued)

PEQ[3:0] Setting

01101 Bass-boost #1

01110 Bass-boost #2

01111 Bass-boost #3

10000 Loudness 1 (least boost)

10001 Loudness 2

10010 Loudness 3

10011 Loudness 4

10100 Loudness 5

10101 Loudness 6

10110 Loudness 7

10111 Loudness 8

11000 Loudness 9

11001 Loudness 10

11010 Loudness 11

11011 Loudness 12

11100 Loudness 13

11101 Loudness 14

11110 Loudness 15

11111 Loudness 16 (most boost)

7.9 Channel configuration registers

7.9.1 Channel 1 configuration (address 0x0E)

D7 D6 D5 D4 D3 D2 D1 D0

C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB

00000000

7.9.2 Channel 2 configuration (address 0x0F)

D7 D6 D5 D4 D3 D2 D1 D0

C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB

00000000

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7.9.3 Channel 3 configuration (address 0x10)

D7 D6 D5 D4 D3 D2 D1 D0

C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP Reserved Reserved

00000000

EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel.

CxEQBP:

" 0: perform EQ on channel X (normal operation)

" 1: bypass EQ on channel X

Tone control (bass and treble) can be bypassed on a per channel basis. If tone control is bypassed on a given channel the two filters that tone control utilizes are bypassed.

CxTCB:

" 0: perform tone control on channel x - (default operation)

" 1: bypass tone control on channel x

Each channel can be configured to output either the patented DDX PWM data or standard binary PWM encoded data. By setting the CxBO bit to ‘1’, each channel can be individually set to binary operation mode.

It is also possible to map each channel independently to either of the two limiters available within the STA323W. In the default mode the channels are not mapped to a limiter.

Table 61. Channel Limiter Mapping Selection

CxLS[1,0] Channel limiter mapping

00 Channel has limiting disabled

01 Channel is mapped to limiter #1

10 Channel is mapped to limiter #2

Each PWM output channel can receive data from any channel output of the volume block. Which channel a particular PWM output receives depends on the CxOM register bits for that channel.

Table 62. Channel PWM output mapping

CxOM[1:0] PWM output from

00 Channel 1

01 Channel 2

10 Channel 3

11 Not used

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STA323W Register descriptions

7.10 Tone control (address 0x11)

D7 D6 D5 D4 D3 D2 D1 D0

TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

01110111

Table 63. Tone control boost/cut selection

BTC[3:0]/TTC[3:0] Boost/cut

0000 -12 dB

0001 -12 dB

……

0111 -4 dB

0110 -2 dB

0111 0 dB

1000 +2 dB

1001 +4 dB

……

1101 +12 dB

1110 +12 dB

1111 +12 dB

7.11 Dynamics control

7.11.1 Limiter 1 attack/release threshold (address 0x12)

D7 D6 D5 D4 D3 D2 D1 D0

L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

01101010

7.11.2 Limiter 1 attack/release threshold (address 0x13)

D7 D6 D5 D4 D3 D2 D1 D0

L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

01101001

7.11.3 Limiter 2 attack/release rate (address 0x14)

D7 D6 D5 D4 D3 D2 D1 D0

L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

01101010

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7.11.4 Limiter 2 attack/release threshold (address 0x15)

D7 D6 D5 D4 D3 D2 D1 D0

L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

01101001

7.11.5 Dynamics control description

The STA323W includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for DVDs.) The two modes are selected via the DRC bit in Configuration Register D, bit 5 address 0x03. Each channel can be mapped to Limiter1 or Limiter2, or not mapped.

If a channel is not mapped, that channel will clip normally when 0 dB FS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then, if needed, adjust the gain of the mapped channels in unison.

The limiter attack thresholds are determined by the LxAT registers. When the Attack Threshold has been exceeded, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. A peak-detect algorithms used to control the gain reduction.

The release of limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume limiter block is passed through an RMS filter. The output of this filter is compared with the release threshold, determined by the Release Threshold register.

When the RMS filter output falls below the release threshold, the gain is increased at a rate dependent upon the release rate register. The gain can never be increased past its set value and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range. This is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.

In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold.

Figure 48. Basic limiter and volume flow diagram

Limiter

Gain/volume

RMS

Input

Gain Attenuation Saturation

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Output

STA323W Register descriptions

Table 64. Limiter attack rate selection

LxA[3:0] Attack rate dB/ms

0000 3.1584 Fast

0001 2.7072

0010 2.2560

0011 1.8048

0100 1.3536

0101 0.9024

0110 0.4512

0111 0.2256

1000 0.1504

1001 0.1123

1010 0.0902

1011 0.0752

1100 0.0645

1101 0.0564

1110 0.0501

1111 0.0451 Slow

Table 65. Limiter release rate selection

LxR[3:0] Release rate dB/ms

0000 0.5116 Fast

0001 0.1370

0010 0.0744

0011 0.0499

0100 0.0360

0101 0.0299

0110 0.0264

0111 0.0208

1000 0.0198

1001 0.0172

1010 0.0147

1011 0.0137

1100 0.0134

1101 0.0117

1110 0.0110

1111 0.0104 Slow

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7.11.6 Anti-clipping mode

Table 66. Limiter attack - threshold selection (AC-mode)

LxAT[3:0] AC (dB relative to FS)

0000 -12

0001 -10

0010 -8

0011 -6

0100 -4

0101 -2

0110 0

0111 +2

1000 +3

1001 +4

1010 +5

1011 +6

1100 +7

1101 +8

1110 +9

1111 +10

Table 67. Limiter release threshold selection (AC-mode)

LxRT[3:0] AC (dB relative to FS)

0000 -∞

0001 -29dB

0010 -20dB

0011 -16dB

0100 -14dB

0101 -12dB

0110 -10dB

0111 -8dB

1000 -7dB

1001 -6dB

1010 -5dB

1011 -4dB

1100 -3dB

1101 -2dB

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STA323W Register descriptions

Table 67. Limiter release threshold selection (AC-mode) (continued)

LxRT[3:0] AC (dB relative to FS)

1110 -1dB

1111 -0dB

7.11.7 Dynamic range compression mode

Table 68. Limiter attack - threshold selection (DRC-mode)

LxAT[3:0] DRC (dB relative to volume)

0000 -31

0001 -29

0010 -27

0011 -25

0100 -23

0101 -21

0110 -19

0111 -17

1000 -16

1001 -15

1010 -14

1011 -13

1100 -12

1101 -10

1110 -7

1111 -4

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Table 69. Limiter release threshold selection (DRC-mode)

LxRT[3:0] DRC (db relative to Volume + LxAT)

0000 -∞

0001 -38 dB

0010 -36 dB

0011 -33 dB

0100 -31 dB

0101 -30 dB

0110 -28 dB

0111 -26 dB

1000 -24 dB

1001 -22 dB

1010 -20 dB

1011 -18 dB

1100 -15 dB

1101 -12 dB

1110 -9 dB

1111 -6 dB

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STA323W User-programmable settings

8 User-programmable settings

8.1 EQ - biquad equation

The biquads use the equation that follows. This is shown in Figure 49.

Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2]

= b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2]

where Y[n] represents the output and X[n] represents the input. Signed, fractional 28-bit multipliers are used, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0.9999998808).

Coefficients stored in the user defined coefficient RAM are referenced in the following manner:

" CxHy0 = b1/2

" CxHy1 = b2

" CxHy2 = -a1/2

" CxHy3 = -a2

" CxHy4 = b0/2

The x represents the channel and the y the biquad number. For example C3H41 is the b0/2 coefficient in the fourth biquad for channel 3.

Figure 49. Biquad filter

Z -1

8.2 Pre-scale

The pre-scale block, which precedes the first biquad, is used for attenuation when filters are designed that boost frequencies above 0 signed multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, all pre-scale factors are set to 0x7FFFFF.

8.3 Post-scale

The STA323W provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. The post-scale block is a 24-bit signed fractional multiplier. The scale factor for this multiplier is loaded into RAM using the same

C registers as the biquad coefficients and the mix. All channels can use the same settings

as channel 1 by setting the post-scale link bit.

b0/2

b1/2

b2 -a2

dBFS. The Pre-Scale block is a single 28-bit

Z -1

-a1/2

Z -1

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User-programmable settings STA323W

8.4 Mix/bass management

The STA323W provides one post-EQ mixing block per channel. Each channel has two mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the two channels of input to the mixing block. These coefficients are accessible via the User Controlled Coefficient RAM described below. The mix coefficients expressed as 24-bit signed, fractional numbers in the range +1.0 (8388607) to -1.0 (-8388608), are used to provide three channels of output from two channels of filtered input.

Figure 50. Mix/bass management block diagram

Channel #1

from EQ

Channel #2 from EQ

C1MX1

C1MX2

C2MX1

C2MX2

C3MX1

C3MX2

User defined mix coefficients

High pass

filter

High pass

filter

Low pass

filter

Crossover frequency determined by XO setting. User defined when XO = 000

Channel #1

to GC/vol

Channel #2

to GC/vol

Channel #3 to GC/vol

After mixing, STA323W also permits the implementation of crossover filters on all channels corresponding to 2.1 bass management operation. Channels 1 and 2 use a 1st order, highpass filter and channel 3 uses a 2nd-order low-pass filter corresponding to the setting of the XO bits of I

C register 0x0C. If XO = 000, user specified crossover filters are used.

By default these coefficients correspond to pass-through. However, the user can write these coefficients in a similar way as the EQ biquads. When user-defined setting is selected, the user can only write 2nd-order crossover filters. This output is then passed on to the Volume and Limiter block.

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STA323W User-programmable settings

8.5 Calculating 24-bit signed fractional numbers from a dB value

The pre-scale, mixing, and post-scale functions of the STA323W use 24-bit signed fractional multipliers to attenuate signals. These attenuations can also invert the phase and therefore range in value from -1 to +1.

It is possible to calculate the coefficient to use for a given negative dB value (attenuation) using the equations following.

" non-inverting phase numbers 0 to +1:

– coefficient = round(8388607 * 10

" inverting phase numbers 0 to -1:

– coefficient = 16777216 - round(8388607 * 10

(dB/20)

)

(dB/20)

)

As can be seen by the preceding equations, the value for positive phase 0 dB is 0x7FFFFF and the value for negative phase 0 dB is 0x800000.

8.6 User defined coefficient RAM

8.6.1 Coefficient address register 1 (address 0x16)

D7 D6 D5 D4 D3 D2 D1 D0

CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

00000000

8.6.2 Coefficient b1data register bits 23:16 (address 0x17)

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

8.6.3 Coefficient b1data register bits 15:8 (address 0x18)

D7 D6 D5 D4 D3 D2 D1 D0

C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

00000000

8.6.4 Coefficient b1data register bits 7:0 (address 0x19)

D7 D6 D5 D4 D3 D2 D1 D0

C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

00000000

8.6.5 Coefficient b2 data register bits 23:16 (address 0x1A)

D7 D6 D5 D4 D3 D2 D1 D0

C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

00000000

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User-programmable settings STA323W

8.6.6 Coefficient b2 data register bits 15:8 (address 0x1B)

D7 D6 D5 D4 D3 D2 D1 D0

C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

00000000

8.6.7 Coefficient b2 data register bits 7:0 (address 0x1C)

D7 D6 D5 D4 D3 D2 D1 D0

C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

00000000

8.6.8 Coefficient a1 data register bits 23:16 (address 0x1D)

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

8.6.9 Coefficient a1 data register bits 15:8 (address 0x1E)

D7 D6 D5 D4 D3 D2 D1 D0

C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

00000000

8.6.10 Coefficient a1 data register bits 7:0 (address 0x1F)

D7 D6 D5 D4 D3 D2 D1 D0

C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

00000000

8.6.11 Coefficient a2 data register bits 23:16 (address 0x20)

D7 D6 D5 D4 D3 D2 D1 D0

C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

00000000

8.6.12 Coefficient a2 data register bits 15:8 (address 0x21)

D7 D6 D5 D4 D3 D2 D1 D0

C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

00000000

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STA323W User-programmable settings

8.6.13 Coefficient a2 data register bits 7:0 (address 0x22)

D7 D6 D5 D4 D3 D2 D1 D0

C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

00000000

8.6.14 Coefficient b0 data register bits 23:16 (address 0x23)

D7 D6 D5 D4 D3 D2 D1 D0

C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

00000000

8.6.15 Coefficient b0 data register bits 15:8 (address 0x24)

D7 D6 D5 D4 D3 D2 D1 D0

C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

00000000

8.6.16 Coefficient b0 data register bits 7:0 (address 0x25)

D7 D6 D5 D4 D3 D2 D1 D0

C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

00000000

8.6.17 Coefficient write control register (address 0x26)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved RA R1 WA W1

00000000

Coefficients for EQ, Mix and Scaling are handled internally in the STA323W via RAM. Access to this RAM is available to the user via an I registers are dedicated to this function. The first register contains base address of the coefficient: five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the reading or writing of the coefficients to RAM. The following are instructions for reading and writing coefficients.

C register interface. A collection of I2C

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User-programmable settings STA323W

8.7 Reading and writing coefficients

8.7.1 Reading a coefficient from RAM

1. Write 8-bits of address to I2C register 0x16.

2. Write 1 to bit R1 (D2) of I

3. Read top 8-bits of coefficient in I

4. Read middle 8-bits of coefficient in I

5. Read bottom 8-bits of coefficient in I

8.7.2 Reading a set of coefficients from RAM

1. Write 8-bits of address to I2C register 0x16.

2. Write 1 to bit RA (D3) of I

3. Read top 8-bits of coefficient in I

4. Read middle 8-bits of coefficient in I

5. Read bottom 8-bits of coefficient in I

6. Read top 8-bits of coefficient b2 in I

7. Read middle 8-bits of coefficient b2 in I

8. Read bottom 8-bits of coefficient b2 in I

9. Read top 8-bits of coefficient a1 in I

10. Read middle 8-bits of coefficient a1 in I

11. Read bottom 8-bits of coefficient a1 in I

12. Read top 8-bits of coefficient a2 in I

13. Read middle 8-bits of coefficient a2 in I

14. Read bottom 8-bits of coefficient a2 in I

15. Read top 8-bits of coefficient b0 in I

16. Read middle 8-bits of coefficient b0 in I

17. Read bottom 8-bits of coefficient b0 in I

C register 0x26.

C address 0x17.

C address 0x18.

C address 0x19.

C register 0x26.

C address 0x17.

C address 0x18.

C address 0x19.

C address 0x1A.

C address 0x1D.

C address 0x20.

C address 0x23.

C address 0x1B.

C address 0x1C.

C address 0x1E.

C address 0x1F.

C address 0x21.

C address 0x22.

C address 0x24.

C address 0x25.

8.7.3 Writing a single coefficient to RAM

1. Write 8-bits of address to I2C register 0x16.

2. Write top 8-bits of coefficient in I

3. Write middle 8-bits of coefficient in I

4. Write bottom 8-bits of coefficient in I

5. Write 1 to W1 bit in I

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C address 0x26.

C address 0x17.

C address 0x18.

C address 0x19.

STA323W User-programmable settings

8.7.4 Writing a set of coefficients to RAM

1. Write 8-bits of starting address to I2C register 0x16.

2. Write top 8-bits of coefficient b1 in I

3. Write middle 8-bits of coefficient b1 in I

4. Write bottom 8-bits of coefficient b1 in I

5. Write top 8-bits of coefficient b2 in I

6. Write middle 8-bits of coefficient b2 in I

7. Write bottom 8-bits of coefficient b2 in I

8. Write top 8-bits of coefficient a1 in I

9. Write middle 8-bits of coefficient a1 in I

10. Write bottom 8-bits of coefficient a1 in I

11. Write top 8-bits of coefficient a2 in I

12. Write middle 8-bits of coefficient a2 in I

13. Write bottom 8-bits of coefficient a2 in I

14. Write top 8-bits of coefficient b0 in I

15. Write middle 8-bits of coefficient b0 in I

16. Write bottom 8-bits of coefficient b0 in I

17. Write 1 to WA bit in I

C address 0x26.

C address 0x17.

C address 0x18.

C address 0x19.

C address 0x1A.

C address 0x1B.

C address 0x1C.

C address 0x1D.

C address 0x1E.

C address 0x1F.

C address 0x20.

C address 0x21.

C address 0x22.

C address 0x23.

C address 0x24.

C address 0x25.

The mechanism for writing a set of coefficients to RAM provides a method of simultaneously updating the five coefficients corresponding to a given biquad (filter) to avoid possible unpleasant acoustic side-effects. When using this technique, the 8-bit address specifies the address of the biquad b1 coefficient (for example 0, 5, 10, 15, …, 45 decimal), and the STA323W generates the RAM addresses as an offsets from this base value to write the complete set of coefficient data.

Table 70. RAM block for biquads, mixing, and scaling

Index (decimal) Index (hex) Coefficient Default

0 0x00

1 0x01 C1H11 (b2) 0x000000

2 0x02 C1H12 (a1/2) 0x000000

3 0x03 C1H13 (a2) 0x000000

4 0x04 C1H14 (b0/2) 0x400000

5 0x05 Channel 1 - biquad 2 C1H20 0x000000

... ... ... ... ...

19 0x13 Channel 1 - biquad 4 C1H44 0x400000

20 0x14

21 0x15 C2H11 0x000000

……… ……

39 0x27 Channel 2 - biquad 4 C2H44 0x400000

Channel 1 - biquad 1

Channel 2 - biquad 1

C1H10 (b1/2) 0x000000

C2H10 0x000000

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User-programmable settings STA323W

Table 70. RAM block for biquads, mixing, and scaling (continued)

Index (decimal) Index (hex) Coefficient Default

40 0x28

41 0x29 C12H1 (b2) 0x000000

42 0x2A C12H2 (a1/2) 0x000000

High-pass 2 filter

For XO = 000

-order

C12H0 (b1/2) 0x000000

43 0x2B C12H3 (a2) 0x000000

44 0x2C C12H4 (b0/2) 0x400000

45 0x2D

46 0x2E C12L1 (b2) 0x000000

47 0x2F C12L2 (a1/2) 0x000000

Low-Pass 2 For XO = 000

-order filter

C12L0 (b1/2) 0x000000

48 0x30 C12L3 (a2) 0x000000

49 0x31 C12L4 (b0/2) 0x400000

50 0x32 Channel 1 - post scale C1PreS 0x7FFFFF

51 0x33 Channel 2 - post scale C2PreS 0x7FFFFF

52 0x34 Channel 1 - post scale C1PstS 0x7FFFFF

53 0x35 Channel 2 - post scale C2PstS 0x7FFFFF

54 0x36 Channel 3 - post scale C3PstS 0x7FFFFF

55 0x37

Thermal warning - post scale

TWPstS 0x5A9DF7

56 0x38 Channel 1 - mix 1 C1MX1 0x7FFFFF

57 0x39 Channel 1 - mix 2 C1MX2 0x000000

58 0x3A Channel 2 - mix 1 C2MX1 0x000000

59 0x3B Channel 2 - mix 2 C2MX2 0x7FFFFF

60 0x3C Channel 3 - mix 1 C3MX1 0x400000

61 0x3D Channel 3 - mix 2 C3MX2 0x400000

62 0x3E Unused

63 0x3F Unused

8.8 Variable max power correction (address 0x27-0x28)

The MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.

D7 D6 D5 D4 D3 D2 D1 D0

MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

00101101

MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

11000000

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STA323W User-programmable settings

8.9 Fault detect recovery (address 0x2B - 0x2C)

FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is active, the TRISTATE output immediately goes low and is held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C specifies approximately 0.1 ms.

D7 D6 D5 D4 D3 D2 D1 D0

FRDC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

00000000

FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

00001100

8.10 Status indicator register (address 0x2D)

D7 D6 D5 D4 D3 D2 D1 D0

PLULL Reserved Reserved Reserved Reserved Reserved FAULT TWARN

00000011

STATUS register bits serve the purpose of communicating the detected error or warning condition to the user. This is a read-only register and writing to this register would not be of any consequence.

8.10.1 Thermal warning indicator

Table 71. Thermal warning indicator

Bit R/W RST Name Description

0RO1RWRAN

If the power stage thermal operating conditions are exceeded, the thermal warning indicator transmits a signal to the digital logic block to initiate a corrective procedure. This register bit is set to 0 to indicate a thermal warning and it reverts back to its default state as soon as the cause of the thermal warning has been corrected.

8.10.2 Fault detect indicator

Table 72. Fault detect indicator

Bit R/W RST Name Description

1RO1FAULT

As soon as the power stage issues a Fault error signal, thereby initiating the Fault recovery procedure described in Section 8.9, this register bit is set to 0 to indicate the error to the user. As soon as the fault condition (over-current or thermal) is corrected, this bit is reset back to its default state.

0: thermal warning detected 1: normal operation (no thermal warning)

0: fault issued from the power stage 1: normal operation (no fault)

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User-programmable settings STA323W

8.10.3 PLL unlock indicator

Table 73. PLL unlock indicator

Bit R/W RST Name Description

7RO0PLLUL

0: normal operation (PLL is in a locked state) 1: PLL unlock is detected (due to probable clock loss)

Under normal conditions (with the correct clock) the PLL is locked into an internal clocking frequency. However, if the clock is insufficient or if it is abruptly lost, the PLL lock state is lost and this information is relayed to the user via setting the PLLUL bit of the Status register to 1. As soon as the PLL reverts back to a locked state, this bit is set to 0.

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STA323W Package information

9 Package information

Figure 51. PowerSO-36 slug down outline drawing

0096119 rev D

RE 1:

73/77

Package information STA323W

Table 74. PowerSO-36 slug down dimensions

mm inch

Symbol

Min Typ Max Min Typ Max

A--3.60--0.142

a1 0.10 - 0.30 .004 - .012

a2--3.30--0.130

a3 0 - 0.10 0 - .004

b 0.22 - 0.38 0.009 - 0.015

c 0.23 - 0.32 0.009 - 0.013

D 15.80 - 16.00 0.622 - 0.630

D1 9.40 - 9.80 0.370 - 0.386

E 13.90 - 14.50 0.547 - 0.571

E1 10.90 - 11.10 0.429 - 0.437

E2--2.90--0.114

E3 5.80 - 6.20 0.228 - 0.244

e - 0.65 - - 0.026 -

e3 - 11.05 - - 0.435 -

G0-0.100-0.004

H 15.50 - 15.90 0.610 - 0.626

h--1.10--0.043

L 0.80 - 1.10 0.031 - 0.043

M 2.25 - 2.60 0.089 - 0.102

N - - 10 degrees - - 10 degrees

R - 0.30 - - 0.012 -

s--8 degrees--8 degrees

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

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STA323W Trademarks and other acknowledgements

10 Trademarks and other acknowledgements

DDX is a registered trademark of Apogee Technology Inc.

AutoModes is a trademark of Apogee Technology Inc.

ECOPACK is a registered trademark of STMicroelectronics.

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Revision history STA323W

11 Revision history

Table 75. Document revision history

Date Revision Changes

01-Jul-2005 1.0 Initial release.

02-Jan-2006 2.0 Modified Configuration Register A (addr 0x00).

02-Feb-2006 3.0 Modified the ordering part numbers.

Added new chapters.

08-Jun-2006 4.0

15-Nov-2006 5.0 Update into latest template.

22-May-2008 6

Updated Electrical characteristics curves . Modified the minimum value of Vcc paramter.

Updated pin 1 connection. General presentation revision.

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STA323W

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ST STA323W User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Table 1. Device summary

Contents

List of tables

List of figures

1 Description

Figure 1. Block diagram

Figure 2. Channel signal flow diagram through the digital core

1.1 EQ processing

Figure 3. Channel signal flow diagram through the EQ block

1.2 Output options

Figure 4. Output power stage configurations

2 Applications

Table 2. Component selection “Table A” - full-bridge operation

Table 3. Component selection "Table B" - binary half-bridge operation

Table 4. Component selection "Table C" - mono operation

Figure 5. Schematic for 2 (half-bridge) channels + 1 (full-bridge) channel

Figure 6. Power schematic for 2 (full-bridge) channels

Figure 7. Power schematic for 1 mono parallel channel

3 Pin out

3.1 Pin numbering

Figure 8. Package pins (viewed from top of device)

3.2 Pin description

4 Electrical specifications

Table 6. Absolute maximum ratings

Table 7. Thermal data

Table 8. Recommended DC operating conditions

4.1 General interface specifications

Table 9. General interface electrical characteristics

4.2 DC electrical specifications (3.3 V buffers)

Table 10. DC electrical characteristics

4.3 Power electrical specifications

4.4 Timing specifications

Table 12. Timing characteristics

Figure 9. Test circuit 1

Figure 10. Test circuit 2

4.5 Power supply and control sequencing

Figure 11. Recommended power up and power down sequence

5 Electrical characteristics curves

5.1 Output power against supply voltage

Figure 12. Stereo mode - output power vs. supply voltage, THD+N = 10%

Figure 13. Output power vs. supply for stereo bridge, THD+N=1%

Figure 14. Half-bridge binary mode output power vs. supply, THD+N=10%

Figure 15. Half-bridge binary mode output power vs. supply voltage, THD+N=1%

5.2 Audio performance

Figure 16. Typical efficiency

Figure 17. Typical frequency response

Figure 18. FFT -60 dB, 1 kHz output

Figure 19. FFT inter-modulation distortion 19 kHz and 20 kHz

5.2.2 Stereo mode, operation with VCC = 18.5 V

Figure 21. Channel separation, 1 W, BTL stereo mode

Figure 22. THD vs. output power, BTL, 1 kHz

Figure 23. THD vs. frequency, 1 W output, stereo mode

Figure 24. THD vs. frequency, BTL, 16 W output

Figure 31. PSRR BTL, 500 mV ripple

5.2.3 Half-bridge binary mode, operation with Vcc = 18.5 V

Figure 32. Frequency response, 1 W, binary half-bridge mode

Figure 33. Channel separation, 1 W, half bridge binary

Figure 34. THD+N vs. output power, single ended, 1 kHz, half-bridge binary

Figure 35. THD vs. frequency, single ended, 1 W

Figure 36. THD vs. frequency, single ended, 8 W

Figure 43. PSRR single ended, 500 mV ripple

6 I2C bus specification

6.1 Communication protocol

6.2 Device addressing

6.3 Write operation

Figure 44. I2C write procedure

6.4 Read operation

Figure 45. I2C read procedure

7 Register descriptions

7.1 Configuration register A (address 0x00)

7.1.1 Master clock select

Table 14. Master clock select

Table 15. IR and MCS settings for input sample rate and clock rate

7.1.2 Interpolation ratio select

Table 16. Interpolation ratio select