ST STA323W User Manual
Features
STA323W
2.1-channel high-efficiency digital audio system
! Wide supply voltage range (10 V - 36 V)
! Three power output configurations
– 2x10W + 1 x20W
–2x20W
–1x40W
! Thermal protection
! Under-voltage protection
! Short-circuit protection
! PowerSO-36 slug down package
! 2.1 channels of 24-bit DDX
100-dB SNR and dynamic range
!
! 32 kHz to 192 kHz input sample rates
! Digital gain/attenuation +48 dB to -80 dB in
®
0.5-dB steps
! Four 28-bit user programmable biquads (EQ)
per channel
2
! I
C control
! 2-channel I
! Individual channel and master gain/attenuation
! Individual channel and master soft and hard
2
S input data interface
mute
! Individual channel volume and EQ bypass
! DDX
! Bass/treble tone control
! Dual independent programmable
®
POP free operation
limiters/compressors
! AutoModes™ settings for:
– 32 preset EQ curves
– 15 preset crossover settings
– Auto volume controlled loudness
– 3 preset volume curves
– 2 preset anti-clipping modes
– Preset night-time listening mode
– Preset TV AGC
PowerSO-36
(slug down)
! Input and output channel mapping
! AM noise-reduction and PWM frequency
shifting modes
! Soft volume update and muting
! Auto zero detect and invalid input detect
muting selectable DDX
®
ternary or binary
PWM output plus variable PWM speeds
! Selectable de-emphasis
! Post-EQ user programmable mix with default
2.1 bass-management settings
! Variable max power correction for lower
full-power THD
! Four output routing configurations
! Selectable clock input ratio
! 96 kHz internal processing sample rate, 24 to
28-bit precision
! Video application supports 576 * fs input mode
Table 1. Device summary
Order code Package
STA323W PowerSO-36 (slug down)
STA323W13TR PowerSO-36 in tape & reel
May 2008 Rev 6 1/77
www.st.com
1
Contents STA323W
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 EQ processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 General interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 DC electrical specifications (3.3 V buffers) . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Output power against supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Audio performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2.1 Stereo mode, operation with VCC = 26 V, 8 Ω load . . . . . . . . . . . . . . . . 23
5.2.2 Stereo mode, operation with V
5.2.3 Half-bridge binary mode, operation with Vcc = 18.5 V . . . . . . . . . . . . . 28
6I
2
C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
= 18.5 V . . . . . . . . . . . . . . . . . . . . . . 24
CC
7 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 Configuration register A (address 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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7.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.1.3 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1.4 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1.5 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 Configuration register B (address 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.1 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.2 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2.3 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.3 Configuration register C (address 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.1 DDX® power-output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.2 DDX
®
variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4 Configuration register D (address 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.4.1 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.4.2 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.4.3 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.4.4 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4.5 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4.6 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 45
7.4.7 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.5 Configuration register E (address 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5.1 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5.2 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5.3 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5.4 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5.5 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.5.6 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.6 Configuration register F (address 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.6.1 Output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.7 Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.7.1 Master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.7.2 Channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.7.3 Volume description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.8 AutoModes™ registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.8.1 AutoModes™ EQ, volume, GC (address 0x0B) . . . . . . . . . . . . . . . . . . . 52
7.8.2 AutoModes™ AM/pre-scale/bass management scale (address 0x0C) . 53
7.8.3 Preset EQ settings (address 0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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Contents STA323W
7.9 Channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.9.1 Channel 1 configuration (address 0x0E) . . . . . . . . . . . . . . . . . . . . . . . . 55
7.9.2 Channel 2 configuration (address 0x0F) . . . . . . . . . . . . . . . . . . . . . . . . 55
7.9.3 Channel 3 configuration (address 0x10) . . . . . . . . . . . . . . . . . . . . . . . . 56
7.10 Tone control (address 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.11 Dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.11.1 Limiter 1 attack/release threshold (address 0x12) . . . . . . . . . . . . . . . . . 57
7.11.2 Limiter 1 attack/release threshold (address 0x13) . . . . . . . . . . . . . . . . . 57
7.11.3 Limiter 2 attack/release rate (address 0x14) . . . . . . . . . . . . . . . . . . . . . 57
7.11.4 Limiter 2 attack/release threshold (address 0x15) . . . . . . . . . . . . . . . . . 58
7.11.5 Dynamics control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.11.6 Anti-clipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.11.7 Dynamic range compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8 User-programmable settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.1 EQ - biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.2 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.3 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.4 Mix/bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.5 Calculating 24-bit signed fractional numbers from a dB value . . . . . . . . . 65
8.6 User defined coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.6.1 Coefficient address register 1 (address 0x16) . . . . . . . . . . . . . . . . . . . . 65
8.6.2 Coefficient b1data register bits 23:16 (address 0x17) . . . . . . . . . . . . . . 65
8.6.3 Coefficient b1data register bits 15:8 (address 0x18) . . . . . . . . . . . . . . . 65
8.6.4 Coefficient b1data register bits 7:0 (address 0x19) . . . . . . . . . . . . . . . . 65
8.6.5 Coefficient b2 data register bits 23:16 (address 0x1A) . . . . . . . . . . . . . 65
8.6.6 Coefficient b2 data register bits 15:8 (address 0x1B) . . . . . . . . . . . . . . 66
8.6.7 Coefficient b2 data register bits 7:0 (address 0x1C) . . . . . . . . . . . . . . . 66
8.6.8 Coefficient a1 data register bits 23:16 (address 0x1D) . . . . . . . . . . . . . 66
8.6.9 Coefficient a1 data register bits 15:8 (address 0x1E) . . . . . . . . . . . . . . 66
8.6.10 Coefficient a1 data register bits 7:0 (address 0x1F) . . . . . . . . . . . . . . . 66
8.6.11 Coefficient a2 data register bits 23:16 (address 0x20) . . . . . . . . . . . . . 66
8.6.12 Coefficient a2 data register bits 15:8 (address 0x21) . . . . . . . . . . . . . . 66
8.6.13 Coefficient a2 data register bits 7:0 (address 0x22) . . . . . . . . . . . . . . . 67
8.6.14 Coefficient b0 data register bits 23:16 (address 0x23) . . . . . . . . . . . . . 67
8.6.15 Coefficient b0 data register bits 15:8 (address 0x24) . . . . . . . . . . . . . . 67
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8.6.16 Coefficient b0 data register bits 7:0 (address 0x25) . . . . . . . . . . . . . . . 67
8.6.17 Coefficient write control register (address 0x26) . . . . . . . . . . . . . . . . . . 67
8.7 Reading and writing coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.7.1 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.7.2 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . 68
8.7.3 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.7.4 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.8 Variable max power correction (address 0x27-0x28) . . . . . . . . . . . . . . . . 70
8.9 Fault detect recovery (address 0x2B - 0x2C) . . . . . . . . . . . . . . . . . . . . . . 71
8.10 Status indicator register (address 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.10.1 Thermal warning indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.10.2 Fault detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.10.3 PLL unlock indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 75
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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List of tables STA323W
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Component selection “Table A” - full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Component selection "Table B" - binary half-bridge operation . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Component selection "Table C" - mono operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Power electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 15. IR and MCS settings for input sample rate and clock rate . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 20. Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 21. Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 22. Supported serial audio input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. Serial input data timing characteristics (fs = 32 to 192 kHz). . . . . . . . . . . . . . . . . . . . . . . . 42
Table 24. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 25. Channel input mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 26. DDX® power-output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 27. DDX® output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 28. DDX® compensating pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 29. High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 30. De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 31. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 32. Post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 33. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 34. Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 35. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 36. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 37. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 38. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 39. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 40. PWM output speed selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 41. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 42. Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 43. Output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 44. Output configuration selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 45. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 46. Binary clock loss detection enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 47. Auto-EAPD on clock loss enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 48. Software power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6/77
STA323W List of tables
Table 49. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 50. Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 51. Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 52. AutoModes™ EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 53. AutoModes™ volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 54. AutoModes™ gain compression/limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 55. AMPS - AutoModes™ auto pre scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 56. AutoModes™ AM switching enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 57. AutoModes™ AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 58. AutoModes™ crossover setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 59. Crossover frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 60. Preset EQ selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 61. Channel Limiter Mapping Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 62. Channel PWM output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 63. Tone control boost/cut selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 64. Limiter attack rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 65. Limiter release rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 66. Limiter attack - threshold selection (AC-mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 67. Limiter release threshold selection (AC-mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 68. Limiter attack - threshold selection (DRC-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 69. Limiter release threshold selection (DRC-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 70. RAM block for biquads, mixing, and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 71. Thermal warning indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 72. Fault detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 73. PLL unlock indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 74. PowerSO-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 75. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7/77
List of figures STA323W
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. Channel signal flow diagram through the digital core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Channel signal flow diagram through the EQ block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Output power stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Schematic for 2 (half-bridge) channels + 1 (full-bridge) channel . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Power schematic for 2 (full-bridge) channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Power schematic for 1 mono parallel channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Package pins (viewed from top of device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Recommended power up and power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Stereo mode - output power vs. supply voltage, THD+N = 10% . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Output power vs. supply for stereo bridge, THD+N=1% . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Half-bridge binary mode output power vs. supply, THD+N=10% . . . . . . . . . . . . . . . . . . . 22
Figure 15. Half-bridge binary mode output power vs. supply voltage, THD+N=1% . . . . . . . . . . . . . . 22
Figure 16. Typical efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Typical frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. FFT -60 dB, 1 kHz output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19. FFT inter-modulation distortion 19 kHz and 20 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20. Frequency response, 1 W, BTL, 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21. Channel separation, 1 W, BTL stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 22. THD vs. output power, BTL, 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 23. THD vs. frequency, 1 W output, stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 24. THD vs. frequency, BTL, 16 W output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25. FFT 0 dBFS 1 kHz, 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 26. FFT 0 dBFS 1 kHz, 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 27. FFT 0 dBFS 1 kHz, 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 28. FFT -60 dBFS 1 kHz, 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 29. FFT -60 dBFS 1 kHz, 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 30. FFT -60 dBFS 1 kHz, 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 31. PSRR BTL, 500 mV ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 32. Frequency response, 1 W, binary half-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33. Channel separation, 1 W, half bridge binary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 34. THD+N vs. output power, single ended, 1 kHz, half-bridge binary . . . . . . . . . . . . . . . . . . . 29
Figure 35. THD vs. frequency, single ended, 1 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. THD vs. frequency, single ended, 8 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 37. FFT 0 dB, 1 kHz, single ended, 2 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 38. FFT 0 dB, 1 kHz, single ended, 3 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 39. FFT 0 dB, 1 kHz, single ended, 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 40. FFT -60 dB, single ended, 1 kHz, 2 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 41. FFT -60 dB, single ended, 1 kHz, 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 42. FFT -60 dB, single ended, 1 kHz, 3 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 43. PSRR single ended, 500 mV ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 44. I
Figure 45. I
Figure 46. General serial input and output formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 47. Serial input and data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 48. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2
C write procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2
C read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8/77
STA323W List of figures
Figure 49. Biquad filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 50. Mix/bass management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 51. PowerSO-36 slug down outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9/77
Description STA323W
1 Description
The STA323W is a single-chip audio system comprising digital audio processing, digital
amplifier control and a DDX
®
power-output stage. The STA323W uses all-digital
amplification to provide high-power, high-quality and high-efficiency.
The STA323W power section consists of four independent half-bridges. These can be
configured, by digital control, to operate in the following modes.
" Tw o channels, provided by two half-bridges, and a single full-bridge giving up to
2 x 10 W + 1 x 20 W of power output.
" Two channels, provided by two full-bridges, giving up to 2 x 20 W of power.
" A single, parallel, full-bridge channel capable of high-current operation and giving
1 x 40W output.
The STA323W also provides a full set of digital processing features. This includes up to four
programmable 28-bit biquads (EQ) per channel, and bass and treble tone control.
AutoModes™ enable a time-to-market advantage by substantially reducing the amount of
software development needed for specific functions. These includes auto volume loudness,
preset volume curves and preset EQ settings. New advanced AM radio-interference
reduction modes are also provided.
The serial audio data input interface accepts all existing formats, including the I
Three channels of DDX
®
processing are provided. This high-quality conversion from PCM
2
S.
audio to DDX patented 3-state PWM switching provides over 100 dB of SNR and dynamic
range.
Figure 1. Block diagram
SDA
LRCKI
BICKI
SDI_12
SCL
I2C
Serial data
input, channel
mapping and
resampling
Power d own
System control
System timing
CLK
Audio EQ, mix,
crossover,
volume, limiter
processing
DDX
processing
TWARN
Powe r d own
power stage
FAU LT
Figure 2. Channel signal flow diagram through the digital core
2
I
S
input
Channel
mapping
Re-sampling
ED
processing
Mix
Crossover
filter
Vol um e
limiter
Interpol
Quad
half-bridge
4x
EAPD
DDX
OUT1A
OUT1B
OUT2A
OUT2B
DDX
output
10/77
STA323W Description
1.1 EQ processing
Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ
processing block. In these blocks, up to four user-defined Biquads can be applied to each of
the two channels.
Pre-scaling, DC-blocking high-pass, de-emphasis, bass, and tone control filters can also be
implemented by means of configuration parameter settings.
The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB
bit to 1. The CxEQBP bits can also be used to bypass the EQ functionality on a per channel
basis. Figure 3 shows the internal signal flow through the EQ block.
Figure 3. Channel signal flow diagram through the EQ block
Re-sampled
input
pre-scale
High pass
If HPB= 0
1.2 Output options
Figure 4. Output power stage configurations
Half
bridge
Half
bridge
Half
bridge
Half
bridge
Half
bridge
Half
bridge
Half
bridge
Half
bridge
filter
OUT1A
OUT1B
OUT2A
OUT2B
OUT1A
OUT1B
OUT2A
OUT2B
BQ#1
BQ#2 BQ#3 BQ#4
4 biquads
User defined if AMEQ = 00
Preset EQ if AMEQ = 01
Auto loudness if AMEQ = 10
If DSPB = 0 and CxEQB = 0
Channel 1
Channel 2
Channel 1
Channel 2
Channel 3
2-channel (full bridge) configuration,
register bits OCFG[1:0] = 00
2.1-channel configuration,
register bits OCFG[1:0] = 01
De-
emphasis
If DEMP = 1
Bass
filter
If CxTCB = 0
BTC: bass boost/cut
TTC: treble boost/cut
Tr eb l e
filter
To
mix
Half
bridge
Half
bridge
Half
bridge
Half
bridge
OUT1A
OUT1B
OUT2A
OUT2B
1-channel mono-parallel configuration,
register bits OCFG[1:0] = 11
Channel 3
The setup register is Configuration
register F (address 0x05) on page 48
11/77
Applications STA323W
2 Applications
Table 2. Component selection “Table A” - full-bridge operation
Load Inductor Capacitor
4 Ω 10 µH1.0µF
6 Ω 15 µH 470 nF
8 Ω 22 µH 470 nF
Table 3. Component selection "Table B" - binary half-bridge operation
Load Inductor Capacitor
4 Ω 22 µH 680 nF
6 Ω 33 µH 470 nF
8 Ω 47 µH 390 nF
Table 4. Component selection "Table C" - mono operation
Load Inductor Capacitor
2 Ω 4.7 µH2.0µF
3 Ω 6.8 µH1.0µF
4 Ω 10 µH1.0µF
Figure 5. Schematic for 2 (half-bridge) channels + 1 (full-bridge) channel
VCC_SIGN
VSS
VDD
GND
BICKI
LRCKI
SDI
VDDA
GNDA
XTI
PLL_FILTER
RESERVED
SDA
SCL
RESET
CONFIG
VL
VDD_REG
STA323W
SUB_GND
SUB_GND
OUT2B
VCC2B
GND2B
GND2A
VCC2A
OUT2A
OUT1B
VCC1B
GND1B
GND1A
VCC1A
OUT1A
GND_CLEAN
GND_REG
N.C.
N.C.
N.C.
12/77
STA323W Applications
Figure 6. Power schematic for 2 (full-bridge) channels
VCC_SIGN
VSS
VDD
GND
BICKI
LRCKI
SDI
VDDA
GNDA
XTI
PLL_FILTER
RESERVED
SDA
SCL
RESET
CONFIG
VL
VDD_REG
SUB_GND
SUB_GND
OUT2B
VCC2B
GND2B
GND2A
VCC2A
OUT2A
OUT1B
VCC1B
GND1B
GND1A
VCC1A
OUT1A
GND_CLEAN
GND_REG
N.C.
N.C.
N.C.
STA323W
Figure 7. Power schematic for 1 mono parallel channel
VCC_SIGN
VSS
VDD
GND
BICKI
LRCKI
SDI
VDDA
GNDA
XTI
PLL_FILTER
RESERVED
SDA
SCL
RESET
CONFIG
VL
VDD_REG
STA323W
SUB_GND
SUB_GND
OUT2B
VCC2B
GND2B
GND2A
VCC2A
OUT2A
OUT1B
VCC1B
GND1B
GND1A
VCC1A
OUT1A
GND_CLEAN
GND_REG
N.C.
N.C.
N.C.
13/77
Pin out STA323W
3 Pin out
3.1 Pin numbering
Figure 8. Package pins (viewed from top of device)
Table 5. Pin list
SUB_GND
N.C.
OUT2B
VCC2B
N.C.
GND2B
GND2A
VCC2A
OUT2A
OUT1B
VCC1B
GND1B
GND1A
N.C.
VCC1A
OUT1A
GND_CLEAN
GND_REG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Type Name Description
1 I/O SUB_GND Ground
2 N.C. N.C. Not connected
3 O OUT2B Output half bridge 2B
4 I/O VCC2B Positive supply
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VCC_SIGN
VSS
VDD
GND
BICKI
LRCKI
SDI
VDDA
GNDA
XTI
PLL_FILTER
RESERVED
SDA
SCL
RESET
CONFIG
VL
VDD_REG
5 N.C. N.C. Not connected
6 I/O GND2B Negative supply
7 I/O GND2A Negative supply
8 I/O VCC2A Positive supply
9 O OUT2A Output half bridge 2A
10 O OUT1B Output half bridge 1B
11 I/O VCC1B Positive supply
12 I/O GND1B Negative supply
13 I/O. GND1A Negative supply
14 N.C. N.C. Not connected
15 I/O VCC1A Positive supply
16 O OUT1A Output half bridge 1A
14/77
STA323W Pin out
Table 5. Pin list (continued)
Pin Type Name Description
17 I/O GND_CLEAN Reference ground
18 I/O GND_REG Substrate ground
19 I/O VDD_REG Logic supply
20 I/O VL Logic supply to power section
21 I CONFIG Logic levels
22 I RESET Reset
2
23 I SCL I
24 I/O SDA I
25 - RESERVED Reserved test pin must be connected to ground
26 I PLL_FILTER Connection to PLL filter
27 I XTI PLL input clock
28 I/O GNDA Analog ground
29 I/O VDDA Analog supply 3.3
30 I SDI_12 I
31 I/O LRCKI I
32 I BICKI I
33 I/O GND Digital ground
34 I/O VDD Digital supply 3.3 V
C serial clock
2
C serial data
2
S serial data channels 1 and 2
2
S left/right clock,
2
S serial clock
35 I/O VSS 5 V regulator referred to Vcc
36 I/O VCC_SIGN 5 V regulator referred to ground
3.2 Pin description
OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3)
The half-bridge PWM outputs 1A, 1B, 2A and 2B provide the inputs signals to the speakers.
RESET (pin 22)
Driving RESET low sets all outputs low and returns all register settings to their default
(reset) values. The reset is asynchronous to the internal clock.
SDA, SCL (pins 24, 23)
The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification
(See Chapter 6 on page 33.) Fast-mode (400 kB/s) I
VDDA, GNDA (pins 29,28)
The phase locked loop power is applied here. This +3.3V supply must be well decoupled
and filtered for good noise immunity since the audio performance of the device depends
upon the PLL circuit.
2
C communication is supported.
15/77
Pin out STA323W
CLK (pin 27)
This is the master clock input used by the digital core. The master clock must be an integer
multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz
(256 * fs) for a 48kHz sample rate; it is the default setting at power-up. Care must be taken
to provide the device with the nominal system clock frequency; over-clocking the device may
result in anomalous operation, such as inability to communicate.
PLL_FILTER (pin 26)
This is the connection for the external filter components for the PLL loop compensation.
Refer to the schematic diagram Figure 7: Power schematic for 1 mono parallel channel on
page 13 for the recommended circuit.
BICKI (pin 32)
The serial or bit clock input is for framing each data bit. The bit clock frequency is typically
64 * fs using I
2
S serial format.
SDI (pin 30)
This is the serial data input where PCM audio information enters the device. Six format
choices are available including I
of 16, 18, 20 and 24 bits.
2
S, left or right justified, LSB or MSB first, with word widths
LRCKI (pin 31)
The left/right clock input is for data word framing. The clock frequency is at the input sample
rate, fs.
16/77
STA323W Electrical specifications
4 Electrical specifications
Table 6. Absolute maximum ratings
Symbol Parameter Value Unit
V
DD_3.3
V
i
V
o
T
stg
T
amb
V
CC
V
MAX
Table 7. Thermal data
3.3 V I/O power supply -0.5 to 4 V
Voltage on input pins -0.5 to (VDD+0.5) V
Voltage on output pins -0.5 to (VDD+0.5) V
Storage temperature -40 to +150 °C
Ambient operating temperature -40 to +85 °C
DC supply voltage 40 V
Maximum voltage on pin 20 5.5 V
Symbol Parameter Min Typ Max Unit
R
thj-case
T
j-SD
T
WARN
T
h-SD
Table 8. Recommended DC operating conditions
Thermal resistance junction to case (thermal pad) 2.5 °C/W
Thermal shut-down junction temperature 150 °C
Thermal warning temperature 130 °C
Thermal shut-down hysteresis 25 °C
Symbol Parameter Value Unit
V
DD_3.3
T
j
I/O power supply 3.0 to 3.6 V
Operating junction temperature -40 to +125 °C
4.1 General interface specifications
Operating conditions V
Table 9. General interface electrical characteristics
Symbol Parameter Test Condition Min. Typ. Max. Unit
I
il
I
ih
I
OZ
V
esd
1. The leakage currents are generally very small < 1 nA. The values given here are maximum after an
electrostatic stress on the pin.
Leakage current: low level
input, no pull-up
Leakage current: high level
input, no pull-down
Leakage current: 3-state
output without pull-up/down
Electrostatic protection
(human body model)
= 3.3 V ±0.3 V, T
DD33
amb
V
= 0 V
i
= V
V
i
DD33
= V
V
i
DD33
Leakage < 1µA2000 V
17/77
= 25° C unless otherwise specified.
(1)
(1)
(1)
1 µA
2 µA
2 µA
Electrical specifications STA323W
4.2 DC electrical specifications (3.3 V buffers)
Operating conditions V
Table 10. DC electrical characteristics
= 3.3 V ±0.3 V, T
DD33
Symbol Parameter Test condition Min. Typ. Max. Unit
V
IL
V
IH
V
hyst
V
ol
V
oh
Low level Input voltage 0.8 V
High level Input voltage 2.0 V
Schmitt trigger hysteresis 0.4 V
Low level output IoI = 2mA 0.15 V
High level output Ioh = -2mA
4.3 Power electrical specifications
Operating conditions V
otherwise specified.
Table 11. Power electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
R
I
g
g
dsON
dss
N
P
Power Pchannel/Nchannel
MOSFET R
Power Pchannel/Nchannel
leakage I
dss
Power Pchannel R
matching
Power Nchannel R
matching
= 3.3 V ±0.3 V, VL= 3.3 V, VCC=30V, T
DD33
dsON
Id = 1 A 200 270 mΩ
Vcc = 35 V 50 µA
dsON
dsON
Id = 1 A 95 %
Id = 1 A 95 %
= 25° C unless otherwise specified
amb
VDD -
0.15
= 25° C unless
amb
V
Dt_s Low current dead time (static)
t
d ON
t
d OFF
t
r
t
f
V
CC
V
L
V
H
I
VCC-
PWRDN
I
VCC-hiz
Turn-on delay time Resistive load 100 ns
Turn-off delay time Resistive load 100 ns
Rise time
Fall time
Supply voltage 8 36 V
Low logical state voltage VL = 3.3 V 0.8 V
High logical state voltage VL = 3.3 V 1.7 V
Supply current from Vcc in
PWRDN
Supply current from Vcc in 3state
18/77
See test circuits , Figure
9 and Figure 10
Resistive load, Figure 9
and Figure 10
Resistive load, Figure 9
and Figure 10
10 20 ns
25 ns
25 ns
PWRDN = 0 3 mA
V
= 30 V, 3-state 22 mA
CC
STA323W Electrical specifications
Table 11. Power electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Input pulse width = 50%
duty,
switching frequency =
384 kHz,
no LC filters;
80 mA
46 A
I
VCC
I
out-sh
Supply current from VCC in
operation
(both channel switching)
Overcurrent protection
threshold (short circuit current
limit)
V
UV
t
pw-min
P
o
P
o
Under voltage protection
threshold
Output minimum pulse width No Load 70 150 ns
Output power
Output power
4.4 Timing specifications
Table 12. Timing characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
t
RESET
f
VCO
Figure 9. Test circuit 1
Hold time for RESET (pin 22) Active low rest 100 ns
VCO free run frequency No clock applied to XTI 18 28 MHz
Low current dead time = MAX(DTr, DTf)
Duty cycle = 50%
INxY
M58
M57
THD = 10%,
= 8 Ω, VCC = 18 V
R
L
THD = 1%,
R
= 8 Ω, VCC = 18 V
L
+Vcc
OUTxY
gnd
OUTxY
DTr DTf
R 8
Ω
V67
+
vdc = Vcc/2
7V
20 W
16 W
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
t
19/77
Electrical specifications STA323W
Figure 10. Test circuit 2
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Duty cycle=A Duty cycle=B
M58
DTin(A)
INA
M57
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
Q1
Q3
OUTA
Iout=1.5A
DTout(A)
C69
470nF
Rload=4Ω
C71 470nF
L68 10µL67 10µ
C70
470nF
4.5 Power supply and control sequencing
Figure 11 shows the recommended power-up and power-down sequencing. The "time zero"
reference point is taken where V
Figure 11. Recommended power up and power down sequence
crosses the under voltage lockout threshold.
CC
M64
OUTB
Q2
INB
M63
Q4
D06AU1651
DTout(B) DTin(B)
Iout=1.5A
20/77
STA323W Electrical characteristics curves
5 Electrical characteristics curves
5.1 Output power against supply voltage
Figure 12. Stereo mode - output power vs. supply voltage, THD+N = 10%
Output power (W)
80
70
60
50
40
30
20
10
10 12 14 16 18 20 22 24 26
Power Supply Voltage (VDC)
4ohm
6ohm
8ohm
Figure 12 shows the full-scale output power (0 dBFS digital input with unity amplifier gain)
as a function of power supply voltage for 4, 6, and 8 Ω loads in either DDX
®
mode or binary
full bridge mode. Output power is constrained for higher impedance loads by the maximum
voltage limit of the STA323W and by the over-current protection limit for lower impedance
loads. The minimum threshold for the over-current protection circuit of the STA323W is 4 A
(at 25° C) but the typical threshold is 6 A for the device. The solid curves shows the typical
output power capability of the device. The dotted curves shows the output power capability
constrained to the minimum current specification of the STA323W. The output power curves
assume proper thermal management of the power device's internal dissipation.
Figure 13. Output power vs. supply for stereo bridge, THD+N=1%
output power (W) - BTL 1% THD
60
6 ohm
50
40
30
20
10
4 ohm
8 ohm
16ohm
0
10 15 20 25 30
supply voltage (V)
21/77
Electrical characteristics curves STA323W
Figure 13 shows the mono mode output power as a function of power supply voltages for
loads of 4, 6, 8 and 16 Ω. The same current limits as those given for Figure 12 apply, except
output current is 8 A minimum, with 12 A typical in the mono-bridge configuration. The solid
curves show typical performance and dashed curves depict the minimum current limit. The
output power curves assume proper thermal management of the power device internal
dissipation.
Figure 14. Half-bridge binary mode output power vs. supply, THD+N=10%
Output power (W)
25
Curves measured at
f = 1 kHz and using
20
a blocking capacitor
of 330 µF
15
10
5
0
10 12 14 16 18 20 22 2 26
Power Supply Voltage (VDC)
4ohm
6ohm
8ohm
Figure 14 shows the output power as a function of power supply voltages for loads of 4, 6,
and 8 Ω when the STA323W is operated in a half-bridge binary mode. The curves depict
typical performance. Minimum current limit is not reached for these combinations of voltage
and load impedance. The output power curves assume proper thermal management of the
power device internal dissipation.
Figure 15. Half-bridge binary mode output power vs. supply voltage, THD+N=1%
output power (W)
25
3 ohm
Curves measured at
f = 1 kHz and using
20
2 ohm
a blocking capacitor
of 330 µF
15
10
4 ohm
8 ohm
5
0
10 15 20 25 30
supply voltage (V)
22/77
STA323W Electrical characteristics curves
100
5.2 Audio performance
5.2.1 Stereo mode, operation with VCC = 26 V, 8 Ω load
Figure 16. Typical efficiency
90
80
70
60
50
40
30
20
10
0
010203040 50
Total Output Power (Watts)
Figure 17. Typical frequency response
60 70 80
Figure 18. FFT -60 dB, 1 kHz output
23/77
Electrical characteristics curves STA323W
Figure 19. FFT inter-modulation distortion 19 kHz and 20 kHz
5.2.2 Stereo mode, operation with VCC = 18.5 V
Figure 20. Frequency response, 1 W, BTL, 8 Ω
dBr A
+3
+2.5
+2
+1.5
+1
+0.5
+0
-0.5
-1
-1.5
-2
-2.5
-3
20 20k50 100 200 500 1 k 2k 5k 10k
6ohm
Figure 21. Channel separation, 1 W, BTL stereo mode
dBr A
+10
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 20k50 100 200 500 1k 2k 5k 10k
4ohm
Hz
8ohm
4 ohm
8ohm
24/77
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