STA309B
Multichannel digital audio processor with FFX
Features
■ 8 channels of 24-bit FFX
■
>100 dB SNR and dynamic range
■ Selectable 32 kH-192 kHz input sampling rates
■ 6 channels of DSD/SACD and PDM input
■ Digital gain/attenuation +58 dB to -100 dB in
0.5 dB steps
■ Advanced “pop-free” operation
■ Digital “pop-free” operation for single-ended
mode
■ Soft volume update
■ Individual channel and master gain/attenuation
plus channel trim (-10 dB to +10 dB)
■ Up to 10 independent 32-bit user-
programmable biquads (EQ) per channel
■ Bass/treble tone control
■ Pre- and post-EQ full 8-channel input mix on all
8 channels
■ Dual independent limiters/compressors
■ Dynamic range compression or anti-clipping
modes
■ AutoModes
– 5-band graphic EQ
– 32 preset EQ curves (rock, jazz, pop, etc.)
– Automatic volume controlled loudness
– 5.1 to 2-channel downmix
– Simultaneous 5.1- and 2-channel downmix
outputs
– 3 preset volume curves
– 2 preset anti-clipping modes
– Preset movie nighttime listening mode
– Preset TV channel/commercial AGC mode
– 5.1, 2.1 bass management configurations
– AM frequency automatic output PWM
frequency shifting
– 8 preset crossover filters
■ Individual channel and master soft/hard mute
®
®
Preliminary data
VFQFPN-56
■ Automatic zero-detect and invalid input mute
■ Automatic amplifier power-down on clock loss
■ Advanced AM interference frequency
switching and noise suppression modes
2
■ I
S output channel mapping function
■ Independent channel volume and DSP bypass
■ Channel mapping of any input to any
processing/FFX channel
■ Selectable per-channel FFX damped ternary or
binary PWM output
■ Max power correction for lower full-power THD
■ Variable per-channel FFX o
■ 192 kHz internal processing sampling rate,
utput delay control
24-bit to 36-bit precision
Description
The STA309B is a single-chip solution for digital
audio processing and control in multichannel
applications and provides output capabilities for
FFX (full flexible amplification). In conjunction with
an FFX power device, it provides high-quality,
high-efficiency, all-digital amplification. The device
is extremely versatile, allowing for input of most
digital formats including 6.1/7.1-channel and
192 kHz, 24-bit DVD-audio, DSD/SACD and PDM
for MEMS microphone inputs. In the 5.1
application, the additional 2 channels can be used
for audio line-out or headphone drive. In speaker
mode, with 8 channel outputs in parallel, the
STA309B can deliver 1 W (maximum).
Table 1. Device summary
Order code Package Packaging
STA309B VFQFPN56 Tube
STA309BTR VFQFPN56 Tape and reel
January 2012 Doc ID 022570 Rev 2 1/66
www.st.com
66
Contents STA309B
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5I
2
C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2.1 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2.2 Configuration register B (0x01) - serial input formats . . . . . . . . . . . . . . 24
7.2.3 Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 26
7.2.4 Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.5 Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2.6 Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/66 Doc ID 022570 Rev 2
STA309B Contents
7.2.7 Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2.8 Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2.9 Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2.10 Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.11 Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.12 Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.13 Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.14 Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.15 Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.16 Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.17 Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.18 Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.19 Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.20 Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 34
7.2.21 Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 34
7.2.22 Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 34
7.2.23 Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 35
7.2.24 Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 35
7.2.25 Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 35
7.2.26 Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 35
7.2.27 Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 35
7.2.28 Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 37
7.2.29 Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 37
7.2.30 Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 37
7.2.31 Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 37
7.2.32 AUTO1 - AutoModes EQ, volume, GC (0x1F) . . . . . . . . . . . . . . . . . . . . 38
7.2.33 AUTO2 - AutoModes bass management2 (0x20) . . . . . . . . . . . . . . . . . 39
7.2.34 AUTO3 - AutoMode AM/pre-scale/bass management scale (0x21) . . . 40
7.2.35 PREEQ - preset EQ settings (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2.36 AGEQ - graphic EQ 80-Hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.37 BGEQ - graphic EQ 300-Hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.38 CGEQ - graphic EQ 1-kHz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.39 DGEQ - graphic EQ 3-kHz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.40 EGEQ - graphic EQ 8-kHz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2.41 Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 43
7.2.42 Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.43 EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Doc ID 022570 Rev 2 3/66
Contents STA309B
7.2.44 Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.45 Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.46 Channel limiter select channels 1,2,3,4 (0x2D) . . . . . . . . . . . . . . . . . . . 45
7.2.47 Channel limiter select channels 5,6,7,8 (0x2E) . . . . . . . . . . . . . . . . . . . 45
7.2.48 Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.49 Limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.50 Limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.51 Limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.52 Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.53 Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.2.54 Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.2.55 Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.2.56 Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.2.57 Channel I
7.2.58 Channel I
7.2.59 Channel I
7.2.60 Channel I
2
S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 51
2
S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 51
2
S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 51
2
S output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 52
7.2.61 Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.2.62 Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.2.63 Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 52
7.2.64 Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 53
7.2.65 Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 53
7.2.66 Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 53
7.2.67 Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 53
7.2.68 Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 53
7.2.69 Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 53
7.2.70 Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 53
7.2.71 Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 54
7.2.72 Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 54
7.2.73 Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 54
7.2.74 Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 54
7.2.75 Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 54
7.2.76 Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 54
7.2.77 Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 54
7.2.78 Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.3 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.4 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4/66 Doc ID 022570 Rev 2
STA309B Contents
7.5 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.6 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.1 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.2 Variable maximum power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.2.1 MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.3 Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.3.1 DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.4 PSCorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52) . . . . . . . . . . . . . . . 60
8.4.2 PSC3: correction normalization value (CNV) (0x53) . . . . . . . . . . . . . . . 60
8.5 Digital pop-free operation in single-ended mode . . . . . . . . . . . . . . . . . . . 60
8.5.1 PFCXON: digital pop-free register (0x5F) . . . . . . . . . . . . . . . . . . . . . . . 61
8.5.2 Timing settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.5.3 RAMPTIM: ramp duration register (0x66) . . . . . . . . . . . . . . . . . . . . . . . 62
8.5.4 TSPUPT: waiting time after EAPD (0x67 - 0x68) . . . . . . . . . . . . . . . . . . 62
8.5.5 LSPDWT: waiting time before EAPD (0x71 - 0x72) . . . . . . . . . . . . . . . . 62
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Doc ID 022570 Rev 2 5/66
List of tables STA309B
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. General interface electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. DC electrical characteristics: 3.3-V buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. RAM block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 10. VFQFPN-56 (8 x 8 mm) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 11. Exposed pad variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6/66 Doc ID 022570 Rev 2
STA309B List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Reference schematic for STA309B-based application . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 8. Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 9. Typical single-ended driver - power stage configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10. Pop-free timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 11. VFQFPN-56 (8 x 8 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Doc ID 022570 Rev 2 7/66
Block diagram STA309B
1 Block diagram
Figure 1. Block diagram
SA
SCL
LRCKI
BICKI
SDI12
SDI34
SDI56
SERIAL
DATA
IN
SYSTEM
CONTROL
SDI78
CHANNEL
MAPPING
VARIABLE
OVER-
SAMPLING
SYSTEM TIMING
PLLB
PLL
XTI
CKOUT
Figure 2. Channel signal flow
6 Inputs
From DSD
DSD
Conversion
SDA
I2C
PWDN
POWER
DOWN
MVO
OVERSAMPLING
TREBLE,
BASS, EQ
(BIQUADS )
EAPD
VOLUME
LIMITING
VARIABLE
DOWN-
SAMPLING
DDX
FFX
SERIAL
DATA
OUT
OUT1A/B
OUT2A/B
OUT3A/B
OUT4A/B
OUT5A/B
OUT6A/B
OUT7A/B
OUT8A/B
LRCKO
BICKO
SDO12
SDO34
SDO56
SDO78
Interp_Rate
8 Inputs
From I2S
From
Mix#1
Engine
Or
Previous
Channel
Biq u a d # 1 0
Output
(CxBLP)
PreScale
Hard Set to
-18dB when
Aut oMod e EQ
(AMEQ)
1x,2x,4x
Interp
Distortion
Compensation
High - P a s s
Filt er
Use r Pr og amm ab le
Biqu ad #1 wh en
High-Pass Bypassed
(HPB)
Biq u a d
DSDE
Mapp ing/
Mix #1
Biq u ad s
B/ T
NS C_Con PWM
Biqu ad
#2
Biqu ad
#3
Hard Set Coeec ients wh en AutoMode EQ
(AMEQ)
Biqu a d
#4
#5
8/66 Doc ID 022570 Rev 2
Biquad
#6
Mix #2
Coeecients when
Bass Management
Biquad
#7
Hard Se t
Aut o Mo d e
Cross over
(AMBMXE)
Vol um e
Limiter
Biqu a d
#8
Hard Se t
Coeecient s when
DeEmphasis
Enab led
(DEMP)
2x
Interp
DDX
Output
Bas s
Use r Pr og ram mab le
Biquads #9 and #10
When Tone Bypass ed
(CxTCB)
Treble
To
Mix# 2
Engine
STA309B Pin connections
2 Pin connections
Figure 3. Pin connections (top view)
PWDN
SDO_78
SDO_56
GND
VDD
SDO_34
SDO_12
LRCKO
BICKO
GND
VDD EAPD
56
1 MVO
2 GND
3 VDD
4 GND
5 SDI_78
6 SDI_56
7 SDI_34
8 SDI_12
9 LRCKI
10 BICKI
11 VDD
12 GND
55
54
52
51
53
VFQFPN-56
50
49
48
47
46
45
OUT1_A
44
OUT1_B
43
42
41
40
39
38
37
36
35
34
33
32
31
OUT2_A
OUT2B
GND
VDD
OUT3_A
OUT3_B
OUT4_A
OUT4_B
OUT5_A
OUT5_B
GND
VDD
13 RESET
14 BYPASS
15
SA
16 SDA
SCL
17
XTI 19 FILTER_PLL
18
20
GNDA
22 CKOUT
21 VDDA
23 GND
25 OUT8_B
24 VDD
26 OUT8_A
27
OUT7_B
28
OUT7_A
30
29
OUT6_A
OUT6_B
Doc ID 022570 Rev 2 9/66
Pin connections STA309B
Table 2. Pin description
STA309B pin Type Name Description
1 5-V tolerant TTL input buffer MVO/DSD_CLK
5 5-V tolerant TTL input buffer SDI_78/DSD_6
6 5-V tolerant TTL input buffer SDI_56/DSD_5
7 5-V tolerant TTL input buffer SDI_34/DSD_4
8 5-V tolerant TTL input buffer SDI_12/DSD_3
9 5-V tolerant TTL input buffer LRCKI/DSD_2
10 5-V tolerant TTL input buffer BICKI/DSD_1
13
5-V tolerant TTL schmitt trigger
input buffer
RESET Global reset
Master volume override/
DSD input clock
Input serial data channels 7 & 8/
DSD input channel 6
Input serial data channels 5 & 6/
DSD input channel 5
Input serial data channels 3 & 4/
DSD input channel 4
Input serial data channels 1 & 2/
DSD input channel 3
Input left/right clock/
DSD input channel 2
Input serial clock/
DSD input channel 1
14 CMOS input buffer with pull-down PLL_BYPASS Bypass phase locked loop
15 CMOS input buffer with pull-down SA Select address (I
16
Bidirectional buffer: 5-V tolerant TTL
schmitt trigger input; 3.3-V capable
SDA Serial data (I
2
C)
2 mA slew-rate controlled output
17
18
5-V tolerant TTL schmitt trigger
input buffer
5-V tolerant TTL schmitt trigger
input buffer
SCL Serial clock (I
XTI Crystal oscillator input (clock input)
2
C)
2
C)
19 Analog pad FILTER_PLL PLL filter
20 Analog ground GNDA PLL ground
21 3.3V analog supply voltage VDDA PLL supply
22
25
26
27
28
29
3.3-V capable TTL tristate 4mA
output buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
CKOUT Clock output
OUT8B PWM channel 8 output B
OUT8A PWM channel 8 output A
OUT7B PWM channel 7 output B
OUT7A PWM channel 7 output A
OUT6B PWM channel 6 output B
10/66 Doc ID 022570 Rev 2
STA309B Pin connections
Table 2. Pin description (continued)
STA309B pin Type Name Description
30
33
34
35
36
37
38
41
42
43
44
45
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 4mA output
buffer
OUT6A PWM channel 6 output A
OUT5B PWM channel 5 output B
OUT5A PWM channel 5 output A
OUT4B PWM channel 4 output B
OUT4A PWM channel 4 output A
OUT3B PWM channel 3 output B
OUT3A PWM channel 3 output A
OUT2B PWM channel 2 output B
OUT2A PWM channel 2 output A
OUT1B PWM channel 1 output B
OUT1A PWM channel 1 output A
EAPD Ext. amp power-down
48
49
50
51
54
55
56
3,11,21,24,31,39,
46,52
2,4,12,20,23,32,
40,47,53
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
3.3-V capable TTL 2mA output
buffer
5-V tolerant TTL schmitt trigger
input buffer
3.3-V digital supply voltage VDD 3.3-V supply
Digital ground GND Ground
Doc ID 022570 Rev 2 11/66
BICKO Output serial clock
LRCKO Output left/right clock
SDO_12 Output serial data channels 1&2
SDO_34 Output serial data channels 3&4
SDO_56 Output serial data channels 5&6
SDO_78 Output serial data channels 7&8
PWDN Device power-down
Electrical specifications STA309B
3 Electrical specifications
3.1 Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Min Typ Max Unit
V
V
V
V
T
T
DD
DDA
i
o
stg
amb
3.3-V I/O power supply -0.5 4 V
3.3-V logic power supply -0.5 4 V
Voltage on input pins -0.5 VDD + 0.5 V
Voltage on output pins -0.5 VDD + 0.3 V
Storage temperature -40 150 °C
Ambient operating temperature -40 90 °C
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Min Typ Max Unit
R
thj-case
Thermal resistance, junction-case (thermal pad)
STA309B
3.3 Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter Min Typ Max Unit
1.5 °C/W
V
V
T
DD
DDA
j
I/O power supply 3.0 3.6 V
Logic power supply 3.0 3.6 V
Operating junction temperature -40 125 °C
12/66 Doc ID 022570 Rev 2
STA309B Electrical specifications
3.4 Electrical specifications
The following specifications are valid for VDD = 3.3 V ± 0.3 V, V
= 3.3 V ± 0.3 V and
DDA
Tamb = 0 to 70 °C, unless otherwise stated.
Table 6. General interface electrical specifications
Symbol Parameter Conditions Min Typ Max Unit
I
il
I
ih
I
OZ
V
esd
1. The leakage currents are generally very small, < 1 nA. The values given here are maximum after an
electrostatic stress on the pin.
Table 7. DC electrical characteristics: 3.3-V buffers
Low-level input no pull-up Vi = 0 V 1
High-level input no
pull-down
Tristate output leakage
without pull-up/down
Electrostatic protection
(human body model)
V
= VDD 2μA
i
= VDD 2μA
V
i
Leakage < 1μA2000V
Symbol Parameter Conditions Min Typ Max Unit
V
IL
V
IH
V
ILhyst
V
IHhyst
V
hyst
V
ol
V
oh
Low-level input voltage 0.8 V
High-level input voltage 2.0 V
Low-level threshold Input falling 0.8 1.35 V
High-level threshold Input rising 1.3 2.0 V
Schmitt trigger hysteresis 0.3 0.8 V
Low-level output IoI = 100 µA 0.2 V
High-level output
Ioh = -100 µA
VDD-
0.2
Ioh = -2 mA 2.4 V
(1)
μA
V
Doc ID 022570 Rev 2 13/66
Pin description STA309B
4 Pin description
Master volume override (MVO)
This pin enables the user to bypass the volume control on all channels. When MVO is pulled
high, the master volume register is set to 0x00, which corresponds to its full-scale setting.
The master volume register setting offsets the individual channel volume settings, which
default to 0 dB.
Serial data in (SDI_12, SDI_34, SDI_56, SDI_78)
Audio information enters the device here. Six format choices are available including I2S,
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
RESET
Driving this pin low turns off the outputs and returns all settings to their defaults.
I2C bus
The SA, SDA and SCL pins operate per the Phillips I2C specification. See Section 5: I2C
bus operation.
Phase locked loop (PLL)
The phase locked loop section provides the system timing signals and CKOUT.
Clock output (CKOUT)
System synchronization and master clocks are provided by CKOUT.
PWM outputs (OUT1 through OUT8)
The PWM outputs provide the input signal for the power devices.
External amplifier power-down (EAPD)
This signal can be used to control the power-down of FFX power devices.
Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)
These are the outputs for audio information. Six different formats are available including I2S,
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
Device power-down (PWDN)
Pulling PWDN low begins the power-down sequence which puts the STA309B into a
low-power state. EAPD (pin 51) goes low approximately 30 ms later.
14/66 Doc ID 022570 Rev 2
STA309B I2C bus operation
5 I2C bus operation
The STA309B supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master).
This protocol defines any device that sends data on to the bus as a transmitter and any
device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA309B is always a slave device in all of its communications.
5.1 Communication protocol
5.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition
while the clock is high is used to identify a START or STOP condition.
5.1.2 Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
5.1.3 Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between the
STA309B and the bus master.
5.1.4 Data input
During the data input the STA309B samples the SDA signal on the rising edge of clock SCL.
For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.
5.2 Device addressing
To start communication between the master and the Omega FFX core, the master must
initiate with a start condition. Following this, the master sends 8 bits to the SDA line (MSB
first) corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I
definition. In the STA309B the I
port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.
th
The 8
for write mode. After a START condition, the STA309B identifies on the bus the device
address and if a match is found, it acknowledges the identification on the SDA bus during
bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0
2
C interface has two device addresses depending on the SA
2
C bus
Doc ID 022570 Rev 2 15/66
I2C bus operation STA309B
the 9th-bit time. The byte following the device identification byte is the internal space
address.
5.3 Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA309B acknowledges this and then waits for the byte of internal address.
After receiving the internal byte address the STA309B again responds with an
acknowledgement.
5.3.1 Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the FFX
core. The master then terminates the transfer by generating a STOP condition.
5.3.2 Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 4. Write mode sequence
BYTE
WRITE
DEV-ADDR
START RW
ACK
ACK
MULTIBYTE
WRITE
DEV-ADDR
START RW
Figure 5. Read mode sequence
ACK
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
START
START
START
START
DEV-ADDR
DEV-ADDR
DEV-ADDR
DEV-ADDR
RW=
HIGH
DATA
RW
ACK
SUB-ADDR
RW
ACK
DATA
ACK
SUB-ADDR
RW
SUB-ADDR
SUB-ADDR
NO ACK
ACK
ACK
ACK
STOP
DATA
DEV-ADDR
DEV-ADDR
ACK
ACK
CK
A
DATA IN
STOP
DATA IN
CK
DATA IN
ACK
A
STOP
CK
A
WRTRATS
ACK
CK
A
WRTRATS
DATA
DATA
DATA
NO ACK
NO A
CK
A
STOP
CK
STOP
DATA
CK NO ACK
A
DATA
STOP
16/66 Doc ID 022570 Rev 2
STA309B Application reference schematic
6 Application reference schematic
Figure 6. Reference schematic for STA309B-based application
+3.3V
2.2UF
2.2UF
EIA3216_A
EIA3216_A
C4
6.3VDC
C4
6.3VDC
+
+
C12
C12
Y5V
100NF
100NF
EIA0603
Y5V
EIA0603
+3.3V
C20
100NF
Y5V
EIA0603
C20
100NF
Y5V
EIA0603
EAPD
2
L1
L1
EIA0805
EIA0805
R6
0
R6
0
0000-0603
0000-0603
+3.3V
C14
C14
Y5V
Y5V
100NF
100NF
EIA0603
EIA0603
1
600 ohm@100mhz
600 ohm@100mhz
2
L3
L3
EIA0805
EIA0805
1
600 ohm@100mhz
600 ohm@100mhz
+3.3V
+3.3V
C145
C145
C18
C18
100NF
100NF
100NF
100NF
Y5V
Y5V
Y5V
Y5V
EIA0603
EIA0603
EIA0603
EIA0603
CH1_A
C147 1000PF
C147 1000PF
PWRDWN
CH1_B
NPO
NPO
EIA0805
EIA0805
CH2_A
CH3_A
44
OUT3_A43OUT3_B
VDD3.3_5
SDI_78
5
6
CH3_B
42
41
SDI_56
8
7
SDATA2
CH4_A
CH4_B
OUT4_A
OUT4_B40OUT5_A
SDI_12
SDI_34
9
SDATA1
SDATA0
CH5_A
39
LRCKI
10
LRCK
38
11
CH2_B
45
47
46
48
U2
NC 46
GND_5
OUT2_A
OUT2_B
OUT1_B
49
OUT1_A
50
EAPD
51
VDD3.3_6
52
GND_6
53
NC 54
54
BICKO
55
LRCKO
56
SDO_12
57
SDO_34
58
VDD3.3_7
59
GND_7
60
NC 61
61
SDO_56
62
SDO_78
63
PWDN
64
VDD3.3_1
TEST_MODE
GND_14NC 5
MVO
3
2
1
0
0
0000-0603
0000-0603
R14
R14
CH5_B
37
NC 37
OUT5_B
VDD3.3_2
BICKI
12
BICK
36
GND_4
GND_2
13
35
14
CH6_B
CH6_A
34
33
OUT6_A
OUT6_B
VDD3.3_4
PLL_BYPASS
NC 14
RESET
16
15
STA308AU2STA308A
OUT7_A
32
OUT7_B
31
OUT8_A
30
OUT8_B
29
VDD3.3_3
28
GND_3
27
NC 26
26
CKOUT
25
VDD3.3_PLL
24
GNDA_PLL
23
VDDA_PLL
22
PLL_FILTER
21
XTI
20
SCL
19
SDA
18
SA
17
NPO
NPO
C157
C157
47PF
47PF
NPO
NPO
1000PF
1000PF
C155
C155
EIA0603
EIA0603
EIA0603
EIA0603
+3.3V
C25
C25
C23
C23
Y5V
Y5V
100NF
100NF
100NF
Y5V
100NF
Y5V
EIA0603
EIA0603
EIA0603
EIA0603
SDA
VDDA
SCL
MCLK
C22
C22
+
+
C24
C24
22UF
22UF
100NF
100NF
R15
R15
EIA3528_B
EIA3528_B
6.3VDC
6.3VDC
Y5V
Y5V
EIA0603
EIA0603
C19
C19
220PF
220PF
3.40K
3.40K
0603
0603
NPO
NPO
EIA0603
EIA0603
C16
C16
C15
C15
NPO
NPO
100PF
100PF
1200PF
1200PF
X7R
X7R
The PLL filter must be placed as close
GNDA
EIA0603
EIA0603
EIA0603
EIA0603
as possible to the STA309B pins
+3.3V
Y5V
Y5V
100NF
EIA0603
100NF
EIA0603
C5
C5
+3.3V
Y5V
Y5V
C6
100NF
C6
100NF
EIA0603
EIA0603
POWER_ON_RST
Doc ID 022570 Rev 2 17/66
Registers STA309B
7 Registers
7.1 Register summary
Table 8. Register summary
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
Configuration
0x00 CONFA COS1 COS0 DSPB IR1 IR0 MCS2 MCS1 MCS0
0x01 ConfB SAIFB SAI3 SAI2 SAI1 SAI0
0x02 ConfC SAOFB SAO3 SAO2 SAO1 SAO0
0x03 ConfD MPC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0
0x04 ConfE C8BO C7BO C6BO C5BO C4BO C3BO C2BO C1BO
0x05 ConfF PWMS2 PWMS1 PWMS0 BQL PSL DEMP DRC HPB
0x06 ConfG MPCV DCCV HPE AM2E AME COD SID PWMD
0x07 ConfH ECLE LDTE BCLE IDE ZDE SVE ZCE NSBW
0x08 ConfI EAPD PSCE
Volu m e c on t rol
0x09 MMUTE MMUTE
0x0A Mvol MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0
0x0B C1Vol C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0
0x0C C2Vol C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0
0x0D C3Vol C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0
0x0E C4Vol C4V7 C4V6 C4V5 C4V4 C4V3 C4V2 C4V1 C4V0
0x0F C5Vol C5V7 C5V6 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0
0x10 C6Vol C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0
0x11 C7Vol C7V7 C7V6 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0
0x12 C8Vol C8V7 C8V6 C8V5 C8V4 C8V3 C8V2 C8V1 C8V0
0x13 C1VTMB C1M C1VBP C1VT4 C1VT3 C1VT2 C1VT1 C1VT0
0x14 C2VTMB C2M C2VBP C2VT4 C2VT3 C2VT2 C2VT1 C2VT0
0x15 C3VTMB C3M C3VBP C3VT4 C3VT3 C3VT2 C3VT1 C3VT0
0x16 C4VTMB C4M C4VBP C4VT4 C4VT3 C4VT2 C4VT1 C4VT0
0x17 C5VTMB C5M C5VBP C5VT4 C5VT3 C5VT2 C5VT1 C5VT0
0x18 C6VTMB C6M C6VBP C6VT4 C6VT3 C6VT2 C6VT1 C6VT0
0x19 C7VTMB C7M C7VBP C7VT4 C7VT3 C7VT2 C7VT1 C7VT0
0x1A C8VTMB C8M C8VBP C8VT4 C8VT3 C8VT2 C8VT1 C8VT0
18/66 Doc ID 022570 Rev 2
STA309B Registers
Table 8. Register summary (continued)
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
Input mapping
0x1B C12im C2IM2 C2IM1 C2IM0 C1IM2 C1IM1 C1IM0
0x1C C34im C4IM2 C4IM1 C4IM0 C3IM2 C3IM1 C3IM0
0x1D C56im C6IM2 C6IM1 C6IM0 C5IM2 C5IM1 C5IM0
0x1E C78im C8IM2 C8IM1 C8IM0 C7IM2 C7IM1 C7IM0
AutoMode
0x1F Auto1 AMDM AMGC2 AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0
0x20 Auto2 SUB RSS1 RSS0 CSS1 CSS0 FSS
0x21 Auto3 AMAM2 AMAM1 AMAM0 AMAME MSA AMPS
0x22 PreEQ XO2 XO1 XO0 PEQ4 PEQ3 PEQ2 PEQ1 PEQ0
0x23 Ageq AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0
0x24 Bgeq BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0
0x25 Cgeq CGEQ4 CGEQ3 CGEQ2 CGEQ1 CGEQ0
0x26 Dgeq DGEQ4 DGEQ3 DGEQ2 DGEQ1 DGEQ0
AMBMXE
AMBMME
0x27 Egeq EGEQ4 EGEQ3 EGEQ2 EGEQ1 EGEQ0
Processing loop
0x28 BQlp C8BLP C7BLP C6BLP C5BLP C4BLP C3BLP C2BLP C1BLP
0x29 MXlp C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP
Processing bypass
0x2A EQbp C8EQBP C7EQBP C6EQBP
0x2B ToneBP C8TCB C7TCB C6TCB C5TCB C4TCB C3TCB C2TCB C1TCB
Tone control
0x2C Tone TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0
Dynamics control
0x2D C1234ls C4LS1 C4LS0 C3LS1 C3LS0 C2LS1 C2LS0 C1LS1 C1LS0
0x2E C5678ls C8LS1 C8LS0 C7LS1 C7LS0 C6LS1 C6LS0 C5LS1 C5LS0
0x2F L1ar L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0
0x30 L1atrt L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0
0x31 L2ar L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0
0x32 L2atrt L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0
PWM output timing
C5EQBP
C4EQBP C3EQBP C2EQBP C1EQBP
0x33 C12ot C2OT2 C2OT1 C2OT0 C1OT2 C1OT1 C1OT0
0x34 C34ot C4OT2 C4OT1 C4OT0 C3OT2 C3OT1 C3OT0
Doc ID 022570 Rev 2 19/66
Registers STA309B
Table 8. Register summary (continued)
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
0x35 C56ot C6OT2 C6OT1 C6OT0 C5OT2 C5OT1 C5OT0
0x36 C78ot C8OT2 C8OT1 C8OT0 C7OT2 C7OT1 C7OT0
I2S output channel mapping
0x37 C12om C2OM2 C2OM1 C2OM0 C1OM2 C1OM1 C1OM0
0x38 C34om C4OM2 C4OM1 C4OM0 C3OM2 C3OM1 C3OM0
0x39 C56om C6OM2 C6OM1 C6OM0 C5OM2 C5OM1 C5OM0
0x3A C78om C8OM2 C8OM1 C8OM0 C7OM2 C7OM1 C7OM0
User-defined coefficient RAM
0x3B Cfaddr1 CFA9 CFA8
0x3C Cfaddr2 CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0
0x3D B1cf1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16
0x3E B1cf2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8
0x3F B1cf3 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0
0x40 B2cf1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16
0x41 B2cf2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8
0x42 B2cf3 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0
0x43 A1cf1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16
0x44 A1cf2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8
0x45 A1cf3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0
0x46 A2cf1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16
0x47 A2cf2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8
0x48 A2cf3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0
0x49 B0cf1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16
0x4A B0cf2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8
0x4B B0cf3 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0
0x4C Cfud WA W1
0x4D MPCC1 MPCC15 MPCC14 MPCC13
0x4E MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0
0x4F DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8
0x50 DCC2 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0
0x51 PSC1 RCV11 RCV10 RCV9 RCV8 RCV7 RCV6 RCV5 RCV4
0x52 PSC2 RCV3 RCV2 RCV1 RCV0 CNV11 CNV10 CNV9 CNV8
MPCC12
MPCC11 MPCC10 MPCC9 MPCC8
0x53 PSC3 CNV7 CNV6 CNV5 CNV4 CNV3 CNV2 CNV1 CNV0
20/66 Doc ID 022570 Rev 2
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