ST STA308A User Manual

Multi-channel digital audio processor with DDX™

Features

! 8 channels of 24-bit DDX

! >100 dB SNR and dynamic range

! Selectable 32 kHz - 192 kHz input sample rates

! 6 channels of DSD/SACD input

! Digital gain/attenuation +58 dB to -100 dB in

0.5 dB steps

! Soft volume update

! Individual channel and master gain/attenuation

plus channel trim (-10 dB to +10 dB)

! Up to 10 independent 32-bit user

programmable biquads (EQ) per channel

! Bass/treble tone control

! Pre and post EQ full 8-channel input mix on all

8 channels

! Dual independent limiters/compressors

! Dynamic range compression or anti-clipping

modes

! AutoModes:

– 5-band graphic EQ – 32 preset EQ curves (rock, jazz, pop, etc.) – Automatic volume controlled loudness – 5.1 to 2-channel downmix – Simultaneous 5.1- and 2-channel downmix

outputs – 3 preset volume curves – 2 preset anti-clipping modes – Preset movie nighttime listening mode – Preset TV channel/commercial AGC mode – 5.1, 2.1 bass management configurations – AM frequency automatic output PWM

frequency shifting – 8 preset crossover filters

! Individual channel and master soft/hard mute

! Automatic zero-detect and invalid input mute

! Automatic invalid input detect mute

STA308A

TQFP64

! Advanced PopFree operation

! Advanced AM interference frequency

switching and noise suppression modes

! I

S output channel mapping function

! Independent channel volume and DSP bypass

! Channel mapping of any input to any

processing/DDX

! DC blocking selectable high-pass filter

! Selectable per-channel DDX

or binary PWM output

! Max power correction for lower full-power THD

! Variable per channel DDX

! 192 kHz internal processing sample rate, 24-bit

to 36-bit precision

Description

The STA308A is a single chip solution for digital audio processing and control in multi-channel applications. It provides output capabilities for

DDX

(direct digital amplification). In conjunction with a DDX quality, high-efficiency, all digital amplification. The device is extremely versatile, allowing for input of most digital formats including 6.1/7.1channel and 192 kHz, 24-bit DVD-audio, DSD/SACD. In 5.1 application the additional 2 channels can be used for audio line-out or headphone drive. In speaker mode, with 8 channel outputs in parallel, the STA308A can deliver 1 W (maximum).

Table 1. Device summary

STA308A TQFP64

power device, it provides high-

Order code Package

channel

damped ternary

utput delay control

July 2007 Rev 4 1/63

www.st.com

Contents STA308A

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.2.1 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.2.2 Configuration register B (0x01) - serial input formats . . . . . . . . . . . . . . 23

7.2.3 Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 25

7.2.4 Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.2.5 Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.2.6 Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/63

STA308A Contents

7.2.7 Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2.8 Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2.9 Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.2.10 Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.11 Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.12 Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.13 Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.14 Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.15 Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.16 Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.17 Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.18 Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.19 Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.20 Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 33

7.2.21 Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 33

7.2.22 Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 33

7.2.23 Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 34

7.2.24 Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 34

7.2.25 Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 34

7.2.26 Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 34

7.2.27 Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 34

7.2.28 Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 36

7.2.29 Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 36

7.2.30 Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 36

7.2.31 Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 36

7.2.32 AUTO1 - AutoModes EQ, volume, GC (0x1F) . . . . . . . . . . . . . . . . . . . . 37

7.2.33 AUTO2 - AutoModes bass management2 (0x20) . . . . . . . . . . . . . . . . . 38

7.2.34 AUTO3 - AutoMode AM/pre-Scale/bass management scale (0x21) . . . 39

7.2.35 PREEQ - Preset EQ settings (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2.36 AGEQ - graphic EQ 80-Hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.37 BGEQ - graphic EQ 300-Hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.38 CGEQ - graphic EQ 1-kHz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.39 DGEQ - graphic EQ 3-kHz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.40 EGEQ - graphic EQ 8-kHz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2.41 Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 42

7.2.42 Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 43

7.2.43 EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3/63

Contents STA308A

7.2.44 Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.2.45 Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.2.46 Channel limiter select channels 1,2,3,4 (0x2D) . . . . . . . . . . . . . . . . . . . 44

7.2.47 Channel limiter select channels 5,6,7,8 (0x2E) . . . . . . . . . . . . . . . . . . . 44

7.2.48 Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.2.49 Limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.50 Limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.51 Limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.52 Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.53 Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2.54 Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2.55 Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2.56 Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.2.57 Channel I

7.2.58 Channel I

7.2.59 Channel I

7.2.60 Channel I

S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 50

S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 50

S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 50

S output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 51

7.2.61 Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2.62 Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2.63 Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 51

7.2.64 Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 52

7.2.65 Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 52

7.2.66 Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 52

7.2.67 Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 52

7.2.68 Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 52

7.2.69 Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 52

7.2.70 Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 52

7.2.71 Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 53

7.2.72 Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 53

7.2.73 Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 53

7.2.74 Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 53

7.2.75 Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 53

7.2.76 Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 53

7.2.77 Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 53

7.2.78 Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.3 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.4 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4/63

STA308A Contents

7.5 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.6 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.1 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.2 Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.2.1 MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.3 Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.3.1 DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.4 PSCorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52) . . . . . . . . . . . . . . . 59

8.4.2 PSC3: correction normalization value (CNV) (0x53) . . . . . . . . . . . . . . . 59

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 61

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5/63

List of tables STA308A

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 7. DC electrical characteristics: 3.3-V buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. RAM block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6/63

STA308A List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Pin connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5. Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. Reference schematic for STA308A-based application . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 8. Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 9. TQFP64 (10 x 10 x 1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . 58

7/63

Block diagram STA308A

(

)

1 Block diagram

Figure 1. Block diagram

LRCKI

BICKI

SDI12

SDI34

SDI56

SDI78

PLLB

SERIAL

CHANNEL MAPPING

PLL

XTI

DATA

SYSTEM TIMING

CKOUT

VARIABLE

OVER-

SAMPLING

Figure 2. Channel signal flow

6 Inputs From DSD

DSD

Conversion

Interp_Rate

SCL

SDA

I2C

SYSTEM

CONTROL

POWER DOWN

PWDN

MVO

TREBLE,

BASS, EQ BIQUADS

EAPD

OVERSAMPLING

VOLUME LIMITING

VARIABLE

DOWN-

SAMPLING

DDX

SERIAL

DATA

OUT

OUT1A/B

OUT2A/B

OUT3A/B

OUT4A/B

OUT5A/B

OUT6A/B

OUT7A/B

OUT8A/B

LRCKO

BICKO SDO12

SDO34

SDO56

SDO78

8 Inputs From I2S

From Mix#1 Engine Or Previous Channel Biq ua d # 1 0 Output (CxBLP)

PreScale

Hard Set to

-18dB when

AutoMode EQ

(AMEQ)

1x,2x,4x

Interp

Distortion

Compensation

High - Pa s s

Filte r

User Progammable

Biquad #1 when

High-Pass Bypassed

(HPB)

Mapping/

Mix #1

DSDE

NS C_Con PWM

Biq ua d#2Biquad#3Biquad

Hard Set Coeffecients when AutoMode EQ

(AMEQ)

8/63

Biq ua ds

B/ T

Biqu a d#5Biquad#6Biquad

Mix #2

Coeffec ients when

Bass Management

Hard Set

Aut oM od e

Cross over

(AMBMXE)

Vol um e

Limiter

Biquad

Hard Set

Coeffec ients when

DeEmphasis

Enable d (DEMP)

Interp

DDX Output

Bas s

User Pro grammable Biquads #9 and #10

When Tone Bypass ed

(CxTCB)

Treble

To Mix#2 Engine

STA308A Pin connections

2 Pin connections

Figure 3. Pin connection (Top view)

VDD

SDO_34

SDO_12

LRCKONCBICKO

GND

VDD

EAPD

OUT1_A

OUT8_B

OUT8_A

OUT1_B

OUT7_B

OUT7_A

OUT2_A

OUT2_B

GND

VDD

OUT3_A

OUT3_B

OUT4_A

OUT4_B

OUT5_A

OUT5_B

GND

VDD

OUT6_A

OUT6_B

STA308APINCON

MVO

GND

VDD

GND

SDI_78

SDI_56

SDI_34

SDI_12

LRCKI

BICKI

VDD

GND

RESET

PLLB

SDO_78

PWDN

17 18 19 20 21

SDA

GND61NC62SDO_56

59 58 57 565455 53 52 51 50 49

22 23 24 25 26

SCL

XTI

FILTER_PLL

GNDA

VDDA

CKOUT

271128 29 30 31 32

VDD

GND

Table 2. Pin description

Pin Type Name Description

1 5-V tolerant TTL input buffer MVO/DSD_CLK

6 5-V tolerant TTL input buffer SDI_78/DSD_6

7 5-V tolerant TTL input buffer SDI_56/DSD_5

8 5-V tolerant TTL input buffer SDI_34/DSD_4

9 5-V tolerant TTL input buffer SDI_12/DSD_3

10 5-V tolerant TTL input buffer LRCKI/DSD_2

11 5-V tolerant TTL input buffer BICKI/DSD_1

5-V tolerant TTL schmitt trigger input buffer

CMOS input buffer with pull-down

RESET Global reset

PLL_BYPASS Bypass phase locked loop

Master volume override/ DSD input clock

Input serial data channels 7 & 8/ DSD input channel 6

Input serial data channels 5 & 6/ DSD input channel 5

Input serial data channels 3 & 4/ DSD input channel 4

Input serial data channels 1 & 2/ DSD input channel 3

Input left/right clock/ DSD input channel 2

Input serial clock/ DSD input channel 1

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Pin connections STA308A

Table 2. Pin description (continued)

Pin Type Name Description

CMOS input buffer with pull-down

SA Select address (I

Bidirectional buffer: 5-V

tolerant TTL schmitt trigger input; 3.3-V capable 2mA

SDA Serial data (I

slew-rate controlled output.

5-V tolerant TTL schmitt trigger input buffer

SCL Serial clock (I

XTI Crystal oscillator input (clock input)

21 Analog pad FILTER_PLL PLL filter

23 Analog ground GNDA PLL ground

24 3.3V analog supply voltage VDDA PLL supply

3.3-V capable TTL tristate 4mA output buffer

3.3-V capable TTL 2mA output buffer

CKOUT Clock output

OUT8B PWM channel 8 output B

OUT8A PWM channel 8 output A

OUT7B PWM channel 7 output B

3.3-V capable TTL 2mA output buffer

OUT7A PWM channel 7 output A

OUT6B PWM channel 6 output B

OUT6A PWM channel 6 output A

OUT5B PWM channel 5 output B

OUT5A PWM channel 5 output A

OUT4B PWM channel 4 output B

OUT4A PWM channel 4 output A

OUT3B PWM channel 3 output B

OUT3A PWM channel 3 output A

OUT2B PWM channel 2 output B

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STA308A Pin connections

Table 2. Pin description (continued)

Pin Type Name Description

3,12,28,35, 44,52,59

3.3-V capable TTL 2mA output buffer

3.3-V capable TTL 4mA output buffer

3.3-V capable TTL 2mA output buffer

5-V tolerant TTL schmitt trigger input buffer

3.3-V digital supply voltage VDD 3.3-V supply

OUT2A PWM channel 2 output A

OUT1B PWM channel 1 output B

OUT1A PWM channel 1 output A

EAPD Ext. amp power-down

BICKO Output serial clock

LRCKO Output left/right clock

SDO_12 Output serial data channels 1&2

SDO_34 Output serial data channels 3&4

SDO_56 Output serial data channels 5&6

SDO_78 Output serial data channels 7&8

PWDN Device power-down

2,4,13,27, 36,45,53,60

5, 14, 22, 26,37,46,54, 61

Digital ground GND Ground

NC Not connected

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Electrical specification STA308A

3 Electrical specification

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

DDA

stg

amb

3.3-V I/O power supply -0.5 4 V

3.3-V logic power supply -0.5 4 V

Voltage on input pins -0.5

Voltage on output pins -0.5

Storage temperature -40 150 °C

Ambient operating temperature -40 90 °C

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Min Typ Max Unit

thj-amb

Thermal resistance, junction to ambient 85 °C/W

3.3 Recommended operating condition

Table 5. Recommended operating condition

VDD +

0.5

VDD +

0.3

Symbol Parameter Min Typ Max Unit

DDA

I/O power supply 3.0 3.6 V

Logic power supply 3.0 3.6 V

Operating junction temperature -40 125 °C

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STA308A Electrical specification

3.4 Electrical specifications

The following specifications are valid for VDD = 3.3V ± 0.3V, VDDA = 3.3V ± 0.3V and Tamb = 0 to 70 °C, unless otherwise stated

Table 6. General interface electrical specifications

Symbol Parameter Conditions Min Typ Max Unit

Low-level input no pull-up Vi = 0V 1

High-level input no pull-down

= VDD 2µA

(1)

µA

esd

1. The leakage currents are generally very small, < 1 nA. The values given here are maximum after an electrostatic stress on the pin.

Table 7. DC electrical characteristics: 3.3-V buffers

Tristate output leakage without pull-up/down

Electrostatic protection (human body model)

= VDD 2µA

Leakage < 1µA2000V

Symbol Parameter Conditions Min Typ Max Unit

ILhyst

IHhyst

hyst

Low-level input voltage 0.8 V

High-level input voltage 2.0 V

Low-level threshold Input falling 0.8 1.35 V

High-level threshold Input rising 1.3 2.0 V

Schmitt trigger hysteresis 0.3 0.8 V

Low-level output IoI = 100uA 0.2 V

High-level output

Ioh = -100uA

VDD-

0.2

Ioh = -2mA 2.4 V

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Pin description STA308A

4 Pin description

Master volume override (MVO)

This pin enables the user to bypass the volume control on all channels. When MVO is pulled high, the master volume register is set to 0x00, which corresponds to its full scale setting. The master volume register setting offsets the individual channel volume settings, which default to 0 dB.

Serial data in (SDI_12, SDI_34, SDI_56, SDI_78)

Audio information enters the device here. Six format choices are available including I2S, left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.

RESET

Driving this pin low turns off the outputs and returns all settings to their defaults.

I2C bus

The SA, SDA and SCL pins operate per the Phillips I2C specification. See Section 5.

Phase locked loop (PLL)

The phase locked loop section provides the system timing signals and CKOUT.

Clock output (CKOUT)

System synchronization and master clocks are provided by the CKOUT.

PWM outputs (OUT1 through OUT8)

The PWM outputs provide the input signal for the power devices.

External amplifier power-down (EAPD)

This signal can be used to control the power-down of DDX power devices.

Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)

These are the outputs for audio information. Six different formats are available including I2S, left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.

Device power-down (PWDN)

Pulling PWDN low begins the power-down sequence which puts the STA308A into a low-power state. EAPD (pin 51) goes low approximately 30 ms later.

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STA308A I2C bus operation

5 I2C bus operation

The STA308A supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master).

This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver.

The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA308A is always a slave device in all of its communications.

5.1 Communication protocol

5.1.1 Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition.

5.1.2 Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.

5.1.3 Stop condition

STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA308A and the bus master.

5.1.4 Data input

During the data input the STA308A samples the SDA signal on the rising edge of clock SCL.

For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

5.2 Device addressing

To start communication between the master and the Omega DDX core, the master must initiate with a start condition. Following this, the master sends 8 bits onto the SDA line (MSB first) corresponding to the device select address and read or write mode.

The 7 most significant bits are the device address identifiers, corresponding to the I definition. In the STA308A the I port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.

The 8 for write mode. After a START condition the STA308A identifies on the bus the device

bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0

C interface has two device addresses depending on the SA

C bus

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I2C bus operation STA308A

address and if a match is found, it acknowledges the identification on SDA bus during the

-bit time. The byte following the device identification byte is the internal space address.

5.3 Write operation

Following the START condition the master sends a device select code with the RW bit set to 0. The STA308A acknowledges this and the writes for the byte of internal address.

After receiving the internal byte address the STA308A again responds with an acknowledgement.

5.3.1 Byte write

In the byte write mode the master sends one data byte, this is acknowledged by the Omega DDX core. The master then terminates the transfer by generating a STOP condition.

5.3.2 Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer.

Figure 4. Write mode sequence

BYTE

WRITE

MULTIBYTE

WRITE

DEV-ADDR

START

DEV-ADDR

START

ACK

Figure 5. Read mode sequence

CURRENT ADDRESS

READ

RANDOM

ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

START

DEV-ADDR

ACK

RW=

ACK

HIGH

ACK

NO ACK

DATA

SUB-ADDR

DATA

SUB-ADDR

ACK

START RW

ACK

START RW

ACK

STOP

DEV-ADDR

DATA

DEV-ADDR

DATA IN

ACK

STOP

NO ACK

DATA

STOP

NO ACK

DATA

STOP

DATA

DATA IN

CK NO ACK

DATA

STOP

DATA

STOP

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STA308A Application reference schematic

6 Application reference schematic

Figure 6. Reference schematic for STA308A-based application

STMicroelect

+3.3V

2.2UF

6.3VDC

EIA3216_A

2.2UF

6.3VDC

EIA3216_A

C12

100NF

Y5V

EIA0603

C12

100NF

Y5V

EIA0603

+3.3V

C20

100NF

Y5V

EIA0603

C20

100NF

Y5V

1 2

EIA0805

EIA0603

EIA0805

1 2

600 ohm@100mhz

EAPD

0000-0603

+3.3V

C14

100NF

Y5V

EIA0603

600 ohm@100mhz

STMicroelect

Title

+3.3V

C145

C18

100NF

Y5V

EIA0603

CH1_A

C147 1000PF

PWRDWN

CH1_B

NPO

EIA0805

CH5_A

CH2_B

CH2_A

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

R14

NC 46

GND_5

OUT2_B

OUT2_A

OUT1_B OUT1_A

EAPD

VDD3.3_6

GND_6

NC 54

BICKO

LRCKO

SDO_12 SDO_34

VDD3.3_7

GND_7

NC 61

SDO_56 SDO_78

PWDN

VDD3.3_13SDI_129SDI_348GND_213RESET

MVO

TEST_MODE2GND_14NC 5

0000-0603

CH5_B

CH3_B

CH3_A

CH4_A

CH4_B

SDI_56

SDATA2

SDATA1

LRCK

SDATA0

BICK

NC 37

GND_4

VDD3.3_4

OUT3_A43OUT3_B42OUT4_A41OUT4_B40OUT5_A39OUT5_B38OUT6_A34OUT6_B

VDD3.3_5

SDI_786BICKI11LRCKI10VDD3.3_212NC 14

CH6_B

CH6_A

PLL_BYPASS

OUT7_A OUT7_B OUT8_A OUT8_B VDD3.3_3 GND_3 NC 26 CKOUT VDD3.3_PLL GNDA_PLL VDDA_PLL PLL_FILTER XTI SCL SDA SA

C157

C155

NPO

47PF

NPO

1000PF

STA308AU2STA308A

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

EIA0603

+3.3V

C25

C23

100NF

Y5V

EIA0603

SDA

VDDA

SCL

MCLK

C22

C24

22UF

6.3VDC

22UF

6.3VDC

100NF

Y5V

100NF

Y5V

C19

R15

3.40K

R15

3.40K

EIA3528_B

EIA0603

220PF

NPO

EIA0603

220PF

NPO

EIA0603

0603

The PLL filter must be placed as close

GNDA

C16

100PF

NPO

EIA0603

100PF

NPO

EIA0603

C15

1200PF

X7R

EIA0603

1200PF

X7R

EIA0603

as possible to the STA308A pins

+3.3V

100NF

Y5V

EIA0603

100NF

Y5V

100NF

Y5V

EIA0603

100NF

Y5V

EIA0603

POWER_ON_RST

+3.3V

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Registers STA308A

7 Registers

7.1 Register summary

Table 8. Register summary

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

Configuration

0x00 CONFA COS1 COS0 DSPB IR1 IR0 MCS2 MCS1 MCS0

0x01 ConfB SAIFB SAI3 SAI2 SAI1 SAI0

0x02 ConfC SAOFB SAO3 SAO2 SAO1 SAO0

0x03 ConfD MPC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

0x04 ConfE C8BO C7BO C6BO C5BO C4BO C3BO C2BO C1BO

0x05 ConfF PWMS2 PWMS1 PWMS0 BQL PSL DEMP DRC HPB

0x06 ConfG MPCV DCCV HPE AM2E AME COD SID PWMD

0x07 ConfH ECLE LDTE BCLE IDE ZDE SVE ZCE NSBW

0x08 ConfI EAPD PSCE

Volume control

0x09 MMUTE MMUTE

0x0A Mvol MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0

0x0B C1Vol C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0

0x0C C2Vol C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0

0x0D C3Vol C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0

0x0E C4Vol C4V7 C4V6 C4V5 C4V4 C4V3 C4V2 C4V1 C4V0

0x0F C5Vol C5V7 C5V6 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0

0x10 C6Vol C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0

0x11 C7Vol C7V7 C7V6 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0

0x12 C8Vol C8V7 C8V6 C8V5 C8V4 C8V3 C8V2 C8V1 C8V0

0x13 C1VTMB C1M C1VBP C1VT4 C1VT3 C1VT2 C1VT1 C1VT0

0x14 C2VTMB C2M C2VBP C2VT4 C2VT3 C2VT2 C2VT1 C2VT0

0x15 C3VTMB C3M C3VBP C3VT4 C3VT3 C3VT2 C3VT1 C3VT0

0x16 C4VTMB C4M C4VBP C4VT4 C4VT3 C4VT2 C4VT1 C4VT0

0x17 C5VTMB C5M C5VBP C5VT4 C5VT3 C5VT2 C5VT1 C5VT0

0x18 C6VTMB C6M C6VBP C6VT4 C6VT3 C6VT2 C6VT1 C6VT0

0x19 C7VTMB C7M C7VBP C7VT4 C7VT3 C7VT2 C7VT1 C7VT0

0x1A C8VTMB C8M C8VBP C8VT4 C8VT3 C8VT2 C8VT1 C8VT0

Input mapping

0x1B C12im C2IM2 C2IM1 C2IM0 C1IM2 C1IM1 C1IM0

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STA308A Registers

Table 8. Register summary (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x1C C34im C4IM2 C4IM1 C4IM0 C3IM2 C3IM1 C3IM0

0x1D C56im C6IM2 C6IM1 C6IM0 C5IM2 C5IM1 C5IM0

0x1E C78im C8IM2 C8IM1 C8IM0 C7IM2 C7IM1 C7IM0

AutoMode

0x1F Auto1 AMDM AMGC2 AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0

0x20 Auto2 SUB RSS1 RSS0 CSS1 CSS0 FSS

0x21 Auto3 AMAM2 AMAM1 AMAM0 AMAME MSA AMPS

0x22 PreEQ XO2 XO1 XO0 PEQ4 PEQ3 PEQ2 PEQ1 PEQ0

0x23 Ageq AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0

0x24 Bgeq BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0

0x25 Cgeq CGEQ4 CGEQ3 CGEQ2 CGEQ1 CGEQ0

0x26 Dgeq DGEQ4 DGEQ3 DGEQ2 DGEQ1 DGEQ0

0x27 Egeq EGEQ4 EGEQ3 EGEQ2 EGEQ1 EGEQ0

Processing loop

0x28 BQlp C8BLP C7BLP C6BLP C5BLP C4BLP C3BLP C2BLP C1BLP

AMBMXE

AMBMME

0x29 MXlp C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP

Processing pypass

0x2A EQbp C8EQBP C7EQBP C6EQBP

0x2B ToneBP C8TCB C7TCB C6TCB C5TCB C4TCB C3TCB C2TCB C1TCB

Tone control

0x2C Tone TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

Dynamics control

0x2D C1234ls C4LS1 C4LS0 C3LS1 C3LS0 C2LS1 C2LS0 C1LS1 C1LS0

0x2E C5678ls C8LS1 C8LS0 C7LS1 C7LS0 C6LS1 C6LS0 C5LS1 C5LS0

0x2F L1ar L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

0x30 L1atrt L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

0x31 L2ar L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

0x32 L2atrt L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

PWM output timing

0x33 C12ot C2OT2 C2OT1 C2OT0 C1OT2 C1OT1 C1OT0

0x34 C34ot C4OT2 C4OT1 C4OT0 C3OT2 C3OT1 C3OT0

0x35 C56ot C6OT2 C6OT1 C6OT0 C5OT2 C5OT1 C5OT0

0x36 C78ot C8OT2 C8OT1 C8OT0 C7OT2 C7OT1 C7OT0

S output channel mapping

0x37 C12om C2OM2 C2OM1 C2OM0 C1OM2 C1OM1 C1OM0

C5EQBP

C4EQBP C3EQBP C2EQBP C1EQBP

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