ST STA308A User Manual

Multi-channel digital audio processor with DDX™

Features

! 8 channels of 24-bit DDX

! >100 dB SNR and dynamic range

! Selectable 32 kHz - 192 kHz input sample rates

! 6 channels of DSD/SACD input

! Digital gain/attenuation +58 dB to -100 dB in

0.5 dB steps

! Soft volume update

! Individual channel and master gain/attenuation

plus channel trim (-10 dB to +10 dB)

! Up to 10 independent 32-bit user

programmable biquads (EQ) per channel

! Bass/treble tone control

! Pre and post EQ full 8-channel input mix on all

8 channels

! Dual independent limiters/compressors

! Dynamic range compression or anti-clipping

modes

! AutoModes:

– 5-band graphic EQ
– 32 preset EQ curves (rock, jazz, pop, etc.)
– Automatic volume controlled loudness
– 5.1 to 2-channel downmix
– Simultaneous 5.1- and 2-channel downmix

outputs
– 3 preset volume curves
– 2 preset anti-clipping modes
– Preset movie nighttime listening mode
– Preset TV channel/commercial AGC mode
– 5.1, 2.1 bass management configurations
– AM frequency automatic output PWM

frequency shifting
– 8 preset crossover filters

! Individual channel and master soft/hard mute

! Automatic zero-detect and invalid input mute

! Automatic invalid input detect mute

®

STA308A

TQFP64

! Advanced PopFree operation

! Advanced AM interference frequency

switching and noise suppression modes

2

! I

S output channel mapping function

! Independent channel volume and DSP bypass

! Channel mapping of any input to any

processing/DDX

! DC blocking selectable high-pass filter

! Selectable per-channel DDX

or binary PWM output

! Max power correction for lower full-power THD

! Variable per channel DDX

! 192 kHz internal processing sample rate, 24-bit

to 36-bit precision

Description

The STA308A is a single chip solution for digital
audio processing and control in multi-channel
applications. It provides output capabilities for

®

DDX

(direct digital amplification). In conjunction
with a DDX
quality, high-efficiency, all digital amplification.
The device is extremely versatile, allowing for
input of most digital formats including 6.1/7.1­channel and 192 kHz, 24-bit DVD-audio,
DSD/SACD. In 5.1 application the additional 2
channels can be used for audio line-out or
headphone drive. In speaker mode, with 8
channel outputs in parallel, the STA308A can
deliver 1 W (maximum).

Table 1. Device summary

STA308A TQFP64

®

power device, it provides high-

Order code Package

®

channel

®

damped ternary

®

o

utput delay control

July 2007 Rev 4 1/63

www.st.com

63

Contents STA308A

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5I

2

C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.2.1 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.2.2 Configuration register B (0x01) - serial input formats . . . . . . . . . . . . . . 23

7.2.3 Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 25

7.2.4 Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.2.5 Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.2.6 Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/63

STA308A Contents

7.2.7 Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2.8 Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2.9 Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.2.10 Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.11 Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.12 Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.13 Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.14 Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.15 Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2.16 Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.17 Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.18 Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.19 Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2.20 Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 33

7.2.21 Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 33

7.2.22 Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 33

7.2.23 Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 34

7.2.24 Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 34

7.2.25 Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 34

7.2.26 Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 34

7.2.27 Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 34

7.2.28 Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 36

7.2.29 Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 36

7.2.30 Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 36

7.2.31 Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 36

7.2.32 AUTO1 - AutoModes EQ, volume, GC (0x1F) . . . . . . . . . . . . . . . . . . . . 37

7.2.33 AUTO2 - AutoModes bass management2 (0x20) . . . . . . . . . . . . . . . . . 38

7.2.34 AUTO3 - AutoMode AM/pre-Scale/bass management scale (0x21) . . . 39

7.2.35 PREEQ - Preset EQ settings (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2.36 AGEQ - graphic EQ 80-Hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.37 BGEQ - graphic EQ 300-Hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.38 CGEQ - graphic EQ 1-kHz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.39 DGEQ - graphic EQ 3-kHz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.40 EGEQ - graphic EQ 8-kHz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2.41 Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 42

7.2.42 Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 43

7.2.43 EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3/63

Contents STA308A

7.2.44 Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.2.45 Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.2.46 Channel limiter select channels 1,2,3,4 (0x2D) . . . . . . . . . . . . . . . . . . . 44

7.2.47 Channel limiter select channels 5,6,7,8 (0x2E) . . . . . . . . . . . . . . . . . . . 44

7.2.48 Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.2.49 Limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.50 Limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.51 Limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.52 Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.2.53 Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2.54 Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2.55 Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.2.56 Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.2.57 Channel I

7.2.58 Channel I

7.2.59 Channel I

7.2.60 Channel I

2

S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 50

2

S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 50

2

S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 50

2

S output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 51

7.2.61 Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2.62 Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.2.63 Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 51

7.2.64 Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 52

7.2.65 Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 52

7.2.66 Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 52

7.2.67 Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 52

7.2.68 Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 52

7.2.69 Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 52

7.2.70 Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 52

7.2.71 Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 53

7.2.72 Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 53

7.2.73 Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 53

7.2.74 Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 53

7.2.75 Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 53

7.2.76 Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 53

7.2.77 Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 53

7.2.78 Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.3 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.4 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4/63

STA308A Contents

7.5 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.6 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.1 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.2 Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.2.1 MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.3 Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.3.1 DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.4 PSCorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52) . . . . . . . . . . . . . . . 59

8.4.2 PSC3: correction normalization value (CNV) (0x53) . . . . . . . . . . . . . . . 59

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 61

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5/63

List of tables STA308A

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 7. DC electrical characteristics: 3.3-V buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. RAM block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6/63

STA308A List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Pin connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5. Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. Reference schematic for STA308A-based application . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 8. Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 9. TQFP64 (10 x 10 x 1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . 58

7/63

Block diagram STA308A

(

)

1 Block diagram

Figure 1. Block diagram

LRCKI

BICKI

SDI12

SDI34

SDI56

SDI78

PLLB

SERIAL

CHANNEL
MAPPING

PLL

XTI

SA

DATA

IN

SYSTEM TIMING

CKOUT

VARIABLE

OVER-

SAMPLING

Figure 2. Channel signal flow

6 Inputs
From DSD

DSD

Conversion

Interp_Rate

SCL

SDA

I2C

SYSTEM

CONTROL

POWER
DOWN

PWDN

MVO

TREBLE,

BASS, EQ
BIQUADS

EAPD

OVERSAMPLING

VOLUME
LIMITING

VARIABLE

DOWN-

SAMPLING

DDX

SERIAL

DATA

OUT

OUT1A/B

OUT2A/B

OUT3A/B

OUT4A/B

OUT5A/B

OUT6A/B

OUT7A/B

OUT8A/B

LRCKO

BICKO
SDO12

SDO34

SDO56

SDO78

8 Inputs
From I2S

From
Mix#1
Engine
Or
Previous
Channel
Biq ua d # 1 0
Output
(CxBLP)

PreScale

Hard Set to

-18dB when

AutoMode EQ

(AMEQ)

1x,2x,4x

Interp

Distortion

Compensation

High - Pa s s

Filte r

User Progammable

Biquad #1 when

High-Pass Bypassed

(HPB)

Mapping/

Mix #1

DSDE

NS C_Con PWM

Biq ua d#2Biquad#3Biquad

Hard Set Coeffecients when AutoMode EQ

(AMEQ)

8/63

Biq ua ds

B/ T

Biqu a d#5Biquad#6Biquad

#4

Mix #2

Coeffec ients when

Bass Management

#7

Hard Set

Aut oM od e

Cross over

(AMBMXE)

Vol um e

Limiter

Biquad

#8

Hard Set

Coeffec ients when

DeEmphasis

Enable d
(DEMP)

2x

Interp

DDX
Output

Bas s

User Pro grammable
Biquads #9 and #10

When Tone Bypass ed

(CxTCB)

Treble

To
Mix#2
Engine

STA308A Pin connections

2 Pin connections

Figure 3. Pin connection (Top view)

VDD

SDO_34

SDO_12

LRCKONCBICKO

GND

VDD

EAPD

OUT1_A

OUT8_B

OUT8_A

OUT1_B

OUT7_B

OUT7_A

48

OUT2_A

47

OUT2_B

46

NC

45

GND

44

VDD

43

OUT3_A

42

OUT3_B

41

OUT4_A

40

OUT4_B

39

OUT5_A

38

OUT5_B

37

NC

36

GND

35

VDD

34

OUT6_A

33

OUT6_B

STA308APINCON

MVO

GND

VDD

GND

SDI_78

SDI_56

SDI_34

SDI_12

LRCKI

BICKI

VDD

GND

RESET

PLLB

NC

NC

SDO_78

PWDN

63

64

1

2

3

4

5

6

7

8

9

10

12

13

14

15

16

17 18 19 20 21

SA

SDA

GND61NC62SDO_56

59 58 57 565455 53 52 51 50 49

60

22 23 24 25 26

SCL

XTI

FILTER_PLL

NC

GNDA

VDDA

NC

CKOUT

271128 29 30 31 32

VDD

GND

Table 2. Pin description

Pin Type Name Description

1 5-V tolerant TTL input buffer MVO/DSD_CLK

6 5-V tolerant TTL input buffer SDI_78/DSD_6

7 5-V tolerant TTL input buffer SDI_56/DSD_5

8 5-V tolerant TTL input buffer SDI_34/DSD_4

9 5-V tolerant TTL input buffer SDI_12/DSD_3

10 5-V tolerant TTL input buffer LRCKI/DSD_2

11 5-V tolerant TTL input buffer BICKI/DSD_1

15

16

5-V tolerant TTL schmitt
trigger input buffer

CMOS input buffer with
pull-down

RESET Global reset

PLL_BYPASS Bypass phase locked loop

Master volume override/
DSD input clock

Input serial data channels 7 & 8/
DSD input channel 6

Input serial data channels 5 & 6/
DSD input channel 5

Input serial data channels 3 & 4/
DSD input channel 4

Input serial data channels 1 & 2/
DSD input channel 3

Input left/right clock/
DSD input channel 2

Input serial clock/
DSD input channel 1

9/63

Pin connections STA308A

Table 2. Pin description (continued)

Pin Type Name Description

17

CMOS input buffer with
pull-down

SA Select address (I

Bidirectional buffer: 5-V

18

tolerant TTL schmitt trigger
input; 3.3-V capable 2mA

SDA Serial data (I

slew-rate controlled output.

19

20

5-V tolerant TTL schmitt
trigger input buffer

5-V tolerant TTL schmitt
trigger input buffer

SCL Serial clock (I

XTI Crystal oscillator input (clock input)

21 Analog pad FILTER_PLL PLL filter

23 Analog ground GNDA PLL ground

24 3.3V analog supply voltage VDDA PLL supply

25

29

30

31

3.3-V capable TTL tristate
4mA output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

CKOUT Clock output

OUT8B PWM channel 8 output B

OUT8A PWM channel 8 output A

OUT7B PWM channel 7 output B

2

C)

2

C)

2

C)

32

33

34

38

39

40

41

42

43

47

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

OUT7A PWM channel 7 output A

OUT6B PWM channel 6 output B

OUT6A PWM channel 6 output A

OUT5B PWM channel 5 output B

OUT5A PWM channel 5 output A

OUT4B PWM channel 4 output B

OUT4A PWM channel 4 output A

OUT3B PWM channel 3 output B

OUT3A PWM channel 3 output A

OUT2B PWM channel 2 output B

10/63

STA308A Pin connections

Table 2. Pin description (continued)

Pin Type Name Description

48

49

50

51

55

56

57

58

62

63

64

3,12,28,35,
44,52,59

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 4mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

3.3-V capable TTL 2mA
output buffer

5-V tolerant TTL schmitt
trigger input buffer

3.3-V digital supply voltage VDD 3.3-V supply

OUT2A PWM channel 2 output A

OUT1B PWM channel 1 output B

OUT1A PWM channel 1 output A

EAPD Ext. amp power-down

BICKO Output serial clock

LRCKO Output left/right clock

SDO_12 Output serial data channels 1&2

SDO_34 Output serial data channels 3&4

SDO_56 Output serial data channels 5&6

SDO_78 Output serial data channels 7&8

PWDN Device power-down

2,4,13,27,
36,45,53,60

5, 14, 22,
26,37,46,54,
61

Digital ground GND Ground

NC Not connected

11/63

Electrical specification STA308A

3 Electrical specification

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

V

V

V

V

T

T

DD

DDA

i

o

stg

amb

3.3-V I/O power supply -0.5 4 V

3.3-V logic power supply -0.5 4 V

Voltage on input pins -0.5

Voltage on output pins -0.5

Storage temperature -40 150 °C

Ambient operating temperature -40 90 °C

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Min Typ Max Unit

R

thj-amb

Thermal resistance, junction to ambient 85 °C/W

3.3 Recommended operating condition

Table 5. Recommended operating condition

VDD +

0.5

VDD +

0.3

V

V

Symbol Parameter Min Typ Max Unit

V

V

T

DD

DDA

j

I/O power supply 3.0 3.6 V

Logic power supply 3.0 3.6 V

Operating junction temperature -40 125 °C

12/63

STA308A Electrical specification

3.4 Electrical specifications

The following specifications are valid for VDD = 3.3V ± 0.3V, VDDA = 3.3V ± 0.3V and
Tamb = 0 to 70 °C, unless otherwise stated

Table 6. General interface electrical specifications

Symbol Parameter Conditions Min Typ Max Unit

I

il

I

ih

Low-level input no pull-up Vi = 0V 1

High-level input no
pull-down

V

= VDD 2µA

i

(1)

µA

I

OZ

V

esd

1. The leakage currents are generally very small, < 1 nA. The values given here are maximum after an
electrostatic stress on the pin.

Table 7. DC electrical characteristics: 3.3-V buffers

Tristate output leakage
without pull-up/down

Electrostatic protection
(human body model)

= VDD 2µA

V

i

Leakage < 1µA2000V

Symbol Parameter Conditions Min Typ Max Unit

V

IL

V

IH

V

ILhyst

V

IHhyst

V

hyst

V

ol

V

oh

Low-level input voltage 0.8 V

High-level input voltage 2.0 V

Low-level threshold Input falling 0.8 1.35 V

High-level threshold Input rising 1.3 2.0 V

Schmitt trigger hysteresis 0.3 0.8 V

Low-level output IoI = 100uA 0.2 V

High-level output

Ioh = -100uA

VDD-

0.2

V

Ioh = -2mA 2.4 V

13/63

Pin description STA308A

4 Pin description

Master volume override (MVO)

This pin enables the user to bypass the volume control on all channels. When MVO is pulled
high, the master volume register is set to 0x00, which corresponds to its full scale setting.
The master volume register setting offsets the individual channel volume settings, which
default to 0 dB.

Serial data in (SDI_12, SDI_34, SDI_56, SDI_78)

Audio information enters the device here. Six format choices are available including I2S,
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.

RESET

Driving this pin low turns off the outputs and returns all settings to their defaults.

I2C bus

The SA, SDA and SCL pins operate per the Phillips I2C specification. See Section 5.

Phase locked loop (PLL)

The phase locked loop section provides the system timing signals and CKOUT.

Clock output (CKOUT)

System synchronization and master clocks are provided by the CKOUT.

PWM outputs (OUT1 through OUT8)

The PWM outputs provide the input signal for the power devices.

External amplifier power-down (EAPD)

This signal can be used to control the power-down of DDX power devices.

Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)

These are the outputs for audio information. Six different formats are available including I2S,
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.

Device power-down (PWDN)

Pulling PWDN low begins the power-down sequence which puts the STA308A into a
low-power state. EAPD (pin 51) goes low approximately 30 ms later.

14/63

STA308A I2C bus operation

5 I2C bus operation

The STA308A supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master).

This protocol defines any device that sends data on to the bus as a transmitter and any
device that reads the data as a receiver.

The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA308A is always a slave device in all of its communications.

5.1 Communication protocol

5.1.1 Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.

5.1.2 Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.

5.1.3 Stop condition

STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA308A and the bus master.

5.1.4 Data input

During the data input the STA308A samples the SDA signal on the rising edge of clock SCL.

For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.

5.2 Device addressing

To start communication between the master and the Omega DDX core, the master must
initiate with a start condition. Following this, the master sends 8 bits onto the SDA line (MSB
first) corresponding to the device select address and read or write mode.

The 7 most significant bits are the device address identifiers, corresponding to the I
definition. In the STA308A the I
port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.

th

The 8
for write mode. After a START condition the STA308A identifies on the bus the device

bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0

2

C interface has two device addresses depending on the SA

2

C bus

15/63

I2C bus operation STA308A

A

A

A

A

A

A

A

address and if a match is found, it acknowledges the identification on SDA bus during the

th

9

-bit time. The byte following the device identification byte is the internal space address.

5.3 Write operation

Following the START condition the master sends a device select code with the RW bit set
to 0. The STA308A acknowledges this and the writes for the byte of internal address.

After receiving the internal byte address the STA308A again responds with an
acknowledgement.

5.3.1 Byte write

In the byte write mode the master sends one data byte, this is acknowledged by the Omega
DDX core. The master then terminates the transfer by generating a STOP condition.

5.3.2 Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.

Figure 4. Write mode sequence

BYTE

WRITE

MULTIBYTE

WRITE

DEV-ADDR

START

DEV-ADDR

START

ACK

RW

ACK

RW

Figure 5. Read mode sequence

CURRENT
ADDRESS

READ

RANDOM

ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

START

START

START

START

DEV-ADDR

DEV-ADDR

DEV-ADDR

DEV-ADDR

ACK

RW

ACK

RW

RW=

ACK

HIGH

ACK

RW

NO ACK

DATA

SUB-ADDR

DATA

SUB-ADDR

SUB-ADDR

SUB-ADDR

ACK

START RW

ACK

ACK

START RW

ACK

ACK

STOP

DEV-ADDR

DATA

DEV-ADDR

DATA IN

DATA IN

CK

ACK

CK

CK

STOP

CK

NO ACK

DATA

STOP

NO ACK

DATA

STOP

CK

DATA

DATA IN

CK NO ACK

DATA

CK

STOP

DATA

STOP

16/63

STA308A Application reference schematic

r

r

r

6 Application reference schematic

Figure 6. Reference schematic for STA308A-based application

STMicroelect

STMicroelect

+3.3V

C4

2.2UF

6.3VDC

EIA3216_A

C4

2.2UF

6.3VDC

EIA3216_A

+

+

C12

100NF

Y5V

EIA0603

C12

100NF

Y5V

EIA0603

+3.3V

C20

100NF

Y5V

EIA0603

C20

100NF

Y5V

1 2

EIA0805

EIA0805

EIA0603

L3

L3

EIA0805

EIA0805

1 2

600 ohm@100mhz

600 ohm@100mhz

EAPD

L1

R6

0

R6

0

0000-0603

0000-0603

+3.3V

C14

C14

100NF

100NF

Y5V

Y5V

EIA0603

EIA0603

L1

600 ohm@100mhz

600 ohm@100mhz

STMicroelect

Title

Title

Title

+3.3V

+3.3V

C145

C145

C18

C18

100NF

100NF

100NF

100NF

Y5V

Y5V

Y5V

Y5V

EIA0603

EIA0603

EIA0603

EIA0603

CH1_A

C147 1000PF

C147 1000PF

PWRDWN

CH1_B

NPO

NPO

EIA0805

EIA0805

CH5_A

CH2_B

CH2_A

45

47

48

U2

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

0

0

R14

R14

46

NC 46

GND_5

OUT2_B

OUT2_A

OUT1_B
OUT1_A

EAPD

VDD3.3_6

GND_6

NC 54

BICKO

LRCKO

SDO_12
SDO_34

VDD3.3_7

GND_7

NC 61

SDO_56
SDO_78

PWDN

VDD3.3_13SDI_129SDI_348GND_213RESET

MVO

TEST_MODE2GND_14NC 5

1

0000-0603

0000-0603

CH5_B

CH3_B

CH3_A

CH4_A

CH4_B

SDI_56

7

SDATA2

SDATA1

LRCK

SDATA0

BICK

37

NC 37

36

GND_4

35

14

VDD3.3_4

15

44

OUT3_A43OUT3_B42OUT4_A41OUT4_B40OUT5_A39OUT5_B38OUT6_A34OUT6_B

VDD3.3_5

SDI_786BICKI11LRCKI10VDD3.3_212NC 14

5

CH6_B

CH6_A

33

PLL_BYPASS

16

OUT7_A
OUT7_B
OUT8_A
OUT8_B
VDD3.3_3
GND_3
NC 26
CKOUT
VDD3.3_PLL
GNDA_PLL
VDDA_PLL
PLL_FILTER
XTI
SCL
SDA
SA

C157

C157

C155

C155

NPO

NPO

47PF

47PF

NPO

NPO

1000PF

1000PF

STA308AU2STA308A

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

EIA0603

EIA0603

EIA0603

EIA0603

+3.3V

C25

C25

C23

C23

100NF

100NF

100NF

100NF

Y5V

Y5V

Y5V

Y5V

EIA0603

EIA0603

EIA0603

EIA0603

SDA

VDDA

SCL

MCLK

C22

C22

+

+

C24

C24

22UF

6.3VDC

22UF

6.3VDC

100NF

Y5V

100NF

Y5V

C19

C19

R15

3.40K

R15

3.40K

EIA3528_B

EIA3528_B

EIA0603

EIA0603

220PF

NPO

EIA0603

220PF

NPO

EIA0603

0603

0603

The PLL filter must be placed as close

GNDA

C16

C16

100PF

NPO

EIA0603

100PF

NPO

EIA0603

C15

C15

1200PF

X7R

EIA0603

1200PF

X7R

EIA0603

as possible to the STA308A pins

+3.3V

C6

100NF

Y5V

EIA0603

C6

100NF

Y5V

C5

100NF

Y5V

EIA0603

C5

100NF

Y5V

EIA0603

EIA0603

POWER_ON_RST

+3.3V

17/63

Registers STA308A

7 Registers

7.1 Register summary

Table 8. Register summary

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

Configuration

0x00 CONFA COS1 COS0 DSPB IR1 IR0 MCS2 MCS1 MCS0

0x01 ConfB SAIFB SAI3 SAI2 SAI1 SAI0

0x02 ConfC SAOFB SAO3 SAO2 SAO1 SAO0

0x03 ConfD MPC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

0x04 ConfE C8BO C7BO C6BO C5BO C4BO C3BO C2BO C1BO

0x05 ConfF PWMS2 PWMS1 PWMS0 BQL PSL DEMP DRC HPB

0x06 ConfG MPCV DCCV HPE AM2E AME COD SID PWMD

0x07 ConfH ECLE LDTE BCLE IDE ZDE SVE ZCE NSBW

0x08 ConfI EAPD PSCE

Volume control

0x09 MMUTE MMUTE

0x0A Mvol MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0

0x0B C1Vol C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0

0x0C C2Vol C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0

0x0D C3Vol C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0

0x0E C4Vol C4V7 C4V6 C4V5 C4V4 C4V3 C4V2 C4V1 C4V0

0x0F C5Vol C5V7 C5V6 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0

0x10 C6Vol C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0

0x11 C7Vol C7V7 C7V6 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0

0x12 C8Vol C8V7 C8V6 C8V5 C8V4 C8V3 C8V2 C8V1 C8V0

0x13 C1VTMB C1M C1VBP C1VT4 C1VT3 C1VT2 C1VT1 C1VT0

0x14 C2VTMB C2M C2VBP C2VT4 C2VT3 C2VT2 C2VT1 C2VT0

0x15 C3VTMB C3M C3VBP C3VT4 C3VT3 C3VT2 C3VT1 C3VT0

0x16 C4VTMB C4M C4VBP C4VT4 C4VT3 C4VT2 C4VT1 C4VT0

0x17 C5VTMB C5M C5VBP C5VT4 C5VT3 C5VT2 C5VT1 C5VT0

0x18 C6VTMB C6M C6VBP C6VT4 C6VT3 C6VT2 C6VT1 C6VT0

0x19 C7VTMB C7M C7VBP C7VT4 C7VT3 C7VT2 C7VT1 C7VT0

0x1A C8VTMB C8M C8VBP C8VT4 C8VT3 C8VT2 C8VT1 C8VT0

Input mapping

0x1B C12im C2IM2 C2IM1 C2IM0 C1IM2 C1IM1 C1IM0

18/63

STA308A Registers

Table 8. Register summary (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x1C C34im C4IM2 C4IM1 C4IM0 C3IM2 C3IM1 C3IM0

0x1D C56im C6IM2 C6IM1 C6IM0 C5IM2 C5IM1 C5IM0

0x1E C78im C8IM2 C8IM1 C8IM0 C7IM2 C7IM1 C7IM0

AutoMode

0x1F Auto1 AMDM AMGC2 AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0

0x20 Auto2 SUB RSS1 RSS0 CSS1 CSS0 FSS

0x21 Auto3 AMAM2 AMAM1 AMAM0 AMAME MSA AMPS

0x22 PreEQ XO2 XO1 XO0 PEQ4 PEQ3 PEQ2 PEQ1 PEQ0

0x23 Ageq AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0

0x24 Bgeq BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0

0x25 Cgeq CGEQ4 CGEQ3 CGEQ2 CGEQ1 CGEQ0

0x26 Dgeq DGEQ4 DGEQ3 DGEQ2 DGEQ1 DGEQ0

0x27 Egeq EGEQ4 EGEQ3 EGEQ2 EGEQ1 EGEQ0

Processing loop

0x28 BQlp C8BLP C7BLP C6BLP C5BLP C4BLP C3BLP C2BLP C1BLP

AMBMXE

AMBMME

0x29 MXlp C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP

Processing pypass

0x2A EQbp C8EQBP C7EQBP C6EQBP

0x2B ToneBP C8TCB C7TCB C6TCB C5TCB C4TCB C3TCB C2TCB C1TCB

Tone control

0x2C Tone TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

Dynamics control

0x2D C1234ls C4LS1 C4LS0 C3LS1 C3LS0 C2LS1 C2LS0 C1LS1 C1LS0

0x2E C5678ls C8LS1 C8LS0 C7LS1 C7LS0 C6LS1 C6LS0 C5LS1 C5LS0

0x2F L1ar L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

0x30 L1atrt L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

0x31 L2ar L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

0x32 L2atrt L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

PWM output timing

0x33 C12ot C2OT2 C2OT1 C2OT0 C1OT2 C1OT1 C1OT0

0x34 C34ot C4OT2 C4OT1 C4OT0 C3OT2 C3OT1 C3OT0

0x35 C56ot C6OT2 C6OT1 C6OT0 C5OT2 C5OT1 C5OT0

0x36 C78ot C8OT2 C8OT1 C8OT0 C7OT2 C7OT1 C7OT0

2

S output channel mapping

I

0x37 C12om C2OM2 C2OM1 C2OM0 C1OM2 C1OM1 C1OM0

C5EQBP

C4EQBP C3EQBP C2EQBP C1EQBP

19/63

Registers STA308A

Table 8. Register summary (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x38 C34om C4OM2 C4OM1 C4OM0 C3OM2 C3OM1 C3OM0

0x39 C56om C6OM2 C6OM1 C6OM0 C5OM2 C5OM1 C5OM0

0x3A C78om C8OM2 C8OM1 C8OM0 C7OM2 C7OM1 C7OM0

User-defined coefficient RAM

0x3B Cfaddr1 CFA9 CFA8

0x3C C fad dr2 CFA7 CFA 6 CFA5 CFA4 CFA3 CFA 2 CFA 1 CFA0

0x3D B1cf1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

0x3E B1cf2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

0x3F B1cf3 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

0x40 B2cf1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

0x41 B2cf2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

0x42 B2cf3 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

0x43 A1cf1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16

0x44 A1cf2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

0x45 A1cf3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

0x46 A2cf1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

0x47 A2cf2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

0x48 A2cf3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

0x49 B0cf1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

0x4A B0cf2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

0x4B B0cf3 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

0x4C Cfud WA W1

0x4D MPCC1 MPCC15 MPCC14 MPCC13

0x4E MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

0x4F DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8

0x50 DCC2 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0

0x51 PSC1 RCV11 RCV10 RCV9 RCV8 RCV7 RCV6 RCV5 RCV4

0x52 PSC2 RCV3 RCV2 RCV1 RCV0 CNV11 CNV10 CNV9 CNV8

0x53 PSC3 CNV7 CNV6 CNV5 CNV4 CNV3 CNV2 CNV1 CNV0

MPCC12

MPCC11 MPCC10 MPCC9 MPCC8

20/63

STA308A Registers

7.2 Register description

7.2.1 Configuration register A (0x00)

D7 D6 D5 D4 D3 D2 D1 D0

COS1 COS0 DSPB IR1 IR0 MCS2 MCS1 MCS0

10000011

Bit RW RST Name Description

0RW1 MCS0

1RW1 MCS1

2RW0 MCS2

The DDX8000 supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4
kHz, 192 kHz, and 2.8224 MHz DSD. Therefore the internal clocks are:

" 65.536 MHz for 32 kHz
" 90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD
" 98.304 MHz for 48 kHz, 96 kHz, and 192 kHz

Master clock select: selects the ratio between the
input I2S sample frequency and the input clock.

The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs). The relationship between the input clock and the input sample rate is
determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits
determine the PLL factor generating the internal clock and the IRn bits determine the
oversampling ratio used internally.

Input sample rate

fs (kHz)

IR

1XX 011 010 001 000

MCS[2:0]

32, 44.1, 48 00 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs

88.2, 96 01 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs

176.4, 192 10 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs

DSD 11 2 * fs 4 * fs 6 * fs 8 * fs 10 * fs

Interpolation ratio select

Bit RW RST Name Description

3 RW 0 IR0 Interpolation ratio select: selects internal

interpolation ratio based on input I

4RW 0 IR1

frequency

The STA308A has variable interpolation (oversampling) settings such that internal
processing and DDX output rates remain consistent. The first processing block interpolates
by either 4 times, 2 times, or 1 time (pass-through).

2

S sample

The oversampling ratio of this interpolation is determined by the IR bits.

21/63

Registers STA308A

I

IR[1,0]

Input sample rate

Fs (kHz)

1st stage interpolation ratio

00 32 4-times oversampling

00 44.1 4-times oversampling

00 48 4-times oversampling

01 88.2 2-times oversampling

01 96 2-times oversampling

10 176.4 Pass-through

10 192 Pass-through

11 DSD DSD to 176.4 kHz conversion

Bit RW RST Name Description

DSP bypass bit:

0 RW 0 DSPB

0: normal operation
1: bypass of biquad and bass/treble functions

Setting the DSPB bit bypasses the biquad function of the Omega DDX core.

COS[1,0] CKOUT frequency

00 PLL output

01 PLL output / 4

10 PLL output / 8

11 PLL output / 16

22/63

STA308A Registers

7.2.2 Configuration register B (0x01) - serial input formats

D7 D6 D5 D4 D3 D2 D1 D0

SAIFB SAI3 SAI2 SAI1 SAI0

00000

Bit RW RST Name Description

0 RW 0 SAI0

1 RW 0 SAI1

2 RW 0 SAI2

3 RW 0 SAI3

Serial data interface

The STA308A audio serial input interfaces with standard digital audio components and
accepts a number of serial data formats. STA308A always acts a slave when receiving audio
input from standard digital audio components. Serial data for eight channels is provided
using 6 input pins: left/right clock LRCKI (pin 10), serial clock BICKI (pin 11), serial data 1
and 2 SDI12 (pin 9), serial data 3 and 4 SDI34 (pin 8), serial data 5 and 6 SDI56 (pin 7), and
serial data 7 and 8 SDI78 (pin 6). The SAI/SAIFB register (Configuration Register B,
address 0x01) is used to specify the serial data format. The default serial data format is I
MSB-first. Available formats are shown in the tables and figure that follow.

Bit RW RST Name Description

Serial audio input interface format: determines the
interface format of the input serial digital audio
interface.

2

S,

Determines MSB or LSB first for all SAO formats:

4 RW 0 SAIFB

0: MSB first
1: LSB first

Note: Serial input and output formats are specified separately

For example, SAI = 1110 and SAIFB = 1 would specify right-justified 16-bit data, LSB-first.

23/63

Registers STA308A

The table below lists the serial audio input formats supported by STA308A as related to
BICKI = 32

* fs, 48 * fs, 64 * fs, where sampling rate, fs = 32, 44.1, 48, 88.2, 96, 176.4,

192 kHz.

BICKI SAI [3:0] SAIFB Interface format

32 * fs

1100 X I

1110 X Left/right-justified 16-bit data

0100 X I

0100 X I

1000 X I

0100 0 MSB-first I

1100 1 LSB-first I

0001 X Left-justified 24-bit data

2

S 15-bit data

2

S 23-bit data

2

S 20-bit data

2

S 18-bit data

2

2

S 16-bit data

S 16-bit data

48 * fs

64 * fs

0101 X Left-justified 20-bit data

1001 X Left-justified 18-bit data

1101 X Left-justified 16-bit data

0010 X Right-justified 24-bit data

0110 X Right-justified 20-bit data

1010 X Right-justified 18-bit data

1110 X Right-justified 16-bit data

2

0000 X I

0100 X I

1000 X I

0000 0 MSB-first I

1100 1 LSB-first I

S 24-bit data

2

S 20-bit data

2

S 18-bit data

2

2

S 16-bit data

S 16-bit data

0001 X Left-justified 24-bit data

0101 X Left-justified 20-bit data

1001 X Left-justified 18-bit data

1101 X Left-justified 16-bit data

0010 X Right-justified 24-bit data

0110 X Right-justified 20-bit data

1010 X Right-justified 18-bit data

1110 X Right-justified 16-bit data

24/63

STA308A Registers

7.2.3 Configuration register C (0x02) - serial output formats

D7 D6 D5 D4 D3 D2 D1 D0

SAOFB SAO3 SAO2 SAIO SAO0

00000

Bit RW RST Name Description

0RW 0 SAO0

1RW 0 SAO1

2RW 0 SAO2

3RW 0 SAO3

The STA308A features a serial audio output interface that consists of 8 channels. The serial
audio output always acts as a slave to the serial audio input interface and, therefore, all
output clocks are synchronous with the input clocks. The output sample frequency (fs) is
also equivalent to the input sample frequency. In the case of SACD/DSD input, the serial
audio output acts as a master with an output sampling frequency of 176.4 kHz. The output
serial format can be selected independently from the input format and is done via the SAO
and SAOFB bits.

Bit RW RST Name Description

Serial audio output interface format: determines the
interface format of the output serial digital audio
interface.

Determines MSB or LSB first for all SAO formats:

4RW 0 SAOFB

0: MSB first
1: LSB first

BICKI = BICKO SAO[3:0] Interface data format

2

0111 I

S data

32 * fs

1111 Left/right-justified 16-bit data

1110 I

2

S data

0001 Left-justified data

1010 Right-justified 24-bit data

48 * fs

1011 Right-justified 20-bit data

1100 Right-justified 18-bit data

1101 Right-justified 16-bit data

0000 I

2

S data

0001 Left-justified data

0010 Right-justified 24-bit data

64 * fs

0011 Right-justified 20-bit data

0100 Right-justified 18-bit data

0101 Right-justified 16-bit data

25/63

Registers STA308A

7.2.4 Configuration register D (0x03)

D7 D6 D5 D4 D3 D2 D1 D0

MPC CSZ4CSZ3CSZ2CSZ1CSZ0OM1 OM0

11000010

Bit RW RST Name Description

0RW 0 OM0

1RW 1 OM1

DDX power output mode: selects configuration of
DDX output.

The DDX power output mode selects how the DDX output timing is configured. Different
power devices use different output modes. The STA50x recommended use is OM = 10.

OM[1,0] Output stage - mode

00 STA50x/STA51xB - drop compensation

01 Discrete output stage - tapered compensation

10 STA50x/STA51xB - full power mode

11 Variable drop compensation (CSZn bits)

Bit RW RST Name Description

2RW 0 CSZ0

3RW 0 CSZ1

4RW 0 CSZ2

5RW 0 CSZ3

6RW 1 CSZ4

CSZ[4:0] Compensating pulse size

Contra size register: when OM[1,0] = 11, this register
determines the size of the DDX compensating pulse
from 0 clock ticks to 31 clock periods.

00000 0 clock period compensating pulse size

00001 1 clock period compensating pulse size

……

11111 31 clock period compensating pulse size

Bit RW RST Name Description

7RW 1 MPC

Setting the MPC bit turns on special processing that corrects the STA50x power device at
high power. This mode should lower the THD+N of a full STA50x DDX system at maximum
power output and slightly below. This mode will only be operational in OM[1,0] = 01.

26/63

Max power correction: setting of 1 enables STA50x
correction for THD reduction near maximum power
output.

STA308A Registers

7.2.5 Configuration register E (0x04)

D7 D6 D5 D4 D3 D2 D1 D0

C8BO C7BO C6BO C5BO C4BO C3BO C2BO C1BO

00000000

Bit RW RST Name Description

0RW 0 C1BO

1RW 0 C2BO

2RW 0 C3BO

3RW 0 C4BO

4RW 0 C5BO

5RW 0 C6BO

6RW 0 C7BO

7RW 0 C8BO

Each individual channel output can be set to output a binary PWM stream. In this mode
output A of a channel will be considered the positive output and output B is negative inverse.

Channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output
mode enable bits. A setting of 0 indicates ordinary
DDX tristate output. A setting of 1 indicates binary
output mode.

7.2.6 Configuration register F (0x05)

D7 D6 D5 D4 D3 D2 D1 D0

PWMS2 PWMS1 PWMS0 BQL PSL DEMP DRC HPB

00000000

Bit RW RST Name Description

0RW 0 HPB

The STA308A features an internal digital high-pass filter for the purpose of AC coupling. The
purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC
signals can cause speaker damage.

If HPB = 1, then the filter that the high-pass filter utilizes is made available as user­programmable biquad#1.

Bit RW RST Name Description

1 RW 0 DRC

Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.
When used in anti-clipping mode the limiter threshold values are constant and dependent on
the limiter settings.

High-pass filter bypass bit: setting of one bypasses
internal AC coupling digital high-pass filter

Dynamic range compression/anti-clipping
0: limiters act in anti-clipping mode

1: limiters act in dynamic range compression mode

27/63

Registers STA308A

In dynamic range compression mode the limiter threshold values vary with the volume
settings allowing a nighttime listening mode that provides a reduction in the dynamic range
regardless of the volume level.

Bit RW RST Name Description

De-emphasis:

2RW 0 DEMP

0: no de-emphasis
1: de-emphasis

By setting this bit to one de-emphasis will implemented on all channels. When this is used it
takes the place of biquad #7 in each channel and any coefficients using biquad #1 will be
ignored. DSPB (DSP bypass) bit must be set to 0 for de-emphasis to function.

Bit RW RST Name Description

Post-scale link:

3 RW 0 PSL

0: each channel uses individual post-scale value
1: each channel uses channel 1 post-scale value

Post-Scale functionality can be used for power-supply error correction. For multi-channel
applications running off the same power-supply, the post-scale values can be linked to the
value of channel 1 for ease of use and update the values faster.

Bit RW RST Name Description

Biquad link:

4RW 0 BQL

0: each channel uses coefficient values
1: each channel uses channel 1 coefficient values

For ease of use, all channels can use the biquad coefficients loaded into the channel 1
Coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to
be performed once.

Bit RW RST Name Description

7:5 RW 00 PWMS[2:0] PWM speed selection:

PWMS[1:0] PWM output speed

000 Normal speed (384 kHz) (all channels

001 Half-speed (192 kHz) (all channels

010 Double-speed (768 kHz) (all channels

011 Normal speed (channels 1-6), double-speed (channels 7-8)

100 Odd speed (341.3 kHz) (all channels)

28/63

STA308A Registers

7.2.7 Configuration register G (0x06)

D7 D6 D5 D4 D3 D2 D1 D0

MPCV DCCV HPE AM2E AME COD SID PWMD

00000000

Bit RW RST Name Description

PWM output disable:

0RW0 PWMD

1RW0 SID

2RW0 COD

Bit RW RST Name Description

0: PWM output normal
1: no PWM output

2

Serial interface (I

2

S output normal

0: I

S out) disable:

1: no I2S output

Clock output disable:
0: clock output normal

1: no clock output

AM mode enable:

3RW 0 AME

0: normal DDX operation.
1: AM reduction mode DDX operation.

The STA308A features a DDX processing mode that minimizes the amount of noise
generated in frequency range of AM radio. This mode is intended for use when DDX is
operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to
~83 dB in this mode, which is still greater than the SNR of AM radio.

Bit RW RST Name Description

AM2 mode enable:

4RW 0 AM2E

0: normal DDX operation.
1: AM2 reduction mode DDX operation.

The STA308A features a 2 DDX processing modes that minimize the amount of noise
generated in frequency range of AM radio. This second mode is intended for use when DDX
is operating in a device with an AM tuner active. This mode eliminates the noise-shaper.

Bit RW RST Name Description

DDX headphone enable:

5RW 0 HPE

0: channels 7 and 8 normal DDX operation
1: channels 7 and 8 headphone operation

Channels 7 and 8 can be configured to be processed and output in such a manner that
headphones can be driven using and appropriate output device. This signal is a differential
3-wire drive called DDX Headphone.

29/63

Registers STA308A

Bit RW RST Name Description

Distortion compensation variable enable:

6 RW 0 DCCV

0: uses preset DC coefficient.
1: uses DCC coefficient.

Bit RW RST Name Description

Max power correction variable:

7RW 0 MPCV

0: use standard MPC coefficient
1: use MPCC bits for MPC coefficient

7.2.8 Configuration register H (0x07)

D7 D6 D5 D4 D3 D2 D1 D0

ECLE LDTE BCLE IDE ZDE SVE ZCE NSBW

01111110

Bit RW RST Name Description

Noise-shaper bandwidth selection:

0 RW 0 NSBW

1: 3

rd

order NS

0: 4th order NS

Bit RW RST Name Description

Zero-crossing volume enable:

1RW1 ZCE

1: volume adjustments will only occur at digital zero­crossings
0: volume adjustments will occur immediately

The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital
zero-crossings no clicks will be audible.

Bit RW RST Name Description

Soft volume enable:

2RW1 SVE

Bit RW RST Name Description

3RW1 ZDE

1: volume adjustments use soft volume
0: volume adjustments occur immediately

Zero-detect mute enable: setting of 1 enables the
automatic zero-detect mute

Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at
the input data to each processing channel after the channel-mapping block. If any channel
receives 2048 consecutive zero value samples (regardless of fs) then that individual
channel is muted if this function is enabled.

30/63

STA308A Registers

Bit RW RST Name Description

4RW 1 IDE

Setting the IDE bit enables this function, which looks at the input I2S data and will
automatically mute if the signals are perceived as invalid.

Bit RW RST Name Description

5 RW 1 BCLE Binary output mode clock loss detection enable

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

Bit RW RST Name Description

6 RW 1 LDTE LRCLK double trigger protection enable

Actively prevents double trigger of LRCLK.

Bit RW RST Name Description

7 RW 0 ECLE Auto EAPD on clock loss

When active will issue a device power down signal (EAPD) on clock loss detection

7.2.9 Configuration register I (0x08)

Invalid input detect mute enable:
1: enable the automatic invalid input detect mute

D7 D6 D5 D4 D3 D2 D1 D0

EAPD PSCE

0 0

This feature utilizes an ADC on SDI78 that provides power supply ripple information for
correction. Registers PSC1, PSC2, PSC3 are utilized in this mode.

Bit RW RST Name Description

Power supply ripple correction enable:

0 RW 0 PSCE

Bit RW RST Name Description

7 RW 0 EAPD

0: normal operation
1: PSCorrect operation

External amplifier power down:
0: external power stage power down active

1: normal operation

31/63

Registers STA308A

7.2.10 Master mute register (0x09)

D7 D6 D5 D4 D3 D2 D1 D0

MMUTE

0

7.2.11 Master volume register (0x0A)

D7 D6 D5 D4 D3 D2 D1 D0

MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0

11111111

Note: Value of volume derived from MVOL is dependent on AMV AutoMode volume settings.

7.2.12 Channel 1 volume (0x0B)

D7 D6 D5 D4 D3 D2 D1 D0

C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0

01100000

7.2.13 Channel 2 volume (0x0C)

D7 D6 D5 D4 D3 D2 D1 D0

C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0

01100000

7.2.14 Channel 3 volume (0x0D)

D7 D6 D5 D4 D3 D2 D1 D0

C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0

01100000

7.2.15 Channel 4 volume (0x0E)

D7 D6 D5 D4 D3 D2 D1 D0

C4V7 C4V6 C4V5 C4V4 C4V3 C4V2 C4V1 C4V0

01100000

32/63

STA308A Registers

7.2.16 Channel 5 volume (0x0F)

D7 D6 D5 D4 D3 D2 D1 D0

C5V7 C5V6 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0

01100000

7.2.17 Channel 6 volume (0x10)

D7 D6 D5 D4 D3 D2 D1 D0

C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0

01100000

7.2.18 Channel 7 volume (0x11)

D7 D6 D5 D4 D3 D2 D1 D0

C7V7 C7V6 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0

01100000

7.2.19 Channel 8 volume (0x12)

D7 D6 D5 D4 D3 D2 D1 D0

C8V7 C8V6 C8V5 C8V4 C8V3 C8V2 C8V1 C8V0

01100000

7.2.20 Channel 1 volume trim, mute, bypass (0x13)

D7 D6 D5 D4 D3 D2 D1 D0

C1M C1VBP C1VT4 C1VT3 C1VT2 C1VT1 C1VT0

00010000

7.2.21 Channel 2 volume trim, mute, bypass (0x14)

D7 D6 D5 D4 D3 D2 D1 D0

C2M C2VBP C2VT4 C2VT3 C2VT2 C2VT1 C2VT0

00010000

7.2.22 Channel 3 volume trim, mute, bypass (0x15)

D7 D6 D5 D4 D3 D2 D1 D0

C3M C3VBP C3VT4 C3VT3 C3VT2 C3VT1 C3VT0

00010000

33/63

Registers STA308A

7.2.23 Channel 4 volume trim, mute, bypass (0x16)

D7 D6 D5 D4 D3 D2 D1 D0

C4M C4VBP C4VT4 C4VT3 C4VT2 C4VT1 C4VT0

00010000

7.2.24 Channel 5 volume trim, mute, bypass (0x17)

D7 D6 D5 D4 D3 D2 D1 D0

C5M C5VBP C5VT4 C5VT3 C5VT2 C5VT1 C5VT0

00010000

7.2.25 Channel 6 volume trim, mute, bypass (0x18)

D7 D6 D5 D4 D3 D2 D1 D0

C6M C6VBP C6VT4 C6VT3 C6VT2 C6VT1 C6VT0

00010000

7.2.26 Channel 7 volume trim, mute, bypass (0x19)

D7 D6 D5 D4 D3 D2 D1 D0

C7M C7VBP C7VT4 C7VT3 C7VT2 C7VT1 C7VT0

00010000

7.2.27 Channel 8 volume trim, mute, bypass (0x1A)

D7 D6 D5 D4 D3 D2 D1 D0

C8M C8VBP C8VT4 C8VT3 C8VT2 C8VT1 C8VT0

00010000

The volume structure of the STA308A consists of individual volume registers for each
channel and a master volume register that provides an offset to each channels volume
setting. There is also an additional offset for each channel called the channel volume trim.
The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -78 dB. As an
example if C5V = 0xXX or +XXX dB and MV = 0xXX or -XX dB, then the total gain for
channel 5 = XX dB. The channel volume trim is adjustable independently on each channel
from -10 dB to +10 dB in 1 dB steps. The master mute when set to 1 will mute all channels
at once, whereas the individual channel mutes (CnM) will mute only that channel. Both the
master mute and the channel mutes provide a "soft mute" with the volume ramping down to
mute in 8192 samples from the maximum volume setting at the internal processing rate
(~192 kHz). A "hard mute" can be obtained by commanding a value of 0xFF (255) to any
channel volume register or the master volume register. When volume offsets are provided
via the master volume register any channel that whose total volume is less than -91 dB will
be muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration
register H) on a per channel basis as this creates the smoothest possible volume transitions.

34/63

STA308A Registers

When ZCE = 0, volume updates occur immediately. Each channel also contains an
individual channel volume bypass. If a particular channel has volume bypassed via the
CnVBP = 1 register then only the channel volume setting for that particular channel affects
the volume setting, the master volume setting will not affect that channel. Each channel also
contains a channel mute. If CnM = 1 a soft mute is performed on that channel.

MV[7:0] Volume offset from channel value

0x00 0 dB

0x01 -0.5 dB

0x02 -1 dB

……

0x4C -38 dB

……

0xFE -127 dB

0xFF Hardware channel mute

CnV[7:0] Volume

0x00 +48 dB

0x01 +47.5 dB

0x02 +47 dB

……

0x5F +0.5 dB

0x60 0 dB

0x61 -0.5 dB

……

0xFE -79.5 dB

0xFF Hardware channel mute

CnVT[4:0] Volume

0x00 to 0x06 +10 dB

0x07 +9 dB

……

0x0F +1 dB

0x10 0 dB

0x11 -1 dB

……

0x19 -9 dB

0x1A to 0x1F -10 dB

35/63

Registers STA308A

7.2.28 Channel input mapping channels 1 and 2 (0x1B)

D7 D6 D5 D4 D3 D2 D1 D0

C2IM2 C2IM1 C2IM0 C1IM2 C1IM1 C1IM0

001 000

7.2.29 Channel input mapping channels 3 and 4 (0x1C)

D7 D6 D5 D4 D3 D2 D1 D0

C4IM2 C4IM1 C4IM0 C3IM2 C3IM1 C3IM0

011 010

7.2.30 Channel input mapping channels 5 and 6 (0x1D)

D7 D6 D5 D4 D3 D2 D1 D0

C6IM2 C6IM1 C6IM0 C5IM2 C5IM1 C5IM0

101 100

7.2.31 Channel input mapping channels 7 and 8 (0x1E)

D7 D6 D5 D4 D3 D2 D1 D0

C8IM2 C8M1 C8IM0 C7IM2 C7IM1 C7IM0

111 110

Each channel received via I2S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing, simplifies output
stage designs, and enables the ability to perform crossovers. The default settings of these
registers map each I

000 Channel 1

001 Channel 2

010 Channel 3

011 Channel 4

100 Channel 5

101 Channel 6

110 Channel 7

111 Channel 8

2

S input channel to its corresponding processing channel.

CnIM[2:0] Serial input from

36/63

STA308A Registers

7.2.32 AUTO1 - AutoModes EQ, volume, GC (0x1F)

D7 D6 D5 D4 D3 D2 D1 D0

AMDM AMGC2 AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0

00000000

Bit RW RST Name Description

Biquad 2-6 mode is:
00: user programmable

1:0 RW 0 AMEQ[1:0]

By setting AMEQ to any setting other than 00 enables AutoMode EQ, biquads 1-5 are not
user programmable. Any coefficient settings for these biquads will be ignored. Also when
AutoMode EQ is used the pre-scale value for channels 1-6 becomes hard-set to -18 dB.

Bit RW RST Name Description

3:2 RW 0 AMV[1:0]

6:4 RW 0 AMGC[2:0]

Bit RW RST Name Description

01: preset EQ - PEQ bits
10: graphic EQ - xGEQ bits
11: auto volume controlled loudness curve

AutoMode volume mode (MVOL) is:
00: MVOL 0.5 dB 256 steps (standard)

01: MVOL auto curve 30 steps
10: MVOL auto curve 40 steps
11: MVOL auto curve 50 steps

AutoMode gain compression/limiters mode is:
000: user programmable GC

001: AC no clipping
010: AC limited clipping (10%)
011: DRC nighttime listening mode
100: DRC TV commercial/channel AGC
101: AC 5.1 no clipping
110: AC 5.1 limited clipping (10%)

AutoMode 5.1 downmix:

7RW 0 AMDM

0: normal operation
1: channels 7-8 are 2-channel downmix of channels
1-6

AutoMode downmix setting uses channels 7-8 of Mix#1 engine and therefore these
channels of this function are fixed and not allowed to be user set when in this mode.

Channels 1-6 must be arranged via channel mapping (registers CnIM) if necessary in the
following manner for this operation:

Channel 1: left
Channel 2: right
Channel 3: left surround
Channel 4: right surround
Channel 5: center
Channel 6: LFE.

37/63

Registers STA308A

7.2.33 AUTO2 - AutoModes bass management2 (0x20)

D7 D6 D5 D4 D3 D2 D1 D0

SUB RSS1 RSS0 CSS1 CSS0 FSS AMBMXE AMBMME

10000000

Bit RW RST Name Description

0 RW 0 AMBMME

0: AutoMode bass management mix disabled
1: AutoMode bass management mix enabled

Bit RW RST Name Description

1 RW 0 AMBMXE

0: AutoMode bass management crossover disabled
1: AutoMode bass management crossover enabled

Setting the AMBMME bit enables the proper mixing to take place for various preset bass
management configurations. Setting the AMBMXE bit enables the proper crossover filtering
in biquad #7 to take place. The crossover for bass management is always 2

nd

order

(24 dB/oct) and the crossover frequency is determined by register bits PREEQ.XO[2:0].

All configurations of Dolby Bass Management can be performed in the IC. These different
configurations are selected as they would be by the end-user.

The AutoMode bass management settings utilize channels 1-6 on the Mix #1 engine,
Channels 1-6 biquad #6, and channels 1-2 on the mix #2 engine in configuration #2. These
functions cannot be user programmed while the bass management automode is active.

Not all settings are valid as some configurations are unlikely and do not have to be
supported by Dolby specification.

Automatic crossover settings are provided or custom crossovers can be implemented using
the available programmable biquads.

Input channels must be mapped using channel-mapping feature in the following manner for
bass management to be performed properly.

1: left front

2: right front

3: left rear

4: right rear

5: center

6: LFE

Bitfield 10 01 00

CSS - center speaker size Off Large Small

RSS - rear speaker size Off Large Small

38/63

STA308A Registers

Bitfield 1 0

FSS - front speaker size Large Small

SUB - subwoofer On Off

When AMBMXE = 1, biquad #7 on channels 1-6 are utilized for bass-management
crossover filter, this biquad is not user programmable in this mode. The XO settings
determine the crossover frequency used, the crossover is 2

nd

order for both high-pass and
low-pass with a -3 dB cross point. Higher order filters can be obtained be programming
coefficients in other biquads if desired.

It is recommended to use settings of 120-160 Hz when using small, single driver satellite
speakers as the frequency response of these speakers normally are limited to this region.

7.2.34 AUTO3 - AutoMode AM/pre-Scale/bass management scale (0x21)

D7 D6 D5 D4 D3 D2 D1 D0

AMAM2 AMAM1 AMAM0 AMAME MSA AMPS

0000 00

Bit RW RST Name Description

AutoMode pre-scale

0RW0 AMPS

0: -18 dB used for pre-scale when AMEQ = 00
1: user defined pre-scale when AMEQ = 00

Bit RW RST Name Description

Bass management mix scale adjustment

1RW0 MSA

0: -12 dB scaling on satellite channels in Config #1
1: no scaling on satellite channels in Config #1

Bit RW RST Name Description

AutoMode AM enable

4RW0 AMAME

0: switching frequency determined by PWMS settings
1: switching frequency determined by AMAM settings

AMAM[2:0] 48 kHz/96 kHz input Fs 44.1 / 88.2 kHz input Fs

000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz

001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz

010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz

011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz

100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz

101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz

110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz

39/63

Registers STA308A

7.2.35 PREEQ - Preset EQ settings (0x22)

D7 D6 D5 D4 D3 D2 D1 D0

XO2 XO1 XO0 PEQ4 PEQ3 PEQ2 PEQ1 PEQ0

10100000

XO[2:0]

000 70 Hz

001 80 Hz

010 90 Hz

011 100 Hz

100 110 Hz

101 120 Hz

110 140 Hz

111 160 Hz

PEQ[4:0] Mode / setting

Bass management

crossover frequency

00000 Flat

00001 Rock

00010 Soft Rock

00011 Jazz

00100 Classical

00101 Dance

00110 Pop

00111 Soft

01000 Hard

01001 Party

01010 Vocal

01011 Hip-Hop

01100 Dialog

01101 Bass-boost #1

01110 Bass-boost #2

01111 Bass-boost #3

10000 Loudness 1

10001 Loudness 2

10010 Loudness 3

10011 Loudness 4

40/63

STA308A Registers

10100 Loudness 5

10101 Loudness 6

10110 Loudness 7

10111 Loudness 8

11000 Loudness 9

11001 Loudness 10

11010 Loudness 11

11011 Loudness 12

11100 Loudness 13

11101 Loudness 14

11110 Loudness 15

11111 Loudness 16

7.2.36 AGEQ - graphic EQ 80-Hz band (0x23)

D7 D6 D5 D4 D3 D2 D1 D0

AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0

01111

7.2.37 BGEQ - graphic EQ 300-Hz band (0x24)

D7 D6 D5 D4 D3 D2 D1 D0

BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0

01111

7.2.38 CGEQ - graphic EQ 1-kHz band (0x25)

D7 D6 D5 D4 D3 D2 D1 D0

CGEQ4 CGEQ3 CGEQ2 CGEQ1 CGEQ0

01111

7.2.39 DGEQ - graphic EQ 3-kHz band (0x26)

D7 D6 D5 D4 D3 D2 D1 D0

DGEQ4 DGEQ3 DGEQ2 DGEQ1 DGEQ0

01111

41/63

Registers STA308A

7.2.40 EGEQ - graphic EQ 8-kHz band (0x27)

D7 D6 D5 D4 D3 D2 D1 D0

EGEQ4 EGEQ3 EGEQ2 EGEQ1 EGEQ0

01111

xGEQ[4:0] Boost / cut

11111 +16

11110 +15

11101 +14

……

10000 +1

01111 0

01110 -1

……

00001 -14

00000 -15

7.2.41 Biquad internal channel loop-through (0x28)

D7 D6 D5 D4 D3 D2 D1 D0

C8BLP C7BLP C6BLP C5BLP C4BLP C3BLP C2BLP C1BLP

00000000

Each internal processing channel can receive two possible inputs at the input to the biquad
block. The input can come either from the output of that channel’s MIX#1 engine or from the
output of the bass/treble (Biquad#10) of the previous channel. In this scenario, channel 1
receives channel 8. This enables the use of more than 10 biquads on any given channel at
the loss of the number of separate internal processing channels.

Bit RW RST Name Description

For n = 1 to 8:
0: input from channel n MIX#1 engine output - normal

7:0 RW 0 CnBLP

operation
1: input from channel (n - 1) biquad #10 output - loop
operation.

42/63

STA308A Registers

7.2.42 Mix internal channel loop-through (0x29)

D7 D6 D5 D4 D3 D2 D1 D0

C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP

00000000

Each internal processing channel can receive two possible sets of inputs at the inputs to the
Mix#1 block. The inputs can come from the outputs of the interpolation block as normally
occurs (CnMXLP = 0) or they can come from the outputs of the Mix#2 block. This enables
the use of additional filtering after the second mix block at the expense of losing this
processing capability on the channel.

Bit RW RST Name Description

For n = 1 to 8:
0: inputs to channel n MIX#1 engine from interpolation

7:0 RW 0 CnMXLP

outputs - normal operation
1: inputs to channel n MIX#1 engine from MIX#2 engine
outputs - loop operation.

7.2.43 EQ bypass (0x2A)

D7 D6 D5 D4 D3 D2 D1 D0

C8EQBP C7EQBP C6EQBP C5EQBP C4EQCBP C3EQBP C2EQBP C1EQBP

00000000

EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given
channel the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management
cross-over, bass, treble in any combination) are bypassed for that channel.

Bit RW RST Name Description

7:0 RW 0 CnEQBP

7.2.44 Tone control bypass (0x2B)

D7 D6 D5 D4 D3 D2 D1 D0

C8TCB C7TCB C6TCB C5TCB C4TCB C3TCB C2TCB C1TCB

00000000

Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is
bypassed on a given channel the two filters that tone control utilizes are made available as
user programmable biquads #9 and #10.

For n = 1 to 8:
0: perform EQ on channel n - normal operation

1: bypass EQ on channel n.

43/63

Registers STA308A

7.2.45 Tone control (0x2C)

D7 D6 D5 D4 D3 D2 D1 D0

TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

01110111

This is the tone control boost / cut as a function of BTC and TTC bits.

BTC[3:0] / TTC[3:0) Boost / cut

0000 -12 dB

0001 -12 dB

……

0111 -4 dB

0110 -2 dB

0111 0 dB

1000 +2 dB

1001 +4 dB

……

1101 +12 dB

1110 +12 dB

1111 +12dB

7.2.46 Channel limiter select channels 1,2,3,4 (0x2D)

D7 D6 D5 D4 D3 D2 D1 D0

C4LS1 C4LS0 C3LS1 C3LS0 C2LS1 C2LS0 C1LS1 C1LS0

00000000

7.2.47 Channel limiter select channels 5,6,7,8 (0x2E)

D7 D6 D5 D4 D3 D2 D1 D0

C8LS1 C8LS0 C7LS1 C7LS0 C6LS1 C6LS0 C5LS1 C5LS0

00000000

7.2.48 Limiter 1 attack/release rate (0x2F)

D7 D6 D5 D4 D3 D2 D1 D0

L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

01101010

44/63

STA308A Registers

7.2.49 Limiter 1 attack/release threshold (0x30)

D7 D6 D5 D4 D3 D2 D1 D0

L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

01101001

7.2.50 Limiter 2 attack/release rate (0x31)

D7 D6 D5 D4 D3 D2 D1 D0

L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

01101010

7.2.51 Limiter 2 attack/release threshold (0x32)

D7 D6 D5 D4 D3 D2 D1 D0

L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

01101001

7.2.52 Bit description

The STA308A includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anti-clipping mode or to actively reduce the dynamic range for a better listening
environment such as a night-time listening mode which is often needed for DVDs. The two
modes are selected via the DRC bit in Configuration Register B, bit 7 address 0x02. Each
channel can be mapped to either limiter or not mapped, meaning that channel will clip when
0 dBFS is exceeded. Each limiter will look at the present value of each channel that is
mapped to it, select the maximum absolute value of all these channels, perform the limiting
algorithm on that value, and then if needed adjust the gain of the mapped channels in
unison.

The limiter attack thresholds are determined by the LnAT registers. It is recommended in
anti-clipping mode to set this to 0 dBFS, which corresponds to the maximum unclipped
output power of a DDX amplifier. Since gain can be added digitally within the STA308A it is
possible to exceed 0 dBFS or any other LnAT setting, when this occurs, the limiter, when
active, will automatically start reducing the gain. The rate at which the gain is reduced when
the attack threshold is exceeded is dependent upon the attack rate register setting for that
limiter. The gain reduction occurs on a peak-detect algorithm.

The release of limiter, when the gain is again increased, is dependent on a RMS-detect
algorithm. The output of the volume/limiter block is passed through a RMS filter. The output
of this filter is compared to the release threshold, determined by the Release Threshold
register. When the RMS filter output falls below the release threshold, the gain is again
increased at a rate dependent upon the Release Rate register. The gain can never be
increased past it's set value and therefore the release will only occur if the limiter has
already reduced the gain. The release threshold value can be used to set what is effectively
a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to
virtually zero and cause program material to sound lifeless.

45/63

Registers STA308A

In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the
attack threshold is set relative to the maximum volume setting of the channels mapped to
that limiter and the release threshold is set relative to the maximum volume setting plus the
attack threshold.

Figure 7. Basic limiter and volume flow diagram

RMSLimiter

Gain/Volume

Input Output

Gain Attenuation Saturation

CnLS[1,0] Channel limiter mapping

00 Channel has limiting disabled

01 Channel is mapped to limiter #1

10 Channel is mapped to limiter #2

LnA[3:0] Attack rate (dB/ms)

0000 3.1584 (fast)

0001 2.7072

0010 2.2560

0011 1.8048

0100 1.3536

0101 0.9024

0110 0.4512

0111 0.2256

1000 0.1504

1001 0.1123

1010 0.0902

1011 0.0752

1100 0.0645

1101 0.0564

1110 0.0501

1111 0.0451 (slow)

46/63

STA308A Registers

LnR[3:0] Release rate (dB/ms)

0000 0.5116 (fast)

0001 0.1370

0010 0.0744

0011 0.0499

0100 0.0360

0101 0.0299

0110 0.0264

0111 0.0208

1000 0.0198

1001 0.0172

1010 0.0147

1011 0.0137

1100 0.0134

1101 0.0117

1110 0.0110

1111 0.0104 (slow)

LnAT[3:0]

0000 -12

0001 -10

0010 -8

0011 -6

0100 -4

0101 -2

0110 0

0111 +2

1000 +3

1001 +4

1010 +5

1011 +6

1100 +7

1101 +8

Anti-clipping (AC)

(dB relative to FS)

1110 +9

1111 +10

47/63

Registers STA308A

LnRT[3:0]

0000 -∞

0001 -29 dB

0010 -20 dB

0011 -16 dB

0100 -14 dB

0101 -12 dB

0110 -10 dB

0111 -8 dB

1000 -7 dB

1001 -6 dB

1010 -5 dB

1011 -4 dB

1100 -3 dB

1101 -2 dB

Anti-clipping (AC)

(dB relative to FS)

1110 -1 dB

1111 -0 dB

LnAT[3:0]

0000 -31

0001 -29

0010 -27

0011 -25

0100 -23

0101 -21

0110 -19

0111 -17

1000 -16

1001 -15

1010 -14

1011 -13

1100 -12

Dynamic range compression (DRC)

(dB relative to volume)

1101 -10

1110 -7

1111 -4

48/63

STA308A Registers

LnRT[3:0]

0000 -∞

0001 -38 dB

0010 -36 dB

0011 -33 dB

0100 -31 dB

0101 -30 dB

0110 -28 dB

0111 -26 dB

1000 -24 dB

1001 -22 dB

1010 -20 dB

1011 -18 dB

1100 -15 dB

1101 -12 dB

Dynamic range compression (DRC)

(db relative to volume + LnAT)

1110 -9 dB

1111 -6 dB

7.2.53 Channel 1 and 2 output timing (0x33)

D7 D6 D5 D4 D3 D2 D1 D0

C2OT2 C2OT1 C2OT0 C1OT2 C1OT1 C1OT0

100 000

7.2.54 Channel 3 and 4 output timing (0x34)

D7 D6 D5 D4 D3 D2 D1 D0

C4OT2 C4OT1 C4OT0 C3OT2 C3OT1 C3OT0

110 010

7.2.55 Channel 5 and 6 output timing (0x35)

D7 D6 D5 D4 D3 D2 D1 D0

C6OT2 C6OT1 C6OT0 C5OT2 C5OT1 C5OT0

101 001

49/63

Registers STA308A

7.2.56 Channel 7 and 8 output timing (0x36)

D7 D6 D5 D4 D3 D2 D1 D0

C8OT2 C8OT1 C8OT0 C7OT2 C7OT1 C7OT0

111 011

The centering of the individual channel PWM output periods can be adjusted by the output
timing registers. PWM slot settings can be chosen to insure that pulse transitions do not
occur at the same time on different channels using the same power device. There are 8
possible settings, the appropriate setting varying based on the application and connections
to the DDX power devices.

CnOT[2:0] PWM slot

000 1

001 2

010 3

011 4

100 5

101 6

110 7

111 8

7.2.57 Channel I2S output mapping channels 1 and 2 (0x37)

D7 D6 D5 D4 D3 D2 D1 D0

C2OM2 C2OM1 C2OM0 C1OM2 C1OM1 C1OM0

001 000

7.2.58 Channel I2S output mapping channels 3 and 4 (0x38)

D7 D6 D5 D4 D3 D2 D1 D0

C4OM2 C4OM1 C4OM0 C3OM2 C3OM1 C3OM0

011 010

7.2.59 Channel I2S output mapping channels 5 and 6 (0x39)

D7 D6 D5 D4 D3 D2 D1 D0

C6OM2 C6OM1 C6OM0 C5OM2 C5OM1 C5OM0

101 100

50/63

STA308A Registers

7.2.60 Channel I2S output mapping channels 7 and 8 (0x3A)

D7 D6 D5 D4 D3 D2 D1 D0

C8OM2 C8M1 C8OM0 C7OM2 C7OM1 C7OM0

111 110

Each I2S output channel can receive data from any channel output of the volume block.
Which channel a particular I

2

S output receives is dependent upon that channels CnOM

register bits.

CnOM[2:0] Serial output from

000 Channel 1

001 Channel 2

010 Channel 3

011 Channel 4

100 Channel 5

101 Channel 6

110 Channel 7

111 Channel 8

7.2.61 Coefficient address register 1 (0x3B)

D7 D6 D5 D4 D3 D2 D1 D0

CFA9 CFA8

00

7.2.62 Coefficient address register 2 (0x3C)

D7 D6 D5 D4 D3 D2 D1 D0

CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

00000000

7.2.63 Coefficient b1 data register, bits 23:16 (0x3D)

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

51/63

Registers STA308A

7.2.64 Coefficient b1 data register, bits 15:8 (0x3E)

D7 D6 D5 D4 D3 D2 D1 D0

C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

00000000

7.2.65 Coefficient b1 data register, bits 7:0 (0x3F)

D7 D6 D5 D4 D3 D2 D1 D0

C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

00000000

7.2.66 Coefficient b2 data register, bits 23:16 (0x40)

D7 D6 D5 D4 D3 D2 D1 D0

C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

00000000

7.2.67 Coefficient b2 data register, bits 15:8 (0x41)

D7 D6 D5 D4 D3 D2 D1 D0

C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

00000000

7.2.68 Coefficient b2 data register, bits 7:0 (0x42)

D7 D6 D5 D4 D3 D2 D1 D0

C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

00000000

7.2.69 Coefficient a1 data register, bits 23:16 (0x43)

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

7.2.70 Coefficient a1 data register, bits 15:8 (0x44)

D7 D6 D5 D4 D3 D2 D1 D0

C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

00000000

52/63

STA308A Registers

7.2.71 Coefficient a1 data register, bits 7:0 (0x45)

D7 D6 D5 D4 D3 D2 D1 D0

C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0
00000000

7.2.72 Coefficient a2 data register, bits 23:16 (0x46)

D7 D6 D5 D4 D3 D2 D1 D0

C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

00000000

7.2.73 Coefficient a2 data register, bits 15:8 (0x47)

D7 D6 D5 D4 D3 D2 D1 D0

C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8
00000000

7.2.74 Coefficient a2 data register, bits 7:0 (0x48)

D7 D6 D5 D4 D3 D2 D1 D0

C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0
00000000

7.2.75 Coefficient b0 data register, bits 23:16 (0x49)

D7 D6 D5 D4 D3 D2 D1 D0

C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

00000000

7.2.76 Coefficient b0 data register, bits 15:8 (0x4A)

D7 D6 D5 D4 D3 D2 D1 D0

C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

00000000

7.2.77 Coefficient b0 data register, bits 7:0 (0x4B)

D7 D6 D5 D4 D3 D2 D1 D0

C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

00000000

53/63

Registers STA308A

7.2.78 Coefficient write control register (0x4C)

D7 D6 D5 D4 D3 D2 D1 D0

WA W1

00

Coefficients for EQ and Bass Management are handled internally in the STA308A via RAM.
Access to this RAM is available to the user via an I

A collection of I

2

C registers are dedicated to this function. One contains a coefficient base

2

C register interface.

address, five sets of three store the values of the 24-bit coefficients to be written or that were
read, and one contains bits used to control the write of the coefficient(s) to RAM. The
following are instructions for reading and writing coefficients.

7.3 Reading a coefficient from RAM

1. write top 2-bits of address to I2C register 0x3B

2. write bottom 8-bits of address to I

3. read top 8-bits of coefficient in I

4. read middle 8-bits of coefficient in I

5. read bottom 8-bits of coefficient in I

2

C register 0x3C

2

C address 0x3D

2

C address 0x3E

2

C address 0x3F

7.4 Reading a set of coefficients from RAM

1. write top 2-bits of address to I2C register 0x3B

2. write bottom 8-bits of address to I

3. read top 8-bits of coefficient in I

4. read middle 8-bits of coefficient in I

5. read bottom 8-bits of coefficient in I

6. read top 8-bits of coefficient b2 in I

7. read middle 8-bits of coefficient b2 in I

8. read bottom 8-bits of coefficient b2 in I

9. read top 8-bits of coefficient a1 in I

10. read middle 8-bits of coefficient a1 in I

11. read bottom 8-bits of coefficient a1 in I

12. read top 8-bits of coefficient a2 in I

13. read middle 8-bits of coefficient a2 in I

14. read bottom 8-bits of coefficient a2 in I

15. read top 8-bits of coefficient b0 in I

16. read middle 8-bits of coefficient b0 in I

17. read bottom 8-bits of coefficient b0 in I

2

C register 0x3C

2

C address 0x3D

2

C address 0x3E

2

C address 0x3F

2

C address 0x40

2

C address 0x41

2

C address 0x42

2

C address 0x43

2

C address 0x44

2

C address 0x45

2

C address 0x46

2

C address 0x47

2

C address 0x48

2

C address 0x49

2

C address 0x4A

2

C address 0x4B

54/63

STA308A Registers

7.5 Writing a single coefficient to RAM

1. write top 2-bits of address to I2C register 0x3B

2. write bottom 8-bits of address to I

3. write top 8-bits of coefficient in I

4. write middle 8-bits of coefficient in I

5. write bottom 8-bits of coefficient in I

6. write 1 to W1 bit in I

2

C address 0x4C

2

C register 0x3C

2

C address 0x3D

2

C address 0x3E

2

C address 0x3F

7.6 Writing a set of coefficients to RAM

1. write top 2-bits of starting address to I2C register 0x3B

2. write bottom 8-bits of starting address to I

3. write top 8-bits of coefficient b1 in I

2

4. write middle 8-bits of coefficient b1 in I

5. write bottom 8-bits of coefficient b1 in I

6. write top 8-bits of coefficient b2 in I

2

7. write middle 8-bits of coefficient b2 in I

8. write bottom 8-bits of coefficient b2 in I

9. write top 8-bits of coefficient a1 in I

2

10. write middle 8-bits of coefficient a1 in I

11. write bottom 8-bits of coefficient a1 in I

12. write top 8-bits of coefficient a2 in I

2

13. write middle 8-bits of coefficient a2 in I

14. write bottom 8-bits of coefficient a2 in I

15. write top 8-bits of coefficient b0 in I

2

16. write middle 8-bits of coefficient b0 in I

17. write bottom 8-bits of coefficient b0 in I

18. write 1 to WA bit in I

2

C address 0x4C

2

C register 0x3C

C address 0x3D

2

C address 0x3E

2

C address 0x3F

C address 0x40

2

C address 0x41

2

C address 0x42

C address 0x43

2

C address 0x44

2

C address 0x45

C address 0x46

2

C address 0x47

2

C address 0x48

C address 0x49

2

C address 0x4A

2

C address 0x4B

The mechanism for writing a set of coefficients to RAM provides a method of updating the
five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible
unpleasant acoustic side-effects.

When using this technique, the 10-bit address would specify the address of the biquad b1
coefficient (for example, decimals 0, 5, 10, 15, …, 100, … 395), and the STA308A will
generate the RAM addresses as offsets from this base value to write the complete set of
coefficient data.

55/63

Equalization and mixing STA308A

8 Equalization and mixing

Figure 8. Channel mixer

CxMIX1

Channel 1

CxMIX2

Channel 2

CxMIX3

Channel 3

8.1 Post-scale

The STA308A provides one additional multiplication after the last interpolation stage and
before the distortion compensation on each channel. This is a 24-bit signed fractional
multiply.

The scale factor for this multiply is loaded into RAM using the same I
biquad coefficients and the bass-management.

This post-scale factor can be used in conjunction with an ADC equipped micro-controller to
perform power-supply error correction. All channels can use the channel 1 by setting the
post-scale link bit.

Table 9. RAM block for biquads, mixing, and bass management

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

CxMIX4

CxMIX5

CxMIX6

CxMIX7

CxMIX8

Channel x

2

C registers as the

Index

(decimal)

Index

(hex)

0 0x00 Channel 1 - Biquad 1 C1H10 (b1/2) 0x000000

1 0x01 C1H11 (b2) 0x000000

2 0x02 C1H12 (a1/2) 0x000000

3 0x03 C1H13 (a2) 0x000000

56/63

Coefficient Default

STA308A Equalization and mixing

Table 9. RAM block for biquads, mixing, and bass management (continued)

Index

(decimal)

4 0x04 C1H14 (b0/2) 0x400000

5 0x05 Channel 1 - Biquad 2 C1H20 0x000000

……… … …

49 0x31 Channel 1 - Biquad 10 C1HA4 0x400000

50 0x32 Channel 2 - Biquad 1 C2H10 0x000000

51 0x33 C2H11 0x000000

……… … …

99 0x63 Channel 2 - Biquad 10 C2HA4 0x4000000

100 0x64 Channel 3 - Biquad 1 C3H10 0x000000

……… … …

399 0x18F Channel 8 - Biquad 10 C8HA4 0x400000

400 0x190 Channel 1 - Pre-Scale C1PreS 0x7FFFFF

401 0x191 Channel 2 - Pre-Scale C2PreS 0x7FFFFF

402 0x192 Channel 3 - Pre-Scale C3PreS 0x7FFFFF

……… … …

407 0x197 Channel 8 - Pre-Scale C8PreS 0x7FFFFF

408 0x198 Channel 1 - Post-Scale C1PstS 0x7FFFFF

Index

(hex)

Coefficient Default

409 0x199 Channel 2 - Post-Scale C2PstS 0x7FFFFF

……… … …

415 0x19F Channel 8 - Post-Scale C8PstS 0x7FFFFF

416 0x1A0 Channel 1 - Mix#1 1 C1MX11 0x7FFFFF

417 0x1A1 Channel 1 - Mix#1 2 C1MX12 0x000000

……… … …

423 0x1A7 Channel 1 - Mix#1 8 C1MX18 0x000000

424 0x1A8 Channel 2 - Mix#1 1 C2MX11 0x000000

425 0x1A9 Channel 2 - Mix#1 2 C2MX12 0x7FFFFF

……… … …

463 0x1CF Channel 8 - Mix#1 8 C8MX18 0x7FFFFF

464 0x1D0 Channel 1 - Mix#2 1 C1MX21 0x7FFFFF

465 0x1D1 Channel 1 - Mix#2 2 C1MX22 0x000000

……… … …

471 0x1D7 Channel 1 - Mix#2 8 C1MX28 0x000000

472 0x1D8 Channel 2 - Mix#2 1 C2MX21 0x000000

473 0x1D9 Channel 2 - Mix#2 2 C2MX22 0x7FFFFF

57/63

Equalization and mixing STA308A

Table 9. RAM block for biquads, mixing, and bass management (continued)

Index

(decimal)

Index

(hex)

……… … …

527 0x20F Channel 8 - Mix#2 8 C8MX28 0x7FFFFF

8.2 Variable max power correction

8.2.1 MPCC1-2 (0x4D, 0x4E)

MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is
used in place of the default coefficient when MPCV = 1.

D7 D6 D5 D4 D3 D2 D1 D0

MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

00101101

D7 D6 D5 D4 D3 D2 D1 D0

Coefficient Default

MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

11000000

8.3 Variable distortion compensation

8.3.1 DCC1-2 (0x4F, 0x50)

DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient
is used in place of the default coefficient when DCCV = 1.

D7 D6 D5 D4 D3 D2 D1 D0

DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8

11110011

D7 D6 D5 D4 D3 D2 D1 D0

DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0

00110011

58/63

STA308A Equalization and mixing

8.4 PSCorrect registers

ADC is used to input ripple data to SDI78. The left channel (7) is used internally. No audio
data can therefore be used on these channels. Though all channel mapping and mixing
from other inputs to channels 7 and 8 internally are still valid.

8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52)

Equivalent to negative maximum ripple peak as a percentage of Vcc (MPR), scaled by the
inverse of maximum ripple p-p as percentage of full-scale analog input to ADC.
Represented as a 1.11 signed fractional number.

D7 D6 D5 D4 D3 D2 D1 D0

RCV11 RCV10 RCV9 RCV8 RCV7 RCV6 RCV5 RCV4

00000000

D7 D6 D5 D4 D3 D2 D1 D0

RCV3 RCV2 RCV1 RCV0 CNV11 CNV10 CNV9 CNV8

00001111

8.4.2 PSC3: correction normalization value (CNV) (0x53)

Equivalent to 1 / (1+MPR) expressed as a 0.12 unsigned fractional number.

D7 D6 D5 D4 D3 D2 D1 D0

CNV7 CNV6 CNV5 CNV4 CNV3 CNV2 CNV1 CNV0

11111111

59/63

Package information STA308A

9 Package information

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

Figure 9. TQFP64 (10 x 10 x 1.4mm) mechanical data and package dimensions

DIM.

A 1.60 0.0 63

A1 0 .05 0.15 0.002 0.0 06

A2 1 .35 1.40 1.45 0.053 0 .055 0.057

B 0 .17 0.22 0.27 0.006 6 0.0086 0.0106

C 0.09 0.0035

D 11.80 12.00 12.20 0.464 0.472 0.480

D1 9.80 10. 00 10.20 0.386 0.394 0.401

D3 7.50 0.295

e 0.50 0. 0197

E 11.80 12.00 12.2 0 0.464 0 .472 0.480

E1 9 .80 10.00 10.20 0.386 0.394 0.401

E3 7.50 0 .295

L 0.45 0.60 0.75 0 .0177 0.0236 0.0 295

L1 1.00 0.0393

K 0˚ (m in.), 3.5˚ (min .), 7˚(max.)

ccc 0.080 0.0031

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

OUTLINE AND

MECHANICAL DATA

TQFP64 (10 x 10 x 1.4mm)

D

D1

48

49

B

64

1

e

TQFP64

33

32

E3D3E1

17

16

E

L1

0.08mm

Seating Plane

L

K

A

A2

A1

ccc

B

C

0051434 E

60/63

STA308A Trademarks and other acknowledgements

10 Trademarks and other acknowledgements

DDX is a registered trademark of Apogee Technology Inc.

ECOPACK is a registered trademark of STMicroelectronics.

61/63

Revision history STA308A

11 Revision history

Table 10. Document revision history

Date Revision Changes

May-2004 1 Initial release.

Nov-2005 2 Changed in page 4 value T

June-2006 3 Changed in Figure 4 and Table 2 the name of the pins 22 and 24.

Updated cover page
Added chapter 6, Application reference schematic

July-2007 4

Removed reserved registers from chapter 7
Updated register descriptions in chapter 7
Various minor changes.

amb

and Tj.

62/63

STA308A

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2007 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

63/63