ST STA2500D User Manual

STA2500D

Bluetooth™ V2.1 + EDR ("Lisbon") for automotive applications

Features

■Based on Ericsson technology licensing baseband core (EBC)

■Bluetooth™ specification compliance: V2.1 + EDR (“Lisbon”)

–Point-to-point, point-to-multipoint (up to 7 slaves) and scatternet capability

–Support ACL and SCO links

–Extended SCO (eSCO) links

–Faster connection

■HW support for packet types

–ACL: DM1, DM3, DM5, DH1, DH3, DH5, 2- DH1, 2-DH3, 2-DH5, 3-DH1, 3-DH3, 3-DH5

–SCO: HV1, HV3 and DV

–eSCO: EV3, EV4, EV5, 2-EV3, 2-EV5, 3- EV3, 3-EV5

■Adaptive frequency hopping (AFH)

■Channel quality driven data rate (CQDDR)

■“Lisbon” features

–Encryption pause/resume (EPR)

–Extended inquiry response (EIR)

–Link supervision time out (LSTO)

–Secure simple pairing

–Sniff subrating

–Quality of service (QoS) Packet boundary flag Erroneous data delivery

■Transmit power

–Power class 2 and power class 1.5 (above 4 dBm)

–Programmable output power

–Power class 1 compatible

■HCI

–HCI H4 and enhanced H4 transport layer

–HCI proprietary commands (e.g. peripherals control)

–Single HCI command for patch/upgrade download

–eSCO over HCI supported

■Supports pitch-period error concealment (PPEC)

■Efficient and flexible support for WLAN coexistence scenarios

LFBGA48 (6x6x1.4mm; 0.8mm Pitch)

■Low power consumption

–Ultra low power architecture with 3 different low-power levels

–Deep sleep modes, including host-power saving feature

–Dual wake-up mechanism: initiated by the host or by the Bluetooth device

■Communication interfaces

–Fast UART up to 4 MHz

–Flexible SPI interface up to 13 MHz

–PCM interface

–Up to 10 additional flexibly programmable GPIOs

–External interrupts possible through the GPIOs

–Fast I2C interface as master

■Clock support

–System clock input (digital or sine wave) at 9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6 or 38.4 MHz

–Low power clock input at 3.2 kHz, 32 kHz and 32.768 kHz

■ARM7TDMI CPU

■Memory organization

–On chip RAM, including provision for patches

–On chip ROM, preloaded with SW up to HCI

■Ciphering support up to 128-bit key

■Single power supply with internal regulators for core voltage generation

■Supports 1.65 V to 2.85 V I/O systems

■Auto calibration (VCO, filters)

January 2010

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www.st.com

Contents	STA2500D

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
	2.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.2	Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.3	I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.4	Clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
	2.5	Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10

3	Block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . .		12
4	Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	4.1	Pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.2	HW configuration of the STA2500D . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	4.3	I/O Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17

5	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	5.1	Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	5.2	Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	5.3	PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	5.4	Bluetooth controller V1.2 and V2.0 + EDR features . . . . . . . . . . . . . . . . .	19
	5.5	Bluetooth controller V2.1 + EDR (“Lisbon”) . . . . . . . . . . . . . . . . . . . . . . .	19
	5.6	Processor and memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	5.7	TX output power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

6	General specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	6.1	Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	6.2	Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	6.3	Class 1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	6.4	Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	6.5	System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	6.6	Low power clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	6.7	Clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27

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STA2500D	Contents

6.8 Clock request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.10 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.10.2 Some examples for the usage of the low power modes . . . . . . . . . . . . 30 6.10.3 Deep sleep mode entry and wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.11 Patch RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.12 Download of SW parameter file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.13 Bluetooth - WLAN coexistence in collocated scenario . . . . . . . . . . . . . . . 38

6.13.1 Algorithm 1: PTA (packet traffic arbitration) . . . . . . . . . . . . . . . . . . . . . . 38 6.13.2 Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.13.3 Algorithm 3: Bluetooth master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.13.4 Algorithm 4: two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.13.5 Algorithm 5: Alternating wireless medium access (AWMA) . . . . . . . . . . 40

7	Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
	7.1	The UART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
	7.2	The SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
	7.3	The PCM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
	7.4	The JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
	7.5	Alternate I/O functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
	7.6	The I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47

8	HCI transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		48
	8.1	H4 UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
	8.2	Enhanced H4 SPI transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
	8.3	H4 SPI transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
	8.4	eSCO over HCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
9	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
10	References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		52
11	Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		53
12	Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		56
13	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		57

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List of tables	STA2500D

List of tables

Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. DC input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. DC output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. System clock supported frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. System clock overall specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 7. System clock, sine wave specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 8. System clock, digital clock DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 9. System clock, digital clock AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 10. Low power clock specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 11. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 12. The STA2500D pin list (functional and supply). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 13. Configuration programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 14. I/O supply split diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 15. Mbps receiver parameters - GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. Mbps receiver parameters - π/4-DQPSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. Mbps receiver parameters - 8-DPSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 18. Transmitter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 19. Output power: class 1 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 20. Output power: class 1 device pin configuration (depending on SW parameter download). 26 Table 21. Output power: class 1 device pin configuration (depending on SW parameter download). 26 Table 22. Use of the BT_CLK_REQ_IN and BT_CLK_REQ_OUT signals in different modes. . . . . . 28 Table 23. Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 24. WLAN HW signal assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 25. SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 26. PCM interface parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 27. PCM interface timing (at PCM_CLK = 2048 kHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 28. Examples of BT_GPIO pin programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 29. Package markings legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 30. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 31. Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 32. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 33. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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STA2500D	List of figures

List of figures

Figure 1.	Block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Figure 2.	Pinout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
Figure 3.	Active high clock request input and output combined with UART or SPI . . . . . . . . . . . . . .	28
Figure 4.	Active low clock request input and output combined with UART . . . . . . . . . . . . . . . . . . . .	28
Figure 5.	Active low clock request input and output combined with SPI . . . . . . . . . . . . . . . . . . . . . .	28
Figure 6.	Deep sleep mode entry and wake-up through H4 UART . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 7.	Entering deep sleep mode through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 8.	Wake-up by the host through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 9.	Wake-up by the Bluetooth controller with data transmission to the host, through enhanced H4
SPI	34
Figure 10.	Deep sleep mode entry and wake-up through H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
Figure 11.	Entering deep sleep mode, pending data on UART interface, through UART with handshake
36
Figure 12.	Wakeup by host through UART with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
Figure 13.	PTA diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 14.	WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 15.	Bluetooth master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 16.	SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
Figure 17.	SPI data transfer timing for data length of 8 bits and lsb first, full duplex . . . . . . . . . . . . . .	42
Figure 18.	SPI setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
Figure 19.	PCM (A-law, µ-law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
Figure 20.	Linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
Figure 21.	Multislot operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
Figure 22.	PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
Figure 23.	UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 24.	LFBGA48 (6x6x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . . . .	50
Figure 25.	Package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51

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Description	STA2500D

1 Description

The STA2500D is a single chip Bluetooth solution that is fully optimized for automotive applications such as telematics, navigation and portable navigation. Power consumption levels are targeted at battery powered devices and single chip solution brings cost advantages. Manufacturers can easily and quickly integrate the STA2500D on their product to enable a rapid time to market.

STA2500D supports the Bluetooth specification V2.1 + EDR (“Lisbon“) and is optimized in terms of RF performance and cost.

The STA2500D is a ROM-based solution targeted at applications requiring integration up to HCI level. Patch RAM is available, enabling multiple patches/upgrades and fast time to volume. The STA2500D’s main interfaces are UART or SPI for HCI transport, PCM for voice and GPIOs for control purposes.

The radio has been designed specifically for single chip requirements, for low power consumption and minimum BOM count.

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STA2500D	Quick reference data

2 Quick reference data

BT_VIO_x means BT_VIO_A, BT_VIO_B.

BT_HVx means BT_HVA, BT_HVD.

(See also Table 12.)

2.1Absolute maximum ratings

The absolute maximum rating (AMR) corresponds to the maximum value that can be applied without leading to instantaneous or very short-term unrecoverable hard failure (destructive breakdown).

	Table 1.	Absolute maximum ratings
	Symbol	Parameter	Min.	Max.	Unit
	BT_HVx	Core supply voltages	-0.3	4.0	V
	BT_VIO_A	Supply voltage I/O	-0.3	4.0	V
	BT_VIO_B	Supply voltage I/O (for the low power clock)	-0.3	4.0	V
	BT_Vin	Input voltage of any digital pin	-0.3	4.0	V
	Vssdiff	Maximum voltage difference between different types of	-0.3	0.3	V
		Vss pins.
	Tstg	Storage temperature	- 65	+ 150	°C

2.2Operating ranges

Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied.

Table 2.	Operating ranges
Symbol		Parameter	Min.	Typ.	Max.	Unit
BT_T		Operating ambient temperature	-40	25	+85	°C
amb
BT_HVx		Core supply voltages	2.65	2.75	2.85	V
BT_VIO_A		I/O supply voltage	1.65	-	2.85	V
BT_VIO_B		I/O supply voltage (for the low power clock)	1.17	-	2.85	V

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Quick reference data	STA2500D

2.3I/O specifications

The I/Os comply with the EIA/JEDEC standard JESD8-B.

Table 3.	DC input specification
Symbol	Parameter						Min.		Typ.	Max.	Unit
VIL_BT	Low level input voltage						-0.2		-	0.35 *	V
										BT_VIO_x
							0.65 *			(BT_VIO_x
VIH_BT	High level input voltage								-	+ 0.2) and	V
							BT_VIO_x
										(≤ 2.85)
C	Input capacitance(1)						1		-	2.5	pF
in_BT
Rpu	Pull-up equivalent resistance (with Vin = 0 V)						31		47	73	kΩ
Rpd	Pull-down equiv. resistance (with Vin = BT_VIO_x)						29		50	100	kΩ
	Schmitt trigger hysteresis (at BT_VIO_A = 1.8 V)
Vhyst	except for BT_CONFIG1-3, BT_RESETN,						0.4		0.5	0.6	V
	BT_WAKEUP
	Schmitt trigger hysteresis (at BT_VIO_x = 1.8 V)
Vhyst	for BT_CONFIG1-3, BT_RESETN, BT_WAKEUP,						0.223		-	0.314	V
	BT_LP_CLK
Vhyst	Schmitt trigger hysteresis (at BT_VIO_B = 1.3 V)						0.2		-	0.3	V
1. Except for the system clock.
Table 4.	DC output specification
Symbol	Parameter			Condition			Min.		Typ.	Max.	Unit
V	Low level output voltage	I	d	= X(1)	mA		-		-	0.15	V
OL_BT
V	High level output voltage	I		= X(1)	mA		BT_VIO_x		-	-	V
			d
OH_BT							- 0.25

1. X is the source/sink current under worst-case conditions according to the drive capabilities (see Section 3)

2.4Clock specifications

The STA2500D supports, on the BT_REF_CLK_IN pin, the system clock both as a sine wave clock and as a digital clock. For configuration, see Table 12: pin BT_VDD_CLD (E6).

Table 5.	System clock supported frequencies
Symbol	Parameter	Values	Unit
FIN	Clock input frequency list	9.6, 10, 13, 16, 16.8, 19.2,	MHz
		26, 33.6, 38.4

Table 6.	System clock overall specifications
Symbol	Parameter	Min.	Typ.	Max.	Unit
FINTOL	Tolerance on input frequency	-20	-	20	ppm

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STA2500D				Quick reference data
Table 7.	System clock, sine wave specifications
Symbol	Parameter	Min.	Typ.		Max.	Unit
VPP	Peak to peak voltage range	0.27	0.5		1.8	V
NH	Total harmonic content of input signal	-	-		-25	dBc
ZINRe	Real part of parallel input impedance at pin	30	60		90	kΩ
ZINIm	Imaginary part of parallel input impedance at pin	-	5		8	pF
ZIDRe	Real impedance discrepancy between active and non-	-	-		7	kΩ
	active mode of clock input
ZIDim	Imaginary impedance discrepancy between active and	-	-		500	fF
	non-active mode of clock input
	Phase noise @ 10 kHz(1)	-	-		-126	dBc/Hz

1. Equivalent to max 10 ps time jitter (rms).

	Table 8.	System clock, digital clock DC specifications
	Symbol	Parameter	Min.	Typ.	Max.	Unit
	VIL	Low level input voltage	-0.2	-	0.35 *	V
					BT_VDD_CLD
			0.65 *		(BT_VDD_CLD
	VIH	High level input voltage		-	+ 0.2) and	V
			BT_VDD_CLD
					(≤ 2.85)
	CIN	Input capacitance	-	5	8	pF

Table 9.	System clock, digital clock AC specifications
Symbol		Parameter		Min.	Typ.	Max.	Unit
TRISE	10%	- 90% rise time		-	1.5	6	ns
TFALL	90%	- 10% fall time		-	1.5	6	ns
DCYCLE	Duty cycle			45	50	55	%
-	Phase noise @ 10 kHz(1)			-	-	-121	dBc/Hz

1. Equivalent to max 15 ps time jitter (rms).

Table 10. Low power clock specifications

The low power clock pin is powered by connecting BT_VIO_B to the wanted supply.

Symbol	Parameter	Min.		Typ.		Max.	Unit
FIN	Clock input frequencies		3.2, 32, 32.768				kHz
-	Duty cycle	30		-		70	%
-	Tolerance on input frequency	−250		-		250	ppm
VIL	Low level input voltage	-		-		0.35 *	V
						BT_VIO_B
VIH	High level input voltage	0.65 *		-		-	V
		BT_VIO_B
Vhyst	Schmitt trigger hysteresis (BT_VIO_B = 1.8 V)	0.4		0.5		0.6	V

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Quick reference data						STA2500D
Table 10.	Low power clock specifications (continued)
	The low power clock pin is powered by connecting BT_VIO_B to the wanted supply.
Symbol	Parameter		Min.	Typ.	Max.		Unit
Vhyst	Schmitt trigger hysteresis (BT_VIO_B = 1.3 V)		0.2	0.3	0.4		V
CIN	Input capacitance		1	-	2.5		pF
TRISE	10% - 90% rise time(1)		-	-	1		μs
T	90% - 10% fall time(1)		-	-	1		μs
FALL
-	Total jitter(2)		-	-	250		ppm

1.The rise and fall time are not the most important parameters for the low power clock input due to the Schmitt trigger logic. It is more important that the noise on the Low power clock line remains substantially below the hysteresis in amplitude.

2.The total jitter is defined as the error that can appear on the actual frequency between two clock edges compared to the perfect frequency. Due to this, the total jitter value must contain the jitter itself and the error due to the accuracy on the clock frequency. The lower the accuracy, the smaller the jitter is allowed to be.

2.5Current consumption

Tamb = 25°C, 13 MHz digital clock, 7 dBm output power for BR packets, 3 dBm output power for EDR packets.

Table 11. Current consumption(1)

	State	Typ.	Unit
	Complete Power Down	1	μA
	Deep Sleep mode	20	μA
	Functional Sleep mode(2)	1.2	mA
	Sniff mode (1.28 s, 2 attempts, 0 timeouts), combined with H4 UART Deep Sleep
	mode
	(see section 6.10.3)	55	μA
	Master mode
		83	μA
	Slave mode
	Inquiry scan (1.28 seconds period), combined with H4 UART Deep Sleep mode
	(see section 6.10.3)	318	μA
	HW Page scan (1.28 seconds period), combined with H4 UART Deep Sleep mode
	(see section 6.10.3)	312	μA
	HW Inquiry and Page scan (1.28 seconds period), combined with H4 UART Deep
	Sleep mode	591	μA
	(see section 6.10.3)
	Idle ACL connection (Master)	3.6	mA
	Idle ACL connection (Slave)	8.2	mA
	Active: audio (HV3) Master (not sniffed)	11.7	mA
	Active: audio (HV3) Slave (Sniff 1.28 s, 2 attempts, 0 timeouts)	10.6	mA
	Active: data (DH1) Master or Slave
	(172.8 kbps asymmetrical in TX mode)	23	mA
	(172.8 kbps symmetrical)	28.5

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STA2500D		Quick reference data
	Table 11.	Current consumption(1) (continued)
		State	Typ.	Unit
	Active: data (DH5) Master or Slave
	(723.2 kbps asymmetrical in TX mode)		35.4	mA
	(433.9 kbps symmetrical)		35.4	mA
	Active: data (2-DH5) Master or Slave (869.7 kbps symmetrical)		35.4	mA
	Active: data (3-DH5) Master or Slave (1306.9 kbps symmetrical)		35.4	mA
	Active: audio eSCO (EV3), (64 kbps symmetrical TeSCO = 6)
	Master mode		12	mA
	Slave mode		15	mA
	Active: audio eSCO (2-EV3), (64 kbps symmetrical TeSCO = 12)
	Master mode		7.8	mA
	Slave mode		11.7	mA
	Active: audio eSCO (3-EV3), (64 kbps symmetrical TeSCO = 18)
	Master mode		6.5	mA
	Slave mode		10.5	mA
	Active: audio eSCO (EV5), (64 kbps symmetrical TeSCO = 36), Master mode		8	mA
	Active: audio eSCO (EV5), (64 kbps symmetrical TeSCO = 36), Slave mode		11.9	mA
	Active: audio eSCO (2-EV5), (64 kbps symmetrical TeSCO = 36), Master mode		6.3	mA
	Active: audio eSCO (3-EV5), (64 kbps symmetrical TeSCO = 36), Master mode		5.75	mA

1.The power consumption (except for power safe modes i.e. complete power down and deep sleep mode) will rise (with approx. 200 µA) if an analog system clock is used instead of a digital clock.

2.In functional sleep mode, the baseband clock is still running.

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Block diagram and electrical schematic	STA2500D

3 Block diagram and electrical schematic

Figure 1. Block diagram and electrical schematic

	BT_VDD[4:0]	BT_HV[1:0]		BT_VIO_A	BT_VIO_B
	INTERNAL SUPPLY MANAGEMENT
						BT_GPIO_0
					ARM7TDMI
					CPU Wrapper JTAG	BT_GPIO/JTAG
						[4:0]
	RECEIVER	DEMO-
		DULATOR
					RAM	BT_LP_CLK
						BT_HOST_WAKEUP/
						BT_SPI_INT
BT_RFP					ROM
	RF PLL	CONTROL
		AND				BT_WAKEUP
	Fractional N
Filter		REGISTER
			BASEBAND		UART/
BT_RFN			CORE		SPI	BT_RESETN
			EBC
	TRANSMITTER	MODU-			TIMER	BT_UART/BT_SPI
		LATOR
						[3:0]
				AMBA	INTERRUPT
				PERIPH.		BT_PCM
				BUS		[3:0]
	AUTOCALIBRATION				PCM	BT_CONFIG
						[2:0]
		PLL
					WLAN	BT_CLK_REQ_IN
BT_REF_CLK_IN						[1:0]
					I2C	BT_CLK_REQ_OUT
						[1:0]
	BT_TEST[1:0]	BT_VDD_CLD	BT_AF_PRG	BT_VSS[5:0]

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STA2500D	Pinout

4 Pinout

Figure 2. Pinout (bottom view)

7		6	5	4	3	2	1
	BT_HVA	BT_TEST2	BT_VSSRF	BT_RFN	BT_RFP	BT_VSSRF	BT_VDD_RF
A
	BT_VDD_DSM	BT_VSSANA	BT_TEST1	BT_VSSANA	BT_GPIO_16	BT_GPIO_11	BT_GPIO_9
B
	BT_VDD_N	BT_VSSANA	BT_WAKEUP	BT_CLK_REQ_OUT_1 BT_GPIO_8		BT_PCM_SYNC	BT_GPIO_10
					JTAG_TCK
C
	BT_VDD_CL	BT_REF_CLK_IN	BT_GPIO_0		BT_RESETN	BT_PCM_A	BT_PCM_CLK
			GPIO_0
D
	BT_VDD_CLD BT_CLK_REQ_IN_1		BT_AF_PRG	BT_VSSDIG	BT_VSSDIG	BT_CONFIG_1	BT_PCM_B
E
	BT_HOST_WAKEUP BT_UART_TXD		BT_UART_RXD	BT_UART_RTS	BT_VIO_B	BT_CONFIG_3	BT_CONFIG_2
	/BTGPIO_SPI_3_INT	/ BT_SPI_DO	/ BT_SPI_DI	/ BT_SPI_CS
F
	BT_CLK_REQ_OUT_2 BT_CLK_REQ_IN_2		BT_VIO_A	BT_UART_CTS	BT_LP_CLK	BT_VDD_D	BT_HVD
				/ BT_SPI_CLK

G

4.1Pin description and assignment

Table 12 shows the pin list of the STA2500D.

In columns “Reset” and “Default after reset”, the “PD/PU” shows the pads implementing an internal pull-down/up.

The column “Reset” shows the state of the pins during hardware reset; the column “Default after reset” shows the state of the pins after the hardware reset state is left, but before any software parameter download.

The column “Type” describes the pin directions:

–I for Input (All inputs have a Schmitt trigger function.)

–O for Output

–I/O for Input/Output

–O/t for tri-state output

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Pinout	STA2500D

For the output pin the default drive capability is 2 mA, except for pin K3 (BT_GPIO_11) and pin L3 (BT_GPIO_8) where it is 8 mA such that when used for Class 1, these 2 pins can be used for a switch control in a cheaper way.

Table 12. The STA2500D pin list (functional and supply)

	Name	Pin	Description	Type	Reset(1)	Default(2)
		#				after reset
	Clock and reset pins
	BT_RESETN	D3	Global reset - active low	-	-
	BT_REF_CLK_IN	D6	Reference clock input(3)	I	Input	Input
	BT_LP_CLK	G3	Low power clock input	-	-
	SW initiated low power mode
			Wake-up signal to Host (Active high or Active		Input PD/PU,	Output
	BT_CLK_REQ_OUT_1	C4			depends on	depends on
			low, depending on configuration pins)
					config	config
	BT_CLK_REQ_OUT_2	G7	Wake-up signal to Host. Active low		Input PU	I/O depends
			(SPI mode only)	I/O(4)		on config
	BT_CLK_REQ_IN_1	E6	Clock request input (Active high)		Input PD	Input PD
	BT_CLK_REQ_IN_2	G6	Clock request input (Active low)		Input PU	Input PU
	BT_HOST_WAKEUP/	F7	Wake-up signal to Host or SPI interrupt		Input PD	Output
	BT_SPI_INT
	BT_WAKEUP	C5	Wake-up signal to Bluetooth (Active high)	I/O	Input (5)	Input
	UART interface
	BT_UART_RXD/	F5	UART receive data			Input PD
	BT_SPI_DI
			SPI data in		Input PD	Input PD
	BT_UART_TXD/	F6	UART transmit data			Output high
	BT_SPI_DO
			SPI data out	I/O(4)		Input PD
	BT_UART_CTS/	G4	UART clear to send			Input PU
	BT_SPI_CLK
			SPI clock		Input PU	Input PD
	BT_UART_RTS/	F4	UART request to send			Output low
	BT_SPI_CSN
			SPI chip select			Input PU
	PCM interface
	BT_PCM_SYNC	C2	PCM frame signal
	BT_PCM_CLK	D1	PCM clock signal	I/O(4)	Input PD	Input PD
	BT_PCM_A	D2	PCM data
	BT_PCM_B	E1	PCM data
	JTAG interface
	BT_GPIO_9	B1	JTAG_TDI or GPIO	-	Input PU(6)	Input PU(6)

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	STA2500D					Pinout
	Table 12. The STA2500D pin list (functional and supply) (continued)
	Name	Pin	Description	Type	Reset(1)	Default(2)
		#				after reset
	BT_GPIO_11	B2	JTAG_TDO or GPIO	-	Input PD(6)	Input PD(6)
	BT_GPIO_10	C1	JTAG_TMS or GPIO	I/O(4)	Input PD(6)	Input PD(6)
	BT_GPIO_16	B3	JTAG_NTRST (Active low) or Alternate	-	Input PD(6)	Input PD(6)
			function.
	BT_GPIO_8	C3	JTAG_TCK or GPIO	-	Input PD(6)	Input PD(6)
	General purpose input/output pins
	BT_GPIO_0	D5	General purpose I/O	I/O(4)	Input PD	Input PD
	Configuration pins
	BT_CONFIG_1	E2		-	-	-
	BT_CONFIG_2	F1	Configuration signal	I	Input	Input
	BT_CONFIG_3	F2		-	-	-
	RF signals
	BT_RFP	A3	Differential RF port	I/O	-	-
	BT_RFN	A4			-	-
	Power supply
	BT_HVA	A7	Power supply (Connect to 2.75 V)	-	-	-
	BT_HVD	G1
	BT_VIO_A	G5	1.65 V to 2.85 V I/Os supply(7)	-	-	-
	BT_VIO_B	F3	1.17 V to 2.85 V I/Os supply(7)	-	-	-
			System clock supply
			1.65 V to 2.85 V
	BT_VDD_CLD	E7	(Connect to BT_VIO_A in case of a digital	-	-	-
			reference clock input, to BT_VSSANA in case
			of an analog reference clock input.)
	BT_VSSDIG	E3	Digital ground	-	-	-
		E4
		B4
	BT_VSSANA	B6	Analog ground	-	-	-
		C6
	BT_VSSRF	A2	RF ground	-	-	-
		A5
			Internal supply decoupling/Regulator output.
	BT_VDD_CL	D7	Need 220nF decoupling capacitor to	-	-	-
			BT_VSSANA.

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	Pinout					STA2500D
	Table 12. The STA2500D pin list (functional and supply) (continued)
	Name	Pin	Description	Type	Reset(1)	Default(2)
		#				after reset
			Internal supply decoupling/Regulator output.
	BT_VDD_D	G2	Need 220nF decoupling capacitor to	-	-	-
			BT_VSSDIG.
			Internal supply decoupling/Regulator output.
	BT_VDD_DSM	B7	Need 220nF decoupling capacitor to	-	-	-
			BT_VSSANA.
			Internal supply decoupling/Regulator output.
	BT_VDD_N	C7	Need 220nF decoupling capacitor to	-	-	-
			BT_VSSANA.
			Internal supply decoupling/Regulator output.
	BT_VDD_RF	A1	Need 220nF decoupling capacitor to	-	-	-
			BT_VSSRF.
	Other pins
	BT_TEST1	B5	Test pin	I/O	Input (8)	Input (8)
	BT_TEST2	A6
	BT_AF_PRG	E5	Test pin (Leave unconnected)(9)	I/O	Open	Open

1.Pin behaviour during HW reset (BT_RESETN low).

2.Pin behaviour immediately after HW reset and internal chip initialization, but before SW parameter download.

3.See also pin BT_VDD_CLD in Table 12.

4.Reconfigurable I/O pin.The functionality of these I/Os can be configured through software parameter download (see

Section 7.5).

5.Should be strapped to BT_VSSDIG if not used.

6.JTAG mode.

7.Described in Section 4.3.

8.To be strapped to BT_VSSANA.

9.Pin is ST - reserved for test function and it must be soldered to an isolated pad (not connected to anything, just floating).

4.2HW configuration of the STA2500D

By means of the three configuration pins, one can select the Host interface (UART or SPI) and clock request signal polarity to be used at startup.

The available combinations of Host interface and protocol are illustrated in Table 13 (where ‘1’ = BT_VIO_A and ‘0’ = BT_VSSDIG). Additionally, the polarity of the BT_CLK_REQ signals can be programmed through the same pins. The polarity of the BT_CLK_REQ_IN and BT_CLK_REQ_OUT signals is further described in Section 6.8.

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STA2500D						Pinout
Table 13.	Configuration programming
BT_CONFIG_1		BT_CONFIG_2	BT_CONFIG_3	Communication	BT_CLK_REQ_OUT_1	BT_CLK_REQ_OUT_2
				Protocol
0		1	0	H4 UART	Active high	Depending on SW
						config
0		1	1	H4 UART	Active low	Depending on SW
						config
1		1	0	Reserved	Reserved	Reserved
1		1	1	Reserved	Reserved	Reserved
1		0	0	Reserved	Reserved	Reserved
1		0	1	Enhanced H4 SPI(1)	Active high	Active low
0		0	1	Reserved	Reserved	Reserved
0		0	0	Reserved	Reserved	Reserved

1.In order to get other SPI modes, the Host must send a specific configuration at start-up in addition of these configuration pins.

4.3I/O Supply

The device STA2500D has two different I/O supplies: BT_VIO_A and BT_VIO_B.

The two different pins may be potentially connected to separate dedicated voltage supplies in order to harmonize the digital levels to the platform.

They are linked to different interfaces as described in Table 14.

	Table 14.	I/O supply split diagram
	I/O supply	Voltage	Function	Associated pins
	name	range [V]
			Configuration	BT_CONFIG_1, BT_CONFIG_2, BT_CONFIG_3
				BT_WAKEUP
			Control	BT_RESETN
				BT_CLK_REQ_OUT_1, BT_CLK_REQ_OUT_2
				BT_GPIO_8 (JTAG_TCK), BT_GPIO_9 (JTAG_TDI),
			GPIO (JTAG)	BT_GPIO_10 (JTAG_TMS), BT_GPIO_11 (JTAG_TDO),
	BT_VIO_A	1.65 - 2.85		BT_GPIO_16 (JTAG_NTRST)
			PCM	BT_PCM_A, BT_PCM_B, BT_PCM_SYNC, BT_PCM_CLK
			Control	BT_REG_CTRL
				BT_UART_RXD (SPI_DI), BT_UART_TXD (SPI_DO),
			UART (SPI)	BT_UART_RTS (SPI_CSN), BT_UART_CTS (SPI_CLK),
				BT_HOST_WAKEUP (SPI_INT)
			Control (GPIO)	BT_CLK_REQ_IN_1 (GPIO_1), BT_CLK_REQ_IN_2 (GPIO_2)
			GPIO	BT_GPIO_0
	BT_VIO_B	1.17 - 2.85	Low - power clock	BT_LP_CLK

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Functional description	STA2500D

5 Functional description

5.1Transmitter

The transmitter uses the serial transmit data from the Bluetooth Controller. The transmitter modulator converts this data into GFSK, π/4-DQPSK or 8-DPSK modulated I and Q digital signals for respectively 1, 2 and 3 Mbps transmission speed. These signals are then converted to analog signals that are low pass filtered before up-conversion. The carrier frequency drift is limited by a closed loop PLL.

5.2Receiver

The STA2500D implements a low-IF receiver for Bluetooth modulated input signals. The radio signal is taken from a balanced RF input and amplified by an LNA. The mixers are driven by two quadrature LO signals, which are locally generated from a VCO signal running at twice the frequency. The I and Q mixer output signals are band pass filtered by a polyphase filter for channel filtering and image rejection. The output of the band pass filter is amplified by a VGA to the optimal input range for the A/D converter. Further channel filtering is done in the digital part. The digital part demodulates the GFSK, π/4-DQPSK or 8-DPSK coded bit stream by evaluating the phase information. RSSI data is extracted. Overall automatic gain amplification in the receive path is controlled digitally. The RC time constants for the analog filters are automatically calibrated on chip.

5.3PLL

The on chip VCO is part of a PLL. The tank resonator circuitry for the VCO is completely integrated without need of external components. Variations in the VCO centre frequency are calibrated out automatically.

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