ST STA2500D User Manual

Bluetooth™ V2.1 + EDR ("Lisbon") for automotive applications

Features

■ Based on Ericsson technology licensing

baseband core (EBC)

■ Bluetooth™ specification compliance:

V2.1 + EDR (“Lisbon”) – Point-to-point, point-to-multipoint (up to 7

slaves) and scatternet capability – Support ACL and SCO links – Extended SCO (eSCO) links – Faster connection

■ HW support for packet types

– ACL: DM1, DM3, DM5, DH1, DH3, DH5, 2-

DH1, 2-DH3, 2-DH5, 3-DH1, 3-DH3, 3-DH5 – SCO: HV1, HV3 and DV – eSCO: EV3, EV4, EV5, 2-EV3, 2-EV5, 3-

EV3, 3-EV5

■ Adaptive frequency hopping (AFH)

■ Channel quality driven data rate (CQDDR)

■ “Lisbon” features

– Encryption pause/resume (EPR) – Extended inquiry response (EIR) – Link supervision time out (LSTO) – Secure simple pairing – Sniff subrating – Quality of service (QoS)

Packet boundary flag

Erroneous data delivery

■ Transmit power

– Power class 2 and power class 1.5 (above

4 dBm) – Programmable output power – Power class 1 compatible

■ HCI

– HCI H4 and enhanced H4 transport layer – HCI proprietary commands (e.g.

peripherals control) – Single HCI command for patch/upgrade

download – eSCO over HCI supported

■

Supports pitch-period error concealment (PPEC)

■ Efficient and flexible support for WLAN

coexistence scenarios

STA2500D

LFBGA48 (6x6x1.4mm; 0.8mm Pitch)

■ Low power consumption

– Ultra low power architecture with 3 different

low-power levels

– Deep sleep modes, including host-power

saving feature

– Dual wake-up mechanism: initiated by the

host or by the Bluetooth device

■ Communication interfaces

– Fast UART up to 4 MHz – Flexible SPI interface up to 13 MHz – PCM interface – Up to 10 additional flexibly programmable

GPIOs

– External interrupts possible through the

GPIOs

–Fast I

■ Clock support

– System clock input (digital or sine wave) at

– Low power clock input at 3.2 kHz, 32 kHz

■ ARM7TDMI CPU

■ Memory organization

– On chip RAM, including provision for

– On chip ROM, preloaded with SW up to

■ Ciphering support up to 128-bit key

■ Single power supply with internal regulators for

core voltage generation

■ Supports 1.65 V to 2.85 V I/O systems

■ Auto calibration (VCO, filters)

C interface as master

9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6 or 38.4 MHz

and 32.768 kHz

patches

HCI

January 2010 Doc ID 16067 Rev 2 1/58

www.st.com

Contents STA2500D

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 HW configuration of the STA2500D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 I/O Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.4 Bluetooth controller V1.2 and V2.0 + EDR features . . . . . . . . . . . . . . . . . 19

5.5 Bluetooth controller V2.1 + EDR (“Lisbon”) . . . . . . . . . . . . . . . . . . . . . . . 19

5.6 Processor and memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.7 TX output power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 General specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3 Class 1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.5 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.6 Low power clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.7 Clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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STA2500D Contents

6.8 Clock request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.10 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.10.2 Some examples for the usage of the low power modes . . . . . . . . . . . . 30

6.10.3 Deep sleep mode entry and wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.11 Patch RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.12 Download of SW parameter file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.13 Bluetooth - WLAN coexistence in collocated scenario . . . . . . . . . . . . . . . 38

6.13.1 Algorithm 1: PTA (packet traffic arbitration) . . . . . . . . . . . . . . . . . . . . . . 38

6.13.2 Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.13.3 Algorithm 3: Bluetooth master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.13.4 Algorithm 4: two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.13.5 Algorithm 5: Alternating wireless medium access (AWMA) . . . . . . . . . . 40

7 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.1 The UART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2 The SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.3 The PCM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.4 The JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5 Alternate I/O functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.6 The I

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8 HCI transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.1 H4 UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.2 Enhanced H4 SPI transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.3 H4 SPI transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.4 eSCO over HCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11 Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Doc ID 16067 Rev 2 3/58

List of tables STA2500D

List of tables

Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. DC input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. DC output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. System clock supported frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. System clock overall specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 7. System clock, sine wave specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 8. System clock, digital clock DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 9. System clock, digital clock AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 10. Low power clock specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 11. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 12. The STA2500D pin list (functional and supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13. Configuration programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 14. I/O supply split diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 15. Mbps receiver parameters - GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 16. Mbps receiver parameters - π/4-DQPSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 17. Mbps receiver parameters - 8-DPSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 18. Transmitter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 19. Output power: class 1 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 20. Output power: class 1 device pin configuration (depending on SW parameter download). 26 Table 21. Output power: class 1 device pin configuration (depending on SW parameter download). 26

Table 22. Use of the BT_CLK_REQ_IN and BT_CLK_REQ_OUT signals in different modes. . . . . . 28

Table 23. Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 24. WLAN HW signal assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 25. SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 26. PCM interface parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 27. PCM interface timing (at PCM_CLK = 2048 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 28. Examples of BT_GPIO pin programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 29. Package markings legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 30. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 31. Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 32. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 33. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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STA2500D List of figures

List of figures

Figure 1. Block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Pinout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. Active high clock request input and output combined with UART or SPI . . . . . . . . . . . . . . 28

Figure 4. Active low clock request input and output combined with UART . . . . . . . . . . . . . . . . . . . . 28

Figure 5. Active low clock request input and output combined with SPI . . . . . . . . . . . . . . . . . . . . . . 28

Figure 6. Deep sleep mode entry and wake-up through H4 UART . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 7. Entering deep sleep mode through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 8. Wake-up by the host through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. Wake-up by the Bluetooth controller with data transmission to the host, through enhanced H4 SPI 34

Figure 10. Deep sleep mode entry and wake-up through H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Entering deep sleep mode, pending data on UART interface, through UART with handshake 36

Figure 12. Wakeup by host through UART with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 13. PTA diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 14. WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 15. Bluetooth master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 16. SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 17. SPI data transfer timing for data length of 8 bits and lsb first, full duplex . . . . . . . . . . . . . . 42

Figure 18. SPI setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19. PCM (A-law, µ-law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 20. Linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 21. Multislot operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 22. PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 23. UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 24. LFBGA48 (6x6x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 50

Figure 25. Package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Doc ID 16067 Rev 2 5/58

Description STA2500D

1 Description

The STA2500D is a single chip Bluetooth solution that is fully optimized for automotive applications such as telematics, navigation and portable navigation. Power consumption levels are targeted at battery powered devices and single chip solution brings cost advantages. Manufacturers can easily and quickly integrate the STA2500D on their product to enable a rapid time to market.

STA2500D supports the Bluetooth specification V2.1 + EDR (“Lisbon“) and is optimized in terms of RF performance and cost.

The STA2500D is a ROM-based solution targeted at applications requiring integration up to HCI level. Patch RAM is available, enabling multiple patches/upgrades and fast time to volume. The STA2500D’s main interfaces are UART or SPI for HCI transport, PCM for voice and GPIOs for control purposes.

The radio has been designed specifically for single chip requirements, for low power consumption and minimum BOM count.

6/58 Doc ID 16067 Rev 2

STA2500D Quick reference data

2 Quick reference data

BT_VIO_x means BT_VIO_A, BT_VIO_B.

BT_HVx means BT_HVA, BT_HVD.

(See also Ta bl e 1 2.)

2.1 Absolute maximum ratings

The absolute maximum rating (AMR) corresponds to the maximum value that can be applied without leading to instantaneous or very short-term unrecoverable hard failure (destructive breakdown).

Table 1. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

BT_HVx Core supply voltages -0.3 4.0 V

BT_VIO_A Supply voltage I/O -0.3 4.0 V

BT_VIO_B Supply voltage I/O (for the low power clock) -0.3 4.0 V

BT_V

ssdiff

stg

Input voltage of any digital pin -0.3 4.0 V

Maximum voltage difference between different types of V

pins.

Storage temperature - 65 + 150 °C

2.2 Operating ranges

Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied.

Table 2. Operating ranges

Symbol Parameter Min. Typ. Max. Unit

BT_T

BT_HVx Core supply voltages 2.65 2.75 2.85 V

BT_VIO_A I/O supply voltage 1.65 - 2.85 V

BT_VIO_B I/O supply voltage (for the low power clock) 1.17 - 2.85 V

Operating ambient temperature -40 25 +85

amb

-0.3 0.3 V

Doc ID 16067 Rev 2 7/58

Quick reference data STA2500D

2.3 I/O specifications

The I/Os comply with the EIA/JEDEC standard JESD8-B.

Table 3. DC input specification

Symbol Parameter Min. Typ. Max. Unit

IL_BT

IH_BT

in_BT

Low level input voltage -0.2 -

High level input voltage

Input capacitance

(1)

Pull-up equivalent resistance (with V

Pull-down equiv. resistance (with V

= 0 V) 31 47 73 kΩ

= BT_VIO_x) 29 50 100 kΩ

0.65 *

BT_VIO_x

1-2.5pF

0.35 *

BT_VIO_x

(BT_VIO_x

+ 0.2) and

(≤ 2.85)

Schmitt trigger hysteresis (at BT_VIO_A = 1.8 V)

hyst

except for BT_CONFIG1-3, BT_RESETN,

0.4 0.5 0.6 V

BT_WAKEUP

Schmitt trigger hysteresis (at BT_VIO_x = 1.8 V)

hyst

for BT_CONFIG1-3, BT_RESETN, BT_WAKEUP,

0.223 - 0.314 V

BT_LP_CLK

hyst

1. Except for the system clock.

Table 4. DC output specification

Schmitt trigger hysteresis (at BT_VIO_B = 1.3 V) 0.2 - 0.3 V

Symbol Parameter Condition Min. Typ. Max. Unit

OL_BT

OH_BT

1. X is the source/sink current under worst-case conditions according to the drive capabilities (see Section 3)

Low level output voltage Id = X

High level output voltage Id = X

(1)

--0.15V

BT_VIO_x

- 0.25

--V

2.4 Clock specifications

The STA2500D supports, on the BT_REF_CLK_IN pin, the system clock both as a sine wave clock and as a digital clock. For configuration, see Tab le 1 2 : pin BT_VDD_CLD (E6).

Table 5. System clock supported frequencies

Symbol Parameter Values Unit

Table 6. System clock overall specifications

Symbol Parameter Min. Typ. Max. Unit

INTOL

8/58 Doc ID 16067 Rev 2

Clock input frequency list

Tolerance on input frequency -20 - 20 ppm

9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6, 38.4

MHz

STA2500D Quick reference data

Table 7. System clock, sine wave specifications

Symbol Parameter Min. Typ. Max. Unit

INRe

INIm

IDRe

IDim

1. Equivalent to max 10 ps time jitter (rms).

Table 8. System clock, digital clock DC specifications

Peak to peak voltage range 0.27 0.5 1.8 V

Total harmonic content of input signal - - -25 dBc

Real part of parallel input impedance at pin 30 60 90 kΩ

Imaginary part of parallel input impedance at pin - 5 8 pF

Real impedance discrepancy between active and nonactive mode of clock input

Imaginary impedance discrepancy between active and non-active mode of clock input

Phase noise @ 10 kHz

(1)

-- 7kΩ

--500fF

---126dBc/Hz

Symbol Parameter Min. Typ. Max. Unit

Table 9. System clock, digital clock AC specifications

Low level input voltage -0.2 -

High level input voltage

BT_VDD_CLD

Input capacitance - 5 8 pF

0.65 *

0.35 *

BT_VDD_CLD

(BT_VDD_CLD

+ 0.2) and

(≤ 2.85)

Symbol Parameter Min. Typ. Max. Unit

RISE

FAL L

CYCLE

- Phase noise @ 10 kHz

1. Equivalent to max 15 ps time jitter (rms).

Table 10. Low power clock specifications

10% - 90% rise time - 1.5 6 ns

90% - 10% fall time - 1.5 6 ns

Duty cycle 45 50 55 %

(1)

- - -121 dBc/Hz

The low power clock pin is powered by connecting BT_VIO_B to the wanted supply.

Symbol Parameter Min. Typ. Max. Unit

- Duty cycle 30 - 70 %

- Tolerance on input frequency −250 - 250 ppm

hyst

Clock input frequencies 3.2, 32, 32.768 kHz

Low level input voltage - -

High level input voltage

0.65 *

BT_VIO_B

--V

0.35 *

BT_VIO_B

Schmitt trigger hysteresis (BT_VIO_B = 1.8 V) 0.4 0.5 0.6 V

Doc ID 16067 Rev 2 9/58

Quick reference data STA2500D

Table 10. Low power clock specifications (continued)

The low power clock pin is powered by connecting BT_VIO_B to the wanted supply.

Symbol Parameter Min. Typ. Max. Unit

hyst

RISE

FAL L

- Total jitter

1. The rise and fall time are not the most important parameters for the low power clock input due to the Schmitt trigger logic. It is more important that the noise on the Low power clock line remains substantially below the hysteresis in amplitude.

2. The total jitter is defined as the error that can appear on the actual frequency between two clock edges compared to the perfect frequency. Due to this, the total jitter value must contain the jitter itself and the error due to the accuracy on the clock frequency. The lower the accuracy, the smaller the jitter is allowed to be.

Schmitt trigger hysteresis (BT_VIO_B = 1.3 V) 0.2 0.3 0.4 V

Input capacitance 1 - 2.5 pF

(1)

--1μs

- - 250 ppm

10% - 90% rise time

90% - 10% fall time

(2)

2.5 Current consumption

= 25°C, 13 MHz digital clock, 7 dBm output power for BR packets, 3 dBm output power

amb

for EDR packets.

Table 11. Current consumption

Complete Power Down 1 μA

Deep Sleep mode 20 μA

Functional Sleep mode

(2)

Sniff mode (1.28 s, 2 attempts, 0 timeouts), combined with H4 UART Deep Sleep mode

(see section 6.10.3) Master mode Slave mode

(1)

State Typ. Unit

1.2 mA

55 83

μA μA

Inquiry scan (1.28 seconds period), combined with H4 UART Deep Sleep mode (see section 6.10.3) 318 μA

HW Page scan (1.28 seconds period), combined with H4 UART Deep Sleep mode (see section 6.10.3) 312 μA

HW Inquiry and Page scan (1.28 seconds period), combined with H4 UART Deep Sleep mode

(see section 6.10.3)

Idle ACL connection (Master) 3.6 mA

Idle ACL connection (Slave) 8.2 mA

Active: audio (HV3) Master (not sniffed) 11.7 mA

Active: audio (HV3) Slave (Sniff 1.28 s, 2 attempts, 0 timeouts) 10.6 mA

Active: data (DH1) Master or Slave (172.8 kbps asymmetrical in TX mode) (172.8 kbps symmetrical)

10/58 Doc ID 16067 Rev 2

591 μA

28.5

STA2500D Quick reference data

Table 11. Current consumption

(1)

(continued)

State Typ. Unit

Active: data (DH5) Master or Slave (723.2 kbps asymmetrical in TX mode) (433.9 kbps symmetrical)

35.4

Active: data (2-DH5) Master or Slave (869.7 kbps symmetrical) 35.4 mA

Active: data (3-DH5) Master or Slave (1306.9 kbps symmetrical) 35.4 mA

Active: audio eSCO (EV3), (64 kbps symmetrical T Master mode Slave mode

Active: audio eSCO (2-EV3), (64 kbps symmetrical T Master mode Slave mode

Active: audio eSCO (3-EV3), (64 kbps symmetrical T Master mode Slave mode

Active: audio eSCO (EV5), (64 kbps symmetrical T

Active: audio eSCO (2-EV5), (64 kbps symmetrical T

Active: audio eSCO (3-EV5), (64 kbps symmetrical T

1. The power consumption (except for power safe modes i.e. complete power down and deep sleep mode) will rise (with approx. 200 µA) if an analog system clock is used instead of a digital clock.

2. In functional sleep mode, the baseband clock is still running.

= 6)

eSCO

12 15

= 12)

eSCO

7.8

11.7

= 18)

eSCO

6.5

10.5

= 36), Master mode 8 mA

eSCO

= 36), Slave mode 11.9 mA

eSCO

= 36), Master mode 6.3 mA

eSCO

= 36), Master mode 5.75 mA

eSCO

mA mA

Doc ID 16067 Rev 2 11/58

Block diagram and electrical schematic STA2500D

3 Block diagram and electrical schematic

Figure 1. Block diagram and electrical schematic

BT_RFP

Filter

BT_RFN

BT_REF_CLK_IN

BT_VDD[4:0]

INTERNAL SUPPLY MANAGEMENT

RECEIVER

RF PLL

Fracti onal N

TRANSMI TTER

AUTOCALIBRATION

BT_TEST[1:0] BT_VDD_CLD

BT_HV[1:0] BT_VIO_A BT_VIO_B

DEMO-

DULATOR

CONTROL

AND

BASEBAND

CORE

MODULATOR

PLL

EBC

AMBA

PERIPH.

BUS

BT_AF_PRG BT_VSS[5:0]

ARM7TDMI

CPU Wrapper

RAM

ROM

INTERRUPT

UART/

SPI

TIMER

PCM

WLAN

I2C

JTAG

BT_GPIO_0

BT_GPIO/JTAG

[4: 0]

BT_LP_CLK

BT_HOST_WAKEUP

BT_SPI_INT

BT_WAKEUP

BT_RESETN

BT_UART/BT_SPI

[3: 0]

BT_PCM

[3: 0]

BT_CONFIG

[2: 0]

BT_CLK_REQ_IN

[1: 0]

BT_CLK_REQ_OUT

[1:0]

12/58 Doc ID 16067 Rev 2

STA2500D Pinout

4 Pinout

Figure 2. Pinout (bottom view)

7654321

BT_VDD_DSM

BT_VDD_N

BT_VDD_CL

BT_VDD_CLD

BT_HOST_WAKEUP

/BT_SPI_I NT

GPIO_ 3

BT_CLK_REQ_OUT_2

BT_TEST2

BT_VSSANA

BT_CLK_REQ_IN _1

BT_UART_T XD

/ BT_SPI_DO

BT_CLK_REQ_IN_2

BT_VSSRF

BT_WAKEUP

BT_GPIO_0

GPIO_ 0

BT_UART_RXD

/ BT_SPI_D I

BT_VSSANABT_VSSANA BT_TEST1

BT_CLK_REQ_OUT_1

BT_UART_R TS

/ BT_SPI_C S

BT_UART_C TS

/ BT_SPI_C LK

BT_RFPBT_RFNBT_HVA

BT_GPIO_16

BT_GPIO_8

JTAG_T CK

BT_RESETNBT_REF_CLK_ IN

BT_VSSDIGBT_VSSDIGBT_AF_PRG

BT_VIO_B

BT_LP_CL K

BT_VSSRF

BT_GPIO_11

BT_PCM_SYNC

BT_CONFIG_1

BT_CONFIG_3

BT_VDD_RF

BT_GPIO_9

BT_GPIO_10

BT_PCM_CLKBT_PCM_A

BT_PCM_B

BT_CONFIG_2

BT_HVDBT_VDD_DBT_VIO_A

4.1 Pin description and assignment

Ta bl e 1 2 shows the pin list of the STA2500D.

In columns “Reset” and “Default after reset”, the “PD/PU” shows the pads implementing an internal pull-down/up.

The column “Reset” shows the state of the pins during hardware reset; the column “Default after reset” shows the state of the pins after the hardware reset state is left, but before any software parameter download.

The column “Type” describes the pin directions:

– I for Input (All inputs have a Schmitt trigger function.)

– O for Output

– I/O for Input/Output

– O/t for tri-state output

Doc ID 16067 Rev 2 13/58

Pinout STA2500D

For the output pin the default drive capability is 2 mA, except for pin K3 (BT_GPIO_11) and pin L3 (BT_GPIO_8) where it is 8 mA such that when used for Class 1, these 2 pins can be used for a switch control in a cheaper way.

Name

Description Type Reset

(3)

I Input Input

(1)

Default

after reset

(2)

Table 12. The STA2500D pin list (functional and supply)

Clock and reset pins

BT_RESETN D3 Global reset - active low - -

BT_REF_CLK_IN D6 Reference clock input

BT_LP_CLK G3 Low power clock input - -

SW initiated low power mode

BT_CLK_REQ_OUT_1 C4

BT_CLK_REQ_OUT_2 G7

Wake-up signal to Host (Active high or Active low, depending on configuration pins)

Wake-up signal to Host. Active low (SPI mode only)

I/O

(4)

Input PD/PU, depends on

config

Input PU

Output depends on

config

I/O depends on config

BT_CLK_REQ_IN_1 E6 Clock request input (Active high) Input PD Input PD

BT_CLK_REQ_IN_2 G6 Clock request input (Active low) Input PU Input PU

BT_HOST_WAKEUP/

BT_SPI_INT

BT_WAKEUP C5 Wake-up signal to Bluetooth (Active high) I/O Input

F7 Wake-up signal to Host or SPI interrupt Input PD Output

(5)

Input

UART interface

BT_UART_RXD/

BT_SPI_DI

UART receive data

SPI data in Input PD

Input PD

BT_UART_TXD/

BT_SPI_DO

BT_UART_CTS/

BT_SPI_CLK

UART transmit data Output high

SPI data out Input PD

I/O

(4)

UART clear to send

SPI clock Input PD

Input PU

BT_UART_RTS/

BT_SPI_CSN

UART request to send Output low

SPI chip select Input PU

PCM interface

BT_PCM_SYNC C2 PCM frame signal

BT_PCM_CLK D1 PCM clock signal

I/O

BT_PCM_A D2 PCM data

BT_PCM_B E1 PCM data

JTAG interface

BT_GPIO_9 B1 JTAG_TDI or GPIO - Input PU

14/58 Doc ID 16067 Rev 2

(4)

Input PD Input PD

(6)

Input PU

(6)

STA2500D Pinout

Table 12. The STA2500D pin list (functional and supply) (continued)

(6)

(2)

Name

Description Type Reset

BT_GPIO_11 B2 JTAG_TDO or GPIO - Input PD

BT_GPIO_10 C1 JTAG_TMS or GPIO I/O

BT_GPIO_16 B3

JTAG_NTRST (Active low) or Alternate function.

(4)

Input PD

- Input PD

BT_GPIO_8 C3 JTAG_TCK or GPIO - Input PD

(1)

(6)

General purpose input/output pins

(4)

BT_GPIO_0 D5 General purpose I/O I/O

Input PD Input PD

Configuration pins

BT_CONFIG_1 E2 - - -

BT_CONFIG_2 F1 Configuration signal I Input Input

BT_CONFIG_3 F2 - - -

RF signals

Default

after reset

Input PD

BT_RFP A3

Differential RF port I/O

BT_RFN A4 - -

Power supply

BT_HVA A7

Power supply (Connect to 2.75 V) - - -

BT_HVD G1

BT_VIO_A G5 1.65 V to 2.85 V I/Os supply

BT_VIO_B F3 1.17 V to 2.85 V I/Os supply

(7)

-- -

System clock supply

1.65 V to 2.85 V

BT_VDD_CLD E7

(Connect to BT_VIO_A in case of a digital

-- -

reference clock input, to BT_VSSANA in case of an analog reference clock input.)

BT_VSSDIG

Digital ground - - -

BT_VSSANA

Analog ground - - -B6

BT_VSSRF

RF ground - - -

BT_VDD_CL D7

Internal supply decoupling/Regulator output. Need 220nF decoupling capacitor to BT_VSSANA.

Doc ID 16067 Rev 2 15/58

-- -

Pinout STA2500D

Table 12. The STA2500D pin list (functional and supply) (continued)

Name

BT_VDD_D G2

BT_VDD_DSM B7

BT_VDD_N C7

BT_VDD_RF A1

Other pins

Description Type Reset

Internal supply decoupling/Regulator output. Need 220nF decoupling capacitor to BT_VSSDIG.

Internal supply decoupling/Regulator output. Need 220nF decoupling capacitor to BT_VSSANA.

Internal supply decoupling/Regulator output. Need 220nF decoupling capacitor to BT_VSSRF.

(1)

Default

after reset

-- -

(2)

BT_TEST1 B5

Test pin I/O Input

(8)

Input

(8)

BT_TEST2 A6

BT_AF_PRG E5 Test pin (Leave unconnected)

1. Pin behaviour during HW reset (BT_RESETN low).

2. Pin behaviour immediately after HW reset and internal chip initialization, but before SW parameter download.

3. See also pin BT_VDD_CLD in Table 12.

4. Reconfigurable I/O pin.The functionality of these I/Os can be configured through software parameter download (see

Section 7.5).

5. Should be strapped to BT_VSSDIG if not used.

6. JTAG mode.

7. Described in Section 4.3.

8. To be strapped to BT_VSSANA.

9. Pin is ST - reserved for test function and it must be soldered to an isolated pad (not connected to anything, just floating).

(9)

I/O Open Open

4.2 HW configuration of the STA2500D

By means of the three configuration pins, one can select the Host interface (UART or SPI) and clock request signal polarity to be used at startup.

The available combinations of Host interface and protocol are illustrated in Tab l e 1 3 (where ‘1’ = BT_VIO_A and ‘0’ = BT_VSSDIG). Additionally, the polarity of the BT_CLK_REQ signals can be programmed through the same pins. The polarity of the BT_CLK_REQ_IN and BT_CLK_REQ_OUT signals is further described in Section 6.8.

16/58 Doc ID 16067 Rev 2

STA2500D Pinout

Table 13. Configuration programming

BT_CONFIG_1 BT_CONFIG_2 BT_CONFIG_3

Communication

Protocol

BT_CLK_REQ_OUT_1 BT_CLK_REQ_OUT_2

0 1 0 H4 UART Active high

0 1 1 H4 UART Active low

Depending on SW

config

Depending on SW

config

1 1 0 Reserved Reserved Reserved

1 1 1 Reserved Reserved Reserved

1 0 0 Reserved Reserved Reserved

1 0 1 Enhanced H4 SPI

(1)

Active high Active low

0 0 1 Reserved Reserved Reserved

0 0 0 Reserved Reserved Reserved

1. In order to get other SPI modes, the Host must send a specific configuration at start-up in addition of these configuration pins.

4.3 I/O Supply

The device STA2500D has two different I/O supplies: BT_VIO_A and BT_VIO_B.

The two different pins may be potentially connected to separate dedicated voltage supplies in order to harmonize the digital levels to the platform.

They are linked to different interfaces as described in Ta bl e 1 4 .

Table 14. I/O supply split diagram

I/O supply

name

BT_VIO_A 1.65 - 2.85

Vol tag e

range [V]

Function Associated pins

Configuration BT_CONFIG_1, BT_CONFIG_2, BT_CONFIG_3

Control

GPIO (JTAG)

PCM BT_PCM_A, BT_PCM_B, BT_PCM_SYNC, BT_PCM_CLK

Control BT_REG_CTRL

UART (SPI)

Control (GPIO) BT_CLK_REQ_IN_1 (GPIO_1), BT_CLK_REQ_IN_2 (GPIO_2)

GPIO BT_GPIO_0

BT_WAKEUP

BT_RESETN

BT_CLK_REQ_OUT_1, BT_CLK_REQ_OUT_2

BT_GPIO_8 (JTAG_TCK), BT_GPIO_9 (JTAG_TDI), BT_GPIO_10 (JTAG_TMS), BT_GPIO_11 (JTAG_TDO), BT_GPIO_16 (JTAG_NTRST)

BT_UART_RXD (SPI_DI), BT_UART_TXD (SPI_DO), BT_UART_RTS (SPI_CSN), BT_UART_CTS (SPI_CLK), BT_HOST_WAKEUP (SPI_INT)

BT_VIO_B 1.17 - 2.85 Low - power clock BT_LP_CLK

Doc ID 16067 Rev 2 17/58

Functional description STA2500D

5 Functional description

5.1 Transmitter

The transmitter uses the serial transmit data from the Bluetooth Controller. The transmitter modulator converts this data into GFSK, π/4-DQPSK or 8-DPSK modulated I and Q digital signals for respectively 1, 2 and 3 Mbps transmission speed. These signals are then converted to analog signals that are low pass filtered before up-conversion. The carrier frequency drift is limited by a closed loop PLL.

5.2 Receiver

The STA2500D implements a low-IF receiver for Bluetooth modulated input signals. The radio signal is taken from a balanced RF input and amplified by an LNA. The mixers are driven by two quadrature LO signals, which are locally generated from a VCO signal running at twice the frequency. The I and Q mixer output signals are band pass filtered by a polyphase filter for channel filtering and image rejection. The output of the band pass filter is amplified by a VGA to the optimal input range for the A/D converter. Further channel filtering is done in the digital part. The digital part demodulates the GFSK, coded bit stream by evaluating the phase information. RSSI data is extracted. Overall automatic gain amplification in the receive path is controlled digitally. The RC time constants for the analog filters are automatically calibrated on chip.

π/4-DQPSK or 8-DPSK

5.3 PLL

The on chip VCO is part of a PLL. The tank resonator circuitry for the VCO is completely integrated without need of external components. Variations in the VCO centre frequency are calibrated out automatically.

18/58 Doc ID 16067 Rev 2

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