NAND/NOR, SRAM
– One bank of 32 KB embedded SRAM
– 64-channel vector interrupt controller (VIC)
– 2 DMA controllers, 16 physical channels
– 32 DMA request for each controller
– Two external DMA requests are supported
■ Display and graphics
– Color LCD controller for STN,TFT or HR-
TFT panels with 24-bit parallel RGB
interface
– Integrated touch screen controller and ADC
– 3D advanced graphics acceleration
– Video input port (VIP) interface
– JPEG baseline profile decoder
STA2065
Cartesio™ family
Data brief
TFBGA372+100 (16x16x1.2mm)
■ Audio interfaces and features
– Four multichannel serial ports (I2S/TDM)
– SPDIF input interface
– C3 hardware reed-solomon decoder
– Sample rate converter
■ Standard interfaces
– Four 16-bit input capture/output compare
– Pulse width light modulator (PWL)
– Four autobaud UART
– Three I
– Two synchronous serial port (SSP, SPI)
– Smartcard interface
– 160 GPIO over 5 32-bit ports
■ Two controller area network (CAN) in
automotive version
■ Programmable voltage IOs: 1.8 V, 2.5 V, 3.3 V
■ V
DDIO_ON
1.25 ±3%V
■ TFBGA 372+100 0.65 mm pitch package,
packing in tray
■ Ambient temperature range: -40 / +85 °C
Table 1.Device summary
Order code
2
C multimaster/slave interfaces
: 1.8 ±10%V, V
Qualification
grade
: VDD,
DD_ON
CPU freq.CAN
■ High throughput interfaces
– 2 ports USB 2.0 OTG with integrated
STA2065NConsumer533 MHzNo
STA2065PConsumer624 MHzNo
physical layers
– 3 SD/MMC up to 8 bit data, all bootable
October 2009Doc ID16050 Rev 31/20
For further information contact your local STMicroelectronics sales office.
STA2065 is a highly integrated SOC application processor combining host capability with
high performance embedded GPS.
STA2065 targets vehicle head units and mobile navigation (PND), telematics, infotainment,
advanced audio and connectivity systems. The STA2065 provides all the elements that are
essential to build a cost effective solution.
Figure 1.Application implementation example
NOR /
USB2.0
USB2.0
W/ UART
W/ UART
mode
mode
NOR /
NAND
NAND
Flash
Flash
SD
SD
MMC
MMC
SD
SD
MMC
MMC
SD/MMC
SD/MMC
slot
slot
GPS
GPS
SD2SD1SD0
SD2SD1SD0
SD/SDIO
SD/SDIO
(e.g.WIFI)
(e.g.WIFI)
Video IN
Video IN
GPS
GPS
Ctrl
Ctrl
HCI
HCI
SCO
SCO
GPS RF
GPS RF
Blue
Blue
Tooth
Tooth
GPS
GPS
BT
BT
TCXO
TCXO
Saw
Saw
Filter
Filter
Li-Ion Battery
Li-Ion Battery
Audio
Audio
Amplifier
Amplifier
Power
Power
Management
Management
IC
IC
USB 2.0
USB 2.0
Conn.
Conn.
mDDR/
mDDR/
DDR2
DDR2
I2S
I2S
MSPx
MSPx
I2C
I2C
I2C
I2C
BL
BL
Ctrl
Ctrl
TS Cont.
TS Cont.
W/ ADC
W/ ADC
Power
Power
TFT
TFT
backlight
backlight
4/20Doc ID16050 Rev 3
STA2065System description
2 System description
2.1 MCU
ARM1176-JZF advanced risc machine CPU up to 624 MHz (with Vdd greater or equal to
1.20 V and under process and temperature worst case conditions).
2.2 Embedded memories
2.2.1 Embedded SRAM (eSRAM)
The embedded SRAM is 8K x 32 (32 KB).
2.3 System functions
2.3.1 System and reset controller (SRC)
This provides a control interface for clock generation components external to the subsystem.
It also controls system-wide and peripherals-specific energy management features.
2.3.2 PMU
The power manager module controls the SLEEP to DEEP-SLEEP modes transition,
controls the external voltage switches on the Vdd and Vddio, monitors the external power
supply (via two signals, Vddok and BATOK), can force the emergency entry of the SDRAM
in self-refresh, and controls the wake-up from DEEP-SLEEP mode.
2.3.3 DMA
Direct memory access can be used with DMA peripherals. FIFO fill/empty requests from
these peripherals can be serviced immediately by the DMA Controller without CPU
interaction. Peripheral-to-peripheral and memory-to-memory DMA are also supported.
STA2065 features two DMA engines. Each DMA supports up to 8-channels and up to 32
requests.
2.3.4 Vectored interrupt controller (VIC)
The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in
response to peripheral interrupts.
2.3.5 GPIOs
Four GPIO ports provide 160 programmable inputs or outputs that can be controlled in two
modes:
●software mode through an APB bus interface
●hardware mode through a hardware control interface
Doc ID16050 Rev 35/20
System descriptionSTA2065
2.3.6 Real-time clock (RTC)
The RTC provides a one second resolution clock. This keeps time when the system is
inactive and can be used to wake the system up when a programmed ‘alarm’ time is
reached. It has a clock trimming feature to compensate the drift of the 32.768 kHz crystal.
2.3.7 Real-time timer (RTT)
The RTT has the possibility of being clocked off. This reduces the always_on domain
consumption during Deep Sleep. By default the RTT has its clock enabled.
2.3.8 Always_ON supply
The “Always_ON” domain retains its two separate supplies, one for the core logic (V
and one for the IOs (V
The V
supply is equal to VDD during normal operation but, with the goal of reaching the
DDON
IOON
).
lowest consumption possible, can also be configured as low as 1.0 ±10%V when the device
is in deep-sleep.
2.3.9 Enhanced function timer (EFT)
STA2065 features 4 16-bit EFTs. Each of the four EFT timers has a 16-bit free-running
counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse
counter function, and a PWM channel with selectable frequency.
2.3.10 Watchdog timer (WDT)
This OS resource is used to trigger a system reset in the event of software failure.
2.4 Memory interfaces
2.4.1 Flexible static memory controller (FSMC)
The flexible static memory controller (FSMC) supports, with two chip selects:
●ROM
●Static RAM
●NOR type flash memories, not multiplexed
●NOR type flash memories, multiplexed
DDON
)
It also supports, with two additional separate chip selects:
●NAND type flash memories, SLC small or large page
●NAND type flash memories, MLC
For NAND type of memories, the FSMC has been enhanced to implement an error
correction in hardware, based on the Bose-Chaudhuri-Hocquenghem (BCH) code, able to
correct up to 8-bit over 512 bytes+syndrome. The BCH code will calculate, in hardware, the
syndrome only. The actual correction will be implemented through S/W intervention.
6/20Doc ID16050 Rev 3
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