ST STA120 User Manual
DIGITAL AUDIO INTERFACE RECEIVER
■
MONOLITHIC CMOS RECEIVER
■
3.3V SUPPLY VOLTAG E
■
LOW-JITTER, ON-CHIP CLOCK RECOVERY
256xFs OUTPUT CLOCK PR OVI DED
■
SUPPORTS: AES/ EBU, IEC 958, S/PDIF, &
EIAJ CP-340/ 1 201 PR OFESSIONAL AND
CONSUMER FORMATS
■
EXTENSIVE ERROR REPO R TING REPEAT
LAST SA M P LE ON ERROR OPTION
STA120
SO28
ORDERING NUMBER: STA120D
DESCRIPTION
The STA120 is a monolithic CMOS device that receives and decodes audio data according to the
AES/EBU, I EC 9 5 8, S/PDIF, & EIAJ CP- 340 /1201
interface standards.
The STA120 recovers the clock and synchroniza-
BLOCK DIAGRAM
VA+ MCK
CLOCK & DATA
RECOVERY
MUX
RXP
RXN
9
10
DGNDVD+
87
RS422
Receiver
MUX
tion signals and de-multiplexes the audio and digital data. Differential or single ended inputs can be
decoded.
The STA120 de-multiplexes the channel, user and
validity data directly to serial output pins with dedicated output pins for the most important channel
status bits.
M2 M0AGNDFILT
AUDIO
REGISTERS
M1
24
2318
26
12
11
1
14
28
19212022
M3
17
SERIAL PORT
DE MUX
SDATA
SCK
FSYNC
C
U
VREF
December 2002
13
CS12/FCK16SEL
6
C0/E0
Ca/E15Cb/E24Cc/F03Cd/F12Ce/F2
27
25 15
ERF CBL
D97AU613A
1/15
STA120
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
D+
, V
Power Supply Voltage 4 V
A+
V
IN
T
amb
T
stg
Input Voltage ( excluding pins 9, 10) -0.3 to VD+ +0.3 V
Ambient Operating Temperature (power applied) -30 to +85 °C
Storage Temperature -40 to 150 °C
PIN CONNECTIONS
(Top view)
CS12/FCK
1
C
Cd/F1
Cc/F0
Cb/E2
Ca/E1 M1
C0/E0
VD+
DGND
RXP
RXN
FSYNC
SCK
2
3
4
5
6
7
8
9
10
11
12
13
14
U
D97AU609A
28
27
26
25
24
22
21
20
19
18
17
16
15
VERF
Ce/F2
SDATA
ERF
M023
VA+
AGND
FILT
MCK
M2
M3
SEL
CBL
PINS DESCRIPTION
N. Name Description
Power Supply
7V
8 DGND Digital Ground.Ground for the digital section.
21 AGND Analog Ground.Ground for the analog section. AGND should be connected to same ground as
22 V
Audio Output Interface
11 FSYNC Frame Sync.Delineates the serial data and may indicate the particular channel, left or right and
12 SCK Serial Clock.Serial clock for SDATA pin which can be configured (via the M0, M1, M2 and M3
17, 18,
23, 24
M2, M3,
M1, M0
26 SDATA Serial Data. Audio data serial output pin.
2/15
Positive Digital Power.Positive supply for the digital section. Nominally 3.3V.
D+
DGND.
Positive Analog Power.Positive supply for the analog section. Nominally 3.3V.
A+
may be an input or output. The format is based on M0, M1, M2 and M3 pins.
pins) as an input or output and can sample data on the rising or falling edge. As an output, SCK
will generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample
must be provided in all normal modes.
Serial Port Mode Selects.Selects the format of Fsync and the sample edge of SCK with respect
to SDATA.
STA120
PINS DESCRIPTION
N. Name Description
Control Pins
1 C Channel Status Output. Rec eived channel sta tus bit ser ial output po rt . FSYNC may be use d to
2 Cd Channel Status Outp ut Bits.These pin are dual Func tion with the "C" bits selected when SEL is
F1 Frequency reporting Bits.Encoder sample frequency information that is enabled by bringing SEL
3 Cc Cha nnel Status Outp ut Bits.These pin are dual Func tion with the "C" bits selected when SEL is
F0 Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL
4 Cb Channel Status Outp ut Bits.These pin are dual Func tion with the "C" bits selected when SEL is
E2 Error Co nditio n.En coded err or informat ion t hat is en abled by br ing ing SEL low. The error cod es
5 Ca Channel Status Outp ut Bits.These pin are dual Func tion with the "C" bits selected when SEL is
5 E2 Erro r Co nditio n.En coded err or in format ion t hat is en abled by br ing ing SEL low. The error cod es
6C0
E0 Error Co nditio n.En coded err or informat ion t hat is en abled by br ing ing SEL low. The error cod es
13 CS12 Channel Select.This pin is also dual function and is selected by bringing SEL high. CS12 selects
FCK Frequency Clock.Frequency Clock input that is enabled by bringing SEL low. FCK is compared to
14 U User Bi t.Received user bit ser ial output por t, FSYNC m ay be used to latch this bit externally.
15 CBL Channel Sta tus Block Start.The channel status block outpu t is high for the first four bytes of
(continued)
2
latch this b it externa lly. Excep t in I
Fsync.
high. Channel status informat ion is displayed for the channel selected by CS12. C0
channel status bit 0, defines professional (C0
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
low. A proper clock on F CK must be input for at least two thirds of a channel status block for
these pins to be valid. They are updated three times per block, starting at the block boundary.
high. Channel status informat ion is displayed for the channel selected by CS12. C0
channel status bit 0, defines professional (C0
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
low. A proper clock on F CK must be input for at least two thirds of a channel status block for
these pins to be valid. They are updated three times per block, starting at the block boundary.
high. Channel status informat ion is displayed for the channel selected by CS12. C0
channel status bit 0, defines professional (C0
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
are prior itized and latch ed so that the erro r code disp layed is the highes t level of error since the
last clearing of the error pins. Clearing is accomplish ed by bringing SEL high for more than 8
MCK cycles.
high. Channel status informat ion is displayed for the channel selected by CS12. C0
channel status bit 0, defines professional (C0
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
are prior itized and latch ed so that the erro r code disp layed is the highes t level of error since the
last clearing of the error pins. Clearing is accomplish ed by bringing SEL high for more than 8
MCK cycles.
Channel Status Outp ut Bits.These pin are dual Func tion with the "C" bits selected when SEL is
high. Channel status informat ion is displayed for the channel selected by CS12. C0
channel status bit 0, defines professional (C0
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
are prior itized and latch ed so that the erro r code disp layed is the highes t level of error since the
last clearing of the error pins. Clearing is accomplish ed by bringing SEL high for more than 8
MCK cycles.
sub-frame1 (when low) or sub- frame2 (wh en high ) to be displayed by channel status pins C0
Ca through Ce.
the received clock frequency w ith the value displayed on F2 through F0. No minal input value is
6.144MHz.
Except in I2S modes when this pin is updated at the active edge off Fsync.
channel status and low for the last 20 bytes.
S modes when this pin is updated at the active edge off
= 0) or consumer (C0 = 1) mode an d further
= 0) or consumer (C0 = 1) mode an d further
= 0) or consumer (C0 = 1) mode an d further
= 0) or consumer (C0 = 1) mode an d further
= 0) or consumer (C0 = 1) mode an d further
, which is
, which is
, which is
, which is
, which is
an
3/15
STA120
PINS DESCRIPTION
(continued)
N. Name Description
16 SEL Select.Control pin that selects either channel status information (SEL = 1) or error and frequency
information (SEL = 0) to be displayed on six (C0
, Ca Cb, Cc, Cd, Ce) pins.
27 Ce Channel Status Outp ut Bits.These pin are dual Func tion with the "C" bits selected when SEL is
high. Channel status informat ion is displayed for the channel selected by CS12. C0 , which is
channel status bit 0, defines professional (C0
= 0) or consumer (C0 = 1) mode an d further
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
F2 Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL
low. A proper clock on F CK must be input for at least two thirds of a channel status block for
these pins to be valid. They are updated three times per block, starting at the block boundary.
28 VERF Validity + Error Flag. A logic al OR'ing of the validity bit from the rece ived data and the erro r flag.
May be used by interpolation filters to interpolate through errors.
Receiver Interface
9 RXP Line Receiver. (RS422 compatible)
10 RXN Line Receiver. (RS422 compatible)
Phase Locked Loop
19 MCK Master Clock.Low Jitter clock output of 256 times the received sample frequency.
20 FILT Filter.An external 330 Ohm resistor and 0.47µF capaci tor in parallel with a 15nF cap acitor is
required from FILT pin to analog ground.
25 E RF Erro r Flag,Signals th at an error has oc curred while rece iving the audio sa mple currently be ing
read from the serial port. Three errors cause ERF to go high: a parity or biphase coding violation
during the current sample, or an out of lock PLL receiver.
DIGITAL CHARACTERISTICS
(T
= 25°C; VD+, VA+ = 3.3V ±10%)
amb
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
D+,VA+
V
V
V
V
F
MCK Master Clock frequency (Note 1) 6.4
Power supply voltage Range 3.0 3.3 3.6 V
High-Level Input Voltage 2.0 V
IH
Low-Level Input Voltage +0.8 V
IL
High-Level Output Voltage IO = 200µA
OH
Low-Level Output Voltage IO = 3.2mA 0.4 V
OL
I
Input Leakage Curren t 1.0 10 µA
in
Input Sample Frequency (Note 1) 25 96 kHz
S
VDD-1.0
256xFS
t
MCK Clock Jitter 300
j
V
25 MHz
ps RMS
MCK Duty Cycle (high time/cycle time) 50 %
I
dd_ST
I
dd_DYN
Note 1: FS is defined as the i ncoming audio sample f requency per channel.
SWITCHING CHARACTERISTICS - SERIAL PORTS
Static Idd (MCK = 0) 0.1 1 mA
Dynamic Idd 6 15 mA
(T
= 25°C; VD+, VA+ = 3.3V ±10%)
amb
Symbol Parameter Test Condition Min. Typ. Max. Unit
f
Note 2: The ou tput word r ate, O WR, refe rs to the f requ enc y at whi ch an au dio sampl e i s ou tp ut f rom the p art. (A ster eo pa ir is tw o a ud io
SCK Frequency (Note 2) OWRx32 Hz
sck
samples). Therefore, in Mas t er mode, there are always 32 SCK periods i n one audio sample. In S l ave mode 32 SCK peri ods must
be provided in most serial port formats.
4/15
Figure 1. Circuit Diagram
3.3V
ANALOG
3.3V
DIGITAL
STA120
VD+
0.1µF
7
8
MCK
19
VERF
28
12
SDATA
26
FSYNC
11
C
1
U
14
CBL
15
AUDIO
DATA
PROCESSOR
µCONTROLLER
or
LOGIC
D97AU611
RECEIVER
CIRCUIT
(See Appendix A)
CHANNEL STATUS
and/or
ERROR/FREQUENCY
REPORTING
330Ω
0.47µF
15nF
0.1µF
CS12/FCK
C/E-F bits
VA+
AGND
RXP
RXN SCK
SEL
ERF
FILT
22
21
9
10
13
STA120
16
25
6
20
DGND
GENERAL DESCRIPTION
The STA120 is a m onolithic CMOS circuit that receives a nd decodes audio and digital d ata acco rding to
the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340/1201 interface standards.
It contains a RS422 line recei ver and P hase-Locked Loops (PLL) that recovers the c lock and synchronization signals and de-multiplexes the audio and digital data. The STA120 de-multiplexes the channel status, user and validity information directly to serial output pins wi th dedicated pins for the m ost important
channel status bits.
Line Receiver
The line receiver can decode differential as well as single ende d inputs. The receiver cons its of a differential input Schmitt trigger with 50mV of hysteresis. The hysteresis prevents noisy signals from corrupting
the phase detector. A ppendi x A contains more informa tion on how to configure the li ne recei v ers f or di fferential and single ended signals.
Clocks and Jitter Attenuation
The primary function of this chip is to recover audio d ata and low jitter clocks from a digital audio transmission line. The cloc ks that can be generated are MCK (256xFS), SCK (64xFS), and FSYNC (F S or
2xFS). MCK is the out put of the v oltage controlled o scillator which is a compo nent of th e PLL. Th e PLL
consists of phase and frequency detectors, a second-order loop filter, and a voltage controlled oscillator.
All components of the PLL are on chip with the exception of a resistor and capacitors used in the loop filter.
This filter is connected between the FILT pin an d AGND. The closed-loop transfer func tion, which s pecifies the PLL's jitter attenuation characteristics, is shown in Figure 2.
The loop wil l begin to at tenuate jitter at approximately 25kHz with anot her pole at 80kHz and w ill have
50dB of attenuation by 1MHz. Since most data jitter introduced by the transmission line is high in frequency, it will be strongly attenuated.
Multiple frequency detectors are us ed to minimize th e time it takes the P LL to lock to the inc oming data
stream and to prevent false lock conditions. When the PLL is not locked to the incoming data stream, the
5/15
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