ST STA120 User Manual

STA120

DIGITAL AUDIO INTERFACE RECEIVER

■MONOLITHIC CMOS RECEIVER

■3.3V SUPPLY VOLTAGE

■LOW-JITTER, ON-CHIP CLOCK RECOVERY 256xFs OUTPUT CLOCK PROVIDED

■SUPPORTS: AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201 PROFESSIONAL AND CONSUMER FORMATS

■EXTENSIVE ERROR REPORTING REPEAT LAST SAMPLE ON ERROR OPTION

DESCRIPTION

The STA120 is a monolithic CMOS device that receives and decodes audio data according to the AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201 interface standards.

The STA120 recovers the clock and synchroniza-

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ORDERING NUMBER: STA120D

tion signals and de-multiplexes the audio and digital data. Differential or single ended inputs can be decoded.

The STA120 de-multiplexes the channel, user and validity data directly to serial output pins with dedicated output pins for the most important channel status bits.

BLOCK DIAGRAM

VD+		DGND	VA+		FILT	AGND		MCK			M3	M2	M1	M0
7		8		22	20		21		19			17	18	24	23
															26
															SDATA
												AUDIO			12
9															SCK
												SERIAL PORT
RXP				CLOCK & DATA											11
		RS422		RECOVERY											FSYNC
10	Receiver								DE MUX						1
RXN
															C
												REGISTERS			14
															U
		MUX						MUX							28
															VREF
		13	16		6	5		4	3	2	27		25	15
	CS12/FCK		SEL	C0/E0		Ca/E1	Cb/E2		Cc/F0	Cd/F1	Ce/F2	ERF		CBL	D97AU613A

December 2002

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ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Value	Unit
VD+, VA+	Power Supply Voltage	4	V
VIN	Input Voltage ( excluding pins 9, 10)	-0.3 to VD+ +0.3	V
Tamb	Ambient Operating Temperature (power applied)	-30 to +85	°C
Tstg	Storage Temperature	-40 to 150	°C

PIN CONNECTIONS (Top view)

		C		1	28		VERF
Cd/F1				2	27		Ce/F2
Cc/F0				3	26		SDATA
Cb/E2				4	25		ERF
Ca/E1				5	24		M1
			6		23		M0
	C0/E0
	VD+		7		22		VA+
DGND			8		21		AGND
	RXP		9		20		FILT
	RXN		10		19		MCK
FSYNC			11		18		M2
	SCK		12		17		M3
CS12/FCK			13		16		SEL
		U	14		15		CBL

D97AU609A

PINS DESCRIPTION

N.	Name	Description
Power Supply
7	VD+	Positive Digital Power.Positive supply for the digital section. Nominally 3.3V.
8	DGND	Digital Ground.Ground for the digital section.
21	AGND	Analog Ground.Ground for the analog section. AGND should be connected to same ground as
		DGND.
22	VA+	Positive Analog Power.Positive supply for the analog section. Nominally 3.3V.
Audio Output Interface
11	FSYNC	Frame Sync.Delineates the serial data and may indicate the particular channel, left or right and
		may be an input or output. The format is based on M0, M1, M2 and M3 pins.
12	SCK	Serial Clock.Serial clock for SDATA pin which can be configured (via the M0, M1, M2 and M3
		pins) as an input or output and can sample data on the rising or falling edge. As an output, SCK
		will generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample
		must be provided in all normal modes.
17, 18,	M2, M3,	Serial Port Mode Selects.Selects the format of Fsync and the sample edge of SCK with respect
23, 24	M1, M0	to SDATA.
26	SDATA	Serial Data. Audio data serial output pin.

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				STA120
PINS DESCRIPTION (continued)
N.	Name			Description
Control Pins
1		C		Channel Status Output. Received channel status bit serial output port. FSYNC may be used to
				latch this bit externally. Except in I2S modes when this pin is updated at the active edge off
				Fsync.
2		Cd		Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
				high. Channel status information is displayed for the channel selected by CS12. C0, which is
				channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further
				controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
		F1		Frequency reporting Bits.Encoder sample frequency information that is enabled by bringing SEL
				low. A proper clock on FCK must be input for at least two thirds of a channel status block for
				these pins to be valid. They are updated three times per block, starting at the block boundary.
3		Cc		Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
				high. Channel status information is displayed for the channel selected by CS12. C0, which is
				channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further
				controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
		F0		Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL
				low. A proper clock on FCK must be input for at least two thirds of a channel status block for
				these pins to be valid. They are updated three times per block, starting at the block boundary.
4		Cb		Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
				high. Channel status information is displayed for the channel selected by CS12. C0, which is
				channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further
				controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
		E2		Error Condition.Encoded error information that is enabled by bringing SEL low. The error codes
				are prioritized and latched so that the error code displayed is the highest level of error since the
				last clearing of the error pins. Clearing is accomplished by bringing SEL high for more than 8
				MCK cycles.
5		Ca		Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
				high. Channel status information is displayed for the channel selected by CS12. C0, which is
				channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further
				controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
5		E2		Error Condition.Encoded error information that is enabled by bringing SEL low. The error codes
				are prioritized and latched so that the error code displayed is the highest level of error since the
				last clearing of the error pins. Clearing is accomplished by bringing SEL high for more than 8
				MCK cycles.
6		C0		Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
				high. Channel status information is displayed for the channel selected by CS12. C0, which is
				channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further
				controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
		E0		Error Condition.Encoded error information that is enabled by bringing SEL low. The error codes
				are prioritized and latched so that the error code displayed is the highest level of error since the
				last clearing of the error pins. Clearing is accomplished by bringing SEL high for more than 8
				MCK cycles.
13	CS12			Channel Select.This pin is also dual function and is selected by bringing SEL high. CS12 selects
				sub-frame1 (when low) or sub-frame2 (when high) to be displayed by channel status pins C0 an
				Ca through Ce.
	FCK			Frequency Clock.Frequency Clock input that is enabled by bringing SEL low. FCK is compared to
				the received clock frequency with the value displayed on F2 through F0. Nominal input value is
				6.144MHz.
14		U		User Bit.Received user bit serial output port, FSYNC may be used to latch this bit externally.
				Except in I2S modes when this pin is updated at the active edge off Fsync.
15	CBL			Channel Status Block Start.The channel status block output is high for the first four bytes of
				channel status and low for the last 20 bytes.

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PINS DESCRIPTION (continued)

N.	Name		Description
16	SEL		Select.Control pin that selects either channel status information (SEL = 1) or error and frequency
			information (SEL = 0) to be displayed on six (C0, Ca Cb, Cc, Cd, Ce) pins.
27	Ce		Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
			high. Channel status information is displayed for the channel selected by CS12. C0, which is
			channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further
			controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
	F2		Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL
			low. A proper clock on FCK must be input for at least two thirds of a channel status block for
			these pins to be valid. They are updated three times per block, starting at the block boundary.
28	VERF		Validity + Error Flag. A logical OR'ing of the validity bit from the received data and the error flag.
			May be used by interpolation filters to interpolate through errors.
Receiver Interface
9	RXP		Line Receiver. (RS422 compatible)
10	RXN		Line Receiver. (RS422 compatible)
Phase Locked Loop
19	MCK		Master Clock.Low Jitter clock output of 256 times the received sample frequency.
20	FILT		Filter.An external 330 Ohm resistor and 0.47μF capacitor in parallel with a 15nF capacitor is
			required from FILT pin to analog ground.
25	ERF		Error Flag,Signals that an error has occurred while receiving the audio sample currently being
			read from the serial port. Three errors cause ERF to go high: a parity or biphase coding violation
			during the current sample, or an out of lock PLL receiver.

DIGITAL CHARACTERISTICS (Tamb = 25°C; V D+, VA+ = 3.3V ±10%)

Symbol	Parameter	Test Condition	Min.	Typ.	Max.	Unit
VD+,VA+	Power supply voltage Range		3.0	3.3	3.6	V
VIH	High-Level Input Voltage		2.0			V
VIL	Low-Level Input Voltage				+0.8	V
VOH	High-Level Output Voltage	IO = 200μA	VDD-1.0			V
VOL	Low-Level Output Voltage	IO = 3.2mA			0.4	V
Iin	Input Leakage Current			1.0	10	μA
FS	Input Sample Frequency	(Note 1)	25		96	kHz
MCK	Master Clock frequency	(Note 1)	6.4	256xFS	25	MHz
tj	MCK Clock Jitter			300		ps RMS
	MCK Duty Cycle	(high time/cycle time)		50		%
Idd_ST	Static Idd (MCK = 0)			0.1	1	mA
Idd_DYN	Dynamic Idd			6	15	mA

Note 1: FS is defined as the incoming audio sample frequency per channel.

SWITCHING CHARACTERISTICS - SERIAL PORTS (Tamb = 25°C; V D+, VA+ = 3.3V ±10%)

Symbol	Parameter		Test Condition	Min.	Typ.	Max.	Unit
fsck	SCK Frequency	(Note 2)			OWRx32		Hz

Note 2: The output word rate, OWR, refers to the frequency at which an audio sample is output from the part. (A stereo pair is two audio samples). Therefore, in Master mode, there are always 32 SCK periods in one audio sample. In Slave mode 32 SCK periods must be provided in most serial port formats.

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Figure 1. Circuit Diagram

			3.3V	3.3V
			ANALOG	DIGITAL
		0.1μF		0.1μF
			VA+	VD+
		AGND	22	7	MCK
			21	19
		RXP
			9		VERF
	RECEIVER			28
	CIRCUIT	RXN			SCK	AUDIO
	(See Appendix A)		10	12
						DATA
					SDATA	PROCESSOR
		CS12/FCK		26
			13
		SEL	STA120		FSYNC
	CHANNEL STATUS		16	11
	and/or
		ERF
	ERROR/FREQUENCY		25
	REPORTING				C
						μCONTROLLER
		C/E-F bits		1
			6		U
				14		or
		FILT			CBL	LOGIC
			20	15
	330Ω			8
	15nF
	0.47μF			DGND
						D97AU611

GENERAL DESCRIPTION

The STA120 is a monolithic CMOS circuit that receives and decodes audio and digital data according to the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340/1201 interface standards.

It contains a RS422 line receiver and Phase-Locked Loops (PLL) that recovers the clock and synchronization signals and de-multiplexes the audio and digital data. The STA120 de-multiplexes the channel status, user and validity information directly to serial output pins with dedicated pins for the most important channel status bits.

Line Receiver

The line receiver can decode differential as well as single ended inputs. The receiver consits of a differential input Schmitt trigger with 50mV of hysteresis. The hysteresis prevents noisy signals from corrupting the phase detector. Appendix A contains more information on how to configure the line receivers for differential and single ended signals.

Clocks and Jitter Attenuation

The primary function of this chip is to recover audio data and low jitter clocks from a digital audio transmission line. The clocks that can be generated are MCK (256xFS), SCK (64xFS), and FSYNC (FS or 2xFS). MCK is the output of the voltage controlled oscillator which is a component of the PLL. The PLL consists of phase and frequency detectors, a second-order loop filter, and a voltage controlled oscillator.

All components of the PLL are on chip with the exception of a resistor and capacitors used in the loop filter. This filter is connected between the FILT pin and AGND. The closed-loop transfer function, which specifies the PLL's jitter attenuation characteristics, is shown in Figure 2.

The loop will begin to attenuate jitter at approximately 25kHz with another pole at 80kHz and will have 50dB of attenuation by 1MHz. Since most data jitter introduced by the transmission line is high in frequency, it will be strongly attenuated.

Multiple frequency detectors are used to minimize the time it takes the PLL to lock to the incoming data stream and to prevent false lock conditions. When the PLL is not locked to the incoming data stream, the

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