ST92124xxx-Auto/ST92150xxxxx-Auto
ST92250xxxx-Auto
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
■Memories
–Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
–In-Application Programming (IAP)
–224 general purpose registers (register file) available as RAM, accumulators or index pointers
■Clock, Reset and Supply Management
–Register-oriented 8/16 bit CORE with RUN, WFI, SLOW, HALT and STOP modes
–0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
–PLL Clock Generator (3-5 MHz crystal)
–Minimum instruction time: 83 ns (24 MHz int. clock)
■Up to 80 I/O pins
■Interrupt Management
–4 external fast interrupts + 1 NMI
–Up to 16 pins programmable as wake-up or additional external interrupt with multi-level interrupt handler
■DMA controller for reduced processor overhead
■Timers
–16-bit Timer with 8-bit Prescaler, and Watchdog Timer (activated by software or by hardware)
–16-bit Standard Timer that can be used to generate a time base independent of PLL Clock Generator
–Two 16-bit independent Extended Function Timers (EFTs) with Prescaler, up to two Input Captures and up to two Output Compares
–Two 16-bit Multifunction Timers, with Prescaler, up to two Input Captures and up to two Output Compares
LQFP64 |
PQFP100 |
|
14x14 |
||
14x20 |
||
|
||
|
LQFP100 |
|
|
14x14 |
■Communication Interfaces
–Serial Peripheral Interface (SPI) with Selectable Master/Slave mode
–One Multiprotocol Serial Communications Interface with asynchronous and synchronous capabilities
–One asynchronous Serial Communications Interface with 13-bit LIN Synch Break generation capability
–J1850 Byte Level Protocol Decoder (JBLPD)
–Up to two full I²C multiple Master/Slave Interfaces supporting Access Bus
–Up to two CAN 2.0B Active interfaces
■Analog peripheral (low current coupling)
–10-bit A/D Converter with up to 16 robust input channels
■Development Tools
–Free High performance Development environment (IDE) based on Visual Debugger, Assembler, Linker, and C-Compiler; Real Time Operating System (OSEK OS, CMX) and CAN drivers
–Hardware Emulator and Flash Programming Board for development and ISP Flasher for production
DEVICE SUMMARY(1)
Device |
Flash(2) |
RAM(2) |
E3 TM(2) |
Timers |
Serial Interface |
ADC |
Network Interface |
Packages |
ST92124R9T-Auto |
64K |
2K |
|
|
SCI, SPI, I²C |
|
- |
LQFP64 |
ST92124V1Q-Auto |
128K |
4K |
|
|
2xSCI, SPI, I²C |
|
LIN Master |
PQFP100 |
ST92124V1T-Auto |
6K |
|
|
|
LQFP100 |
|||
|
|
|
|
|
|
|||
ST92150CR9T-Auto |
64K |
2K |
|
2xMFT, |
SCI, SPI, I²C |
|
CAN |
LQFP64 |
ST92150CV9T-Auto |
|
2xSCI, SPI, I²C |
16 x 10 |
CAN, LIN Master |
LQFP100 |
|||
|
|
|
2xEFT, |
|||||
ST92150CV1Q-Auto |
|
|
1K |
|
|
PQFP100 |
||
|
|
STIM, |
2xSCI, SPI, I²C |
bits |
CAN |
|||
ST92150CV1T-Auto |
|
|
|
LQFP100 |
||||
128K |
6K |
|
WD |
|
|
|
||
ST92150JDV1Q-Auto |
|
|
2xSCI, SPI, I²C |
|
2 CAN, J1850, |
PQFP100 |
||
ST92150JDV1T-Auto |
|
|
|
|
|
LIN Master |
LQFP100 |
|
|
|
|
|
|
|
|||
ST92250CV2Q-Auto |
256K |
8K |
|
|
2xSCI, SPI, |
|
CAN, |
PQFP100 |
ST92250CV2T-Auto |
|
|
2xI²C(3) |
|
LIN Master |
LQFP100 |
||
|
|
|
|
|
1)See Table 72 on page 405 for the list of supported part numbers
2)Bytes
3)See Section 12.5 on page 408 for important information
Rev. 1
September 2007 |
1/430 |
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 VOLTAGE REGULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5 ALTERNATE FUNCTIONS FOR I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.6 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3 SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.4 WRITE OPERATION EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.5 PROTECTION STRATEGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.6 FLASH IN-SYSTEM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.2 MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3 ST92124-AUTO/150-AUTO/250-AUTO REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . 74
5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.7 STANDARD INTERRUPTS (CAN AND SCI-A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.8 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.9 DEDICATED ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.10 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.11 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . 113
6 ON-CHIP DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
6.2 |
DMA PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
6.3 |
DMA TRANSACTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
122 |
6.4 |
DMA CYCLE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
6.5 |
SWAP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
2/430
Table of Contents
6.6 DMA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.2 CLOCK CONTROL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.3 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7.5 CRYSTAL OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.6 RESET/STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
8 EXTERNAL MEMORY INTERFACE (EXTMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.2 EXTERNAL MEMORY SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.3 PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.4 INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.5 ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 9.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
10.1 TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.3 EXTENDED FUNCTION TIMER (EFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.4 MULTIFUNCTION TIMER (MFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) . . . . . . . . . . . 212 10.6 ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) . . . . . . . . . . . 237 10.7 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 10.8 I2C BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 10.9 J1850 BYTE LEVEL PROTOCOL DECODER (JBLPD) . . . . . . . . . . . . . . . . . . . . . . . . 284 10.10 CONTROLLER AREA NETWORK (BXCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 10.11 10-BIT ANALOG TO DIGITAL CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 12 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
12.1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 12.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 12.3 VERSION-SPECIFIC SALES CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 12.4 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 12.5 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
13 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
13.1 FLASH ERASE SUSPEND LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 13.2 FLASH CORRUPTION WHEN EXITING STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . 410 13.3 I2C LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 13.4 SCI-A AND CAN INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 13.5 SCI-A MUTE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 13.6 CAN FIFO CORRUPTION WHEN 2 FIFO MESSAGES ARE PENDING . . . . . . . . . . . 415 13.7 MFT DMA MASK BIT RESET WHEN MFT0 DMA PRIORITY LEVEL IS SET TO 0 . . . 420
3/430
Table of Contents
13.8 EMULATION CHIP LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
14 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
4/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
The ST92124-Auto/150-Auto/250-Auto microcontroller is developed and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultrafast context switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The new-generation ST9 MCU devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems.
The advanced Core consists of the Central Processing Unit (CPU), the Register File, the Interrupt and DMA controller, and the Memory Management Unit. The MMU allows a single linear address space of up to 4 Mbytes.
Four independent buses are controlled by the Core: a 22-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit interrupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the core.
This multiple bus architecture makes the ST9 family devices highly efficient for accessing on and offchip memory and fast exchange of data with the on-chip peripherals.
The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges.
The powerful I/O capabilities demanded by microcontroller applications are fulfilled by the ST92150-Auto/124-Auto with 48 (64-pin devices) or 77 (100-pin devices) I/O lines dedicated to digital Input/Output and with 80 I/O lines by the ST92250-Auto. These lines are grouped into up to ten 8-bit I/O Ports and can be configured on a bit basis under software control to provide timing, status signals, an address/data bus for interfacing to the external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel I/O. Two memory spaces are available to support this wide range of configurations: a combined
Program/Data Memory Space and the internal Register File, which includes the control and status registers of the on-chip peripherals.
100-pin devices have a 22-bit external address bus allowing them to address up to 4M bytes of external memory.
Two 16-bit Multifunction Timers, each with an 8 bit Prescaler and 12 operating modes allow simple use for complex waveform generation and measurement, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer.
Two Extended Function Timers provide further timing and signal generation capabilities.
A Standard Timer can be used to generate a stable time base independent from the PLL.
An I2C interface (two in the ST92250-Auto device) provides fast I2C and Access Bus support.
The SPI is a synchronous serial interface for Master and Slave device communication. It supports single master and multimaster systems.
A J1850 Byte Level Protocol Decoder is available (ST92150JDV1-Auto device only) for communicating with a J1850 network.
The bxCAN (basic extended) interface (two in the ST92150JDV1-Auto device) supports 2.0B Active protocol. It has 3 transmit mailboxes, 2 independent receive FIFOs and 8 filters.
In addition, there is an 16 channel Analog to Digital Converter with integral sample and hold, fast conversion time and 10-bit resolution.
There is one Multiprotocol Serial Communications Interface with an integral generator, asynchronous and synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels.
On 100-pin devices, there is an additional asynchronous Serial Communications interface with 13-bit LIN Synch Break generation capability.
Finally, a programmable PLL Clock Generator allows the usage of standard 3 to 5 MHz crystals to obtain a large range of internal frequencies up to 24 MHz. Low power Run (SLOW), Wait For Interrupt, low power Wait For Interrupt, STOP and HALT modes are also available.
5/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 1. ST92124R9-Auto: Architectural Block Diagram
NMI
INT[5:0]
WKUP[13:0]
OSCIN OSCOUT
RESET
CLOCK2/8 INTCLK
CK_AF
STOUT
ICAPA0
OCMPA0
ICAPB0
ICAPA1
OCMPA1
ICAPB1
TINPA0
TOUTA0 TINPB0 TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
VREG
FLASH
64 Kbytes
E3 TM
1 Kbyte
RAM
2 Kbytes
256 bytes Register File
8/16 bits CPU
Interrupt
Management
ST9 CORE
RCCU
ST. TIMER
EF TIMER 0
EF TIMER 1
MF TIMER 0
MF TIMER 1
VOLTAGE REGULATOR
MEMORY BUS
REGISTER BUS
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P0[7:0] |
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P1[2:0] |
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Fully |
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P2[7:0] |
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Prog. |
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P3[7:4] |
I/Os |
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P4[7:4] |
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P5[7:0] |
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P6[5:2,0] |
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P7[7:0] |
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SDA |
I2C BUS |
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SCL |
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WDOUT |
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WATCHDOG |
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HW0SW1 |
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MISO |
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SPI |
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MOSI |
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SCK |
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SS |
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AVDD |
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ADC |
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AVSS |
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AIN[15:8] |
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EXTRG |
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TXCLK |
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RXCLK |
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SIN |
SCI M |
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DCD |
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SOUT |
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CLKOUT |
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RTS |
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6 and Port7.
6/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 2. ST92124V1-Auto: Architectural Block Diagram
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FLASH |
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Ext. MEM. |
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128 Kbytes |
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A[7:0] |
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ADDRESS |
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DATA |
D[7:0] |
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E3 TM |
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Port0 |
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1 Kbyte |
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Ext. MEM. |
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A[10:8] |
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RAM |
BUS |
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ADDRESS |
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A[21:11] |
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Ports |
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AS |
4 Kbytes |
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1,9 |
P0[7:0] |
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MEMORY |
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DS |
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P1[7:3] |
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RW |
256 bytes |
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Fully |
P1[2:0] |
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WAIT |
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Prog. |
P2[7:0] |
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Register File |
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NMI |
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I/Os |
P3[7:4] |
DS2 |
8/16 bits |
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P3[3:1] |
RW |
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P4[7:4] |
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CPU |
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P4[3:0] |
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Interrupt |
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P5[7:0] |
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P6[5:2,0] |
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INT[6:0] |
Management |
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P6.1 |
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WKUP[15:0] |
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ST9 CORE |
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P7[7:0] |
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OSCIN |
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P8[7:0] |
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P9[7:0] |
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OSCOUT |
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RESET |
RCCU |
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I2C BUS |
SDA |
CLOCK2/8 |
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SCL |
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INTCLK |
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CK_AF |
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STOUT |
ST. TIMER |
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BUS |
WATCHDOG |
WDOUT |
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HW0SW1 |
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ICAPA0 |
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REGISTER |
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MISO |
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OCMPA0 |
EF TIMER 0 |
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ICAPB0 |
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SPI |
MOSI |
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OCMPB0 |
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SCK |
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EXTCLK0 |
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SS |
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ICAPA1 |
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AVDD |
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AVSS |
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OCMPA1 |
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EF TIMER 1 |
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ADC |
AIN[15:8] |
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ICAPB1 |
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AIN[7:0] |
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OCMPB1 |
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EXTRG |
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EXTCLK1 |
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TXCLK |
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TINPA0 |
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RXCLK |
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TOUTA0 |
MF TIMER 0 |
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SIN |
TINPB0 |
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SCI M |
DCD |
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TOUTB0 |
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SOUT |
TINPA1 |
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CLKOUT |
TOUTA1 |
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MF TIMER 1 |
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RTS |
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TINPB1 |
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RDI |
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TOUTB1 |
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SCI A |
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TDO |
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VREG |
VOLTAGE |
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REGULATOR |
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The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7, |
|||||
Port8 and Port9. |
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7/430 |
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 3. ST92150C(R/V)1/9-Auto: Architectural Block Diagram
AS
DS
RW
WAIT NMI
DS2
RW*
INT[5:0] INT6*
WKUP[13:0]
WKUP[15:14]*
OSCIN OSCOUT
RESET
CLOCK2/8 INTCLK
CK_AF
STOUT
ICAPA0
OCMPA0
ICAPB0
OCMPB0*
EXTCLK0*
ICAPA1
OCMPA1
ICAPB1
OCMPB1*
EXTCLK1*
TINPA0
TOUTA0 TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
FLASH
128/64 Kbytes
E3 TM
1 Kbyte
RAM
2/4 Kbytes
256 bytes Register File
8/16 bits CPU
Interrupt
Management
ST9 CORE
RCCU
ST. TIMER
EF TIMER 0
EF TIMER 1
MF TIMER 0
MF TIMER 1
VOLTAGE
VREG REGULATOR
* Not available on 64-pin version.
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Ext. MEM. |
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ADDRESS |
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DATA |
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Port0 |
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Ext. MEM. |
BUS |
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ADDRESS |
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Ports |
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MEMORY |
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1,9* |
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Fully |
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Prog. |
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I/Os |
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I2C BUS |
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BUS |
WATCHDOG |
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REGISTER |
SPI |
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ADC |
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SCI M |
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SCI A* |
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CAN_0 |
A[7:0]
D[7:0]
A[10:8]
A[21:11]*
P0[7:0]
P1[7:3]*
P1[2:0]
P2[7:0]
P3[7:4]
P3[3:1]*
P4[7:4]
P4[3:0]*
P5[7:0]
P6[5:2,0]
P6.1*
P7[7:0]
P8[7:0]*
P9[7:0]*
SDA
SCL
WDOUT
HW0SW1
MISO
MOSI
SCK
SS
AVDD
AVSS
AIN[15:8]
AIN[7:0]
EXTRG
TXCLK
RXCLK SIN
DCD
SOUT CLKOUT RTS
RDI TDO
RX0
TX0
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7, Port8* and Port9*.
8/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 4. ST92150JDV1-Auto: Architectural Block Diagram
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FLASH |
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128 Kbytes |
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E3 TM |
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1K byte |
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RAM |
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6 Kbytes |
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AS |
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DS |
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RW |
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256 bytes |
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WAIT |
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Register File |
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NMI |
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DS2 |
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8/16 bit |
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RW |
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CPU |
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INT[6:0] |
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Interrupt |
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Management |
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WKUP[15:0] |
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ST9 CORE |
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OSCIN
OSCOUT
RESET RCCU
CLOCK2/8
CLOCK2
INTCLK
CK_AF
STOUT |
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ST. TIMER |
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
EF TIMER 0
EF TIMER 1
MF TIMER 0
MF TIMER 1
VOLTAGE
VREG REGULATOR
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Ext. MEM. |
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ADDRESS |
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DATA |
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Port0 |
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Ext. MEM. |
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ADDRESS |
BUS |
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Ports 1,9 |
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MEMORY |
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Fully Prog. |
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I/Os |
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J1850 |
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JBLPD |
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I2C BUS |
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WATCHDOG |
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BUS |
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REGISTER |
SPI |
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ADC |
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SCI M |
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SCI A |
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CAN_0 |
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CAN_1 |
A[7:0]
D[7:0]
A[21:8]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:1] P4[7:0] P5[7:0] P6[5:0] P7[7:0] P8[7:0] P9[7:0]
VPWI
VPWO
SDA
SCL
WDOUT
HW0SW1
MISO MOSI SCK
SS
AVDD AVSS
AIN[15:0]
EXTRG
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
RDI
TDO
RX0
TX0
RX1
TX1
The alternate functions (Italic characters) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8 and Port9.
9/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 5. ST92250CV2-Auto: Architectural Block Diagram
FLASH
256 Kbytes
E3 TM
1K byte
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RAM |
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8 Kbytes |
|
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AS |
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|||||
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||||
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DS |
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RW |
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256 bytes |
|
||||
WAIT |
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Register File |
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|||
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|||||
NMI |
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|||||
DS2 |
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8/16 bit |
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|||||
RW |
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CPU |
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|||||
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Interrupt
INT[6:0] Management
WKUP[15:0]
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ST9 CORE |
OSCIN |
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|||
OSCOUT |
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|||
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||||
RESET |
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RCCU |
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CLOCK2/8 |
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CLOCK2 |
|
|||
INTCLK |
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|||
CK_AF |
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|||
STOUT |
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ST. TIMER |
||
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ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
EF TIMER 0
EF TIMER 1
MF TIMER 0
MF TIMER 1
VOLTAGE
VREG REGULATOR
|
|
Ext. MEM. |
|
|
ADDRESS |
|
|
DATA |
|
|
Port0 |
|
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Ext. MEM. |
|
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ADDRESS |
BUS |
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Ports 1,9 |
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MEMORY |
|
Fully Prog. |
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I/Os |
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I2C BUS _0 |
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I2C BUS _1 |
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BUS |
WATCHDOG |
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REGISTER |
SPI |
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ADC |
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SCI M |
|
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SCI A |
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CAN_0 |
A[7:0]
D[7:0]
A[21:8]
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
P4[7:0]
P5[7:0]
P6[7:0]
P7[7:0]
P8[7:0]
P9[7:0]
SDA0 SCL0
SDA1 SCL1
WDOUT
HW0SW1
MISO MOSI SCK
SS
AVDD AVSS
AIN[15:0]
EXTRG
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
RDI
TDO
RX0
TX0
The alternate functions (Italic characters) are mapped on Port0, Port1, Port2, Port3, Port4, Port5, Port6, Port7, Port8 and Port9.
10/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
AS. Address Strobe (output, active low, 3-state). Address Strobe is pulsed low once at the begin- ning of each memory cycle. The rising edge of AS indicates that address, Read/Write (RW), and Data signals are valid for memory transfers.
DS. Data Strobe (output, active low, 3-state). Data Strobe provides the timing for data movement to or from Port 0 for each memory transfer. During a write cycle, data out is valid at the leading edge of DS. During a read cycle, Data In must be valid prior to the trailing edge of DS. When the ST9 accesses on-chip memory, DS is held high during the whole memory cycle.
RESET. Reset (input, active low). The ST9 is initialised by the Reset signal. With the deactivation of RESET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h.
RW. Read/Write (output, 3-state). Read/Write determines the direction of data transfer for external memory transactions. RW is low when writing to external memory, and high for all other transactions.
OSCIN, OSCOUT. Oscillator (input and output). These pins connect a parallel-resonant crystal, or an external source to the on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter; OSCOUT is the output of the oscillator inverter.
HW0SW1. When connected to VDD through a 1K pull-up resistor, the software watchdog option is selected. When connected to VSS through a 1K pull-down resistor, the hardware watchdog option is selected.
VPWO. This pin is the output line of the J1850 peripheral (JBLPD). It is available only on some devices.
RX1/WKUP6. Receive Data input of CAN1 and Wake-up line 6. Available only on some devices. When the CAN1 peripheral is disabled, a pull-up resistor is connected internally to this pin.
TX1. Transmit Data output of CAN1. Available on some devices.
P0[7:0], P1[7:0] or P9[7:2] (Input/Output, TTL or CMOS compatible). 11 lines (64-pin devices) or 22
lines (100-pin devices) providing the external memory interface for addressing 2K or 4M bytes of external memory.
P0[7:0], P1[2:0], P2[7:0], P3[7:4], P4.[7:4], P5[7:0], P6[5:2,0], P7[7:0] I/O Port Lines (Input/ Output, TTL or CMOS compatible). I/O lines grouped into I/O ports of 8 bits, bit programmable under software control as general purpose I/O or as alternate functions.
P1[7:3], P3[3:1], P4[3:0], P6.1, P8[7:0], P9[7:0]
Additional I/O Port Lines available on 100-pin versions only.
P3.0, P6[7:6] Additional I/O Port Lines available on ST92250-Auto version only.
AVDD. Analog VDD of the Analog to Digital Converter (common for ADC 0 and ADC 1).
AVDD can be switched off when the ADC is not in use.
AVSS. Analog VSS of the Analog to Digital Converter (common for ADC 0 and ADC 1).
VDD. Main Power Supply Voltage. Four pins are available on 100-pin versions, two on 64-pin versions. The pins are internally connected.
VSS. Digital Circuit Ground. Four pins are available on 100-pin versions, two on 64-pin versions. The pins are internally connected.
VTEST Power Supply Voltage for Flash test purposes. This pin must be kept to 0 in user mode.
VREG. Stabilization capacitors for the internal voltage regulator. The user must connect external stabilization capacitors to these pins. Refer to Figure 16.
Each pin of the I/O ports of the ST92124-Auto/ 150-Auto/250-Auto may assume software programmable Alternate Functions as shown in Section 1.4.
For unused pins, input mode is not recommended. These pins must be kept at a fixed voltage using the output push pull mode of the I/O or an external pull-up or pull-down resistor.
11/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 6. ST92124R9-Auto: Pin Configuration (Top-view LQFP64)
|
|
|
|
|
|
|
|
|
HW0SW1 |
|
|
RESET OSCOUT |
|
OSCIN V |
V P7.7/AIN15/WKUP13 P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 |
P7.3/AIN11 |
P7.2/AIN10 |
P7.1/AIN9 P7.0/AIN8/CK AF AV |
AV |
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DD |
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DD |
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64 63 62 61 60 59 58 |
57 56 55 54 53 52 51 50 49 |
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N.C |
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WAIT/WKUP5/P5.0 |
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1 |
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48 |
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WKUP6/WDOUT/P5.1 |
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2 |
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47 |
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P6.5/WKUP10/INTCLK |
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SIN/WKUP2/P5.2 |
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3 |
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46 |
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P6.4/NMI |
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WDIN/SOUT/P5.3 |
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4 |
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45 |
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P6.3/INT3/INT5 |
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TXCLK/CLKOUT/P5.4 |
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5 |
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44 |
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P6.2/INT2/INT4 |
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RXCL0/WKUP7/P5.5 |
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6 |
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43 |
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P6.0/INT0/INT1/CLOCK2/8 |
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DCD/WKUP8/P5.6 |
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7 |
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42 |
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P0.7(/AIN7***) |
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WKUP9/RTS/P5.7 |
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8 |
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ST92124R9-Auto |
41 |
|
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P0.6(/AIN6***) |
|||||||||||||||||||||||||||||||
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WKUP4/P4.4 |
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9 |
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40 |
|
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P0.5(/AIN5***) |
|||||||||||||||||||||||||||||||
EXTRG/STOUT/P4.5 |
|
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10 |
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39 |
|
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P0.4(/AIN4***) |
||||||||||
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||||||||||||||
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SDA/P4.6 |
|
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11 |
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38 |
|
|
P0.3(/AIN3***) |
||||||||
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||||||||||||
|
WKUP1/SCL/P4.7 |
|
|
12 |
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37 |
|
|
P0.2(/AIN2***) |
|||||||||
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13 |
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36 |
|
|
P0.1(/AIN1***) |
|||||||
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SS/P3.4 |
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||||||||||
|
|
MISO/P3.5 |
|
|
14 |
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35 |
|
|
P0.0(/AIN0***) |
||||||||
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||||||||||||
|
|
MOSI/P3.6 |
|
|
15 |
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34 |
|
|
Reserved* |
||||||||
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||||||||||||
|
SCK/WKUP0/P3.7 |
|
|
16 |
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33 |
|
|
Reserved* |
|||||||||
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |
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Reserved* |
|
|
TINPA0/P2.0 TINPB0/P2.1 |
|
TOUTA0/P2.2 TOUTB0/P2.3 |
TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 TOUTB1/P2.7 V |
V |
V |
**V (ICAPA0***/OCMPA0***/)P1.0 (ICAPA1***/OCMPA1***/)P1.1 |
(ICAPB1***/ICAPB0***/)P1.2 |
|
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SS |
DD |
REG |
TEST |
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|
*Reserved for ST tests, must be left unconnected
**VTEST must be kept low in standard operating mode
***The ST92F150-EMU2 emulator does not emulate ADC channels from AIN0 to AIN7 and extended function tim-
ers because they are not implemented on the emulator chip. See also Section 13.8 on page 424
12/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 7. ST92124V1-Auto: Pin Configuration (Top-view PQFP100)
A17/P9.3
A18/P9.4
A19/P9.5
A20/P9.6
A21/P9.7
WAIT/WKUP5/P5.0
WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
CLOCK2/P4.1
OCMPA1/P4.2
VSS
VDD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
|
|
P9.2/A16 |
|
|
P9.1/TDO |
|
P9.0/RDI |
|
HW0SW1 |
|
RESET OSCOUT OSCIN V |
V P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 |
P7.5/AIN13/WKUP11 |
P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8/CK AF |
AV |
AV P8.7/AIN7 |
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DD |
SS |
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SS |
DD |
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||
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 |
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|
|
P8.6/AIN6 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 |
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80 |
||||||||||||||
2 |
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79 |
P8.5/AIN5 |
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3 |
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78 |
P8.4/AIN4 |
|||||||||||||
4 |
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77 |
P8.3/AIN3 |
|||||||||||||
5 |
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76 |
P8.2/AIN2 |
|||||||||||||
6 |
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75 |
P8.1/AIN1/WKUP15 |
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7 |
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74 |
P8.0/AIN0/WKUP14 |
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8 |
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73 |
NC |
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9 |
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72 |
P6.5/WKUP10/INTCLK |
|||||||||||||
10 |
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71 |
P6.4/NMI |
|||||||||||||||
11 |
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70 |
P6.3/INT3/INT5 |
|||||||||||||||
12 |
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69 |
P6.2/INT2/INT4/DS2 |
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|||||||||||||||||
13 |
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68 |
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P6.1/INT6/RW |
|
||||||||||||||||
14 |
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67 |
P6.0/INT0/INT1/CLOCK2/8 |
|||||||||||||||
15 |
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ST92124V1-Auto |
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66 |
P0.7/A7/D7 |
||||||||||||||||||||||||||||||||||||||||||||
16 |
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65 |
VDD |
|||||||||||||||||||||||||||||||||||||||||||||
17 |
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64 |
VSS |
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18 |
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63 |
P0.6/A6/D6 |
||||||||||||||||
19 |
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62 |
P0.5/A5/D5 |
|||||||||||||||
20 |
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61 |
P0.4/A4/D4 |
|||||||||||||||
21 |
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60 |
P0.3/A3/D3 |
|||||||||||||||
22 |
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59 |
P0.2/A2/D2 |
|||||||||||||||
23 |
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58 |
P0.1/A1/D1 |
|||||||||||||||
24 |
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57 |
P0.0/A0/D0 |
|||||||||||||||
25 |
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56 |
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AS |
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26 |
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55 |
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DS |
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27 |
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54 |
P1.7/A15 |
|||||||||||||||
28 |
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53 |
P1.6/A14 |
|||||||||||||||
29 |
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52 |
P1.5/A13 |
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30 |
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51 |
P1.4/A12 |
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31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
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||||||||
|
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REG |
|
RW |
TINPA0/P2.0 |
TINPB0/P2.1 |
|
TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 |
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SS |
DD |
REG |
TEST |
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WKUP6 NC |
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||||||||||||||||||||||||||||||||||||||||||||||||||||
|
V |
|
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TOUTA1/P2.6 TOUTB1/P2.7 V |
V |
V |
*V A8/P1.0 A9/P1.1 A10/P1.2 |
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A11/P1.3 |
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* VTEST must be kept low in standard operating mode.
13/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 8. ST92124V1-Auto: Pin Configuration (Top-view LQFP100)
|
|
|
P9.5/A19 |
P9.4/A18 |
P9.3/A17 P9.2/A16 P9.1/TDO |
P9.0/RDI HW0SW1 |
|
RESET OSCOUT OSCIN V |
V |
P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8/CKAF AV |
AV P8.7/AIN7 P8.6/AIN6 P8.5/AIN5 |
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DD |
SS |
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SS |
DD |
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||||||||
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 |
||||||||||||
|
|
A20/P9.6 |
1 |
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A21/P9.7 |
2 |
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WAIT/WKUP5/P5.0 |
3 |
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WKUP6/WDOUT/P5.1 |
4 |
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SIN/WKUP2/P5.2 |
5 |
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WDIN/SOUT/P5.3 |
6 |
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TXCLK/CLKOUT/P5.4 |
7 |
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RXCLK/WKUP7/P5.5 |
8 |
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DCD/WKUP8/P5.6 |
9 |
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WKUP9/RTS/P5.7 |
10 |
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ICAPA1/P4.0 |
11 |
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CLOCK2/P4.1 |
12 |
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ST92124V1-Auto |
|
|||||||
|
OCMPA1/P4.2 |
13 |
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||||||||
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||
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VSS |
14 |
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VDD |
15 |
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ICAPB1/OCMPB1/P4.3 |
16 |
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||
EXTCLK1/WKUP4/P4.4 |
17 |
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EXTRG/STOUT/P4.5 |
18 |
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|
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SDA/P4.6 |
19 |
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WKUP1/SCL/P4.7 |
20 |
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ICAPB0/P3.1 |
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21 |
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ICAPA0/OCMPA0/P3.2 |
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22 |
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|||
|
OCMPB0/P3.3 |
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|
23 |
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||
|
EXTCLK0/SS/P3.4 |
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|
24 |
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||
|
|
MISO/P3.5 |
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25 |
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|
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
||||||||||||
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|
SCK/WKUP0/P3.7 |
REG |
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SS |
DD |
REG TEST |
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||||||
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||||||
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|
MOSI/P3.6 |
V RW TINPA0/P2.0 |
TINPB0/P2.1 TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 |
TOUTB1/P2.7 |
V |
V |
V *V A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 WKUP6 NC A12/P1.4 A13/P1.5 A14/P1.6 |
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14 NC P6.5/WKUP10/INTCLK P6.4/NMI P6.3/INT3/INT5 P6.2/INT2/INT4/DS2 P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
VDD
VSS
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0 AS
DS P1.7/A15
* VTEST must be kept low in standard operating mode.
14/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 9. ST92150-Auto: Pin Configuration (Top-view LQFP64)
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HW0SW1 |
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RESET OSCOUT |
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OSCIN V |
V P7.7/AIN15/WKUP13 P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 |
P7.3/AIN11 |
P7.2/AIN10 |
P7.1/AIN9 |
P7.0/AIN8/CK_AF AV |
AV |
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DD |
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64 63 62 61 60 59 58 |
57 56 55 54 53 52 51 50 49 |
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N.C |
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TX0/WAIT/WKUP5/P5.0 |
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1 |
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48 |
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RX0/WKUP6/WDOUT/P5.1 |
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2 |
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47 |
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P6.5/WKUP10/INTCLK |
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SIN/WKUP2/P5.2 |
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3 |
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46 |
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P6.4/NMI |
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WDIN/SOUT/P5.3 |
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4 |
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45 |
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P6.3/INT3/INT5 |
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TXCLK/CLKOUT/P5.4 |
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5 |
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44 |
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P6.2/INT2/INT4 |
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RXCL0/WKUP7/P5.5 |
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6 |
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43 |
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P6.0/INT0/INT1/CLOCK2/8 |
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DCD/WKUP8/P5.6 |
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7 |
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ST92150-Auto |
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42 |
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P0.7(/AIN7***) |
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WKUP9/RTS/P5.7 |
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8 |
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41 |
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P0.6(/AIN6***) |
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WKUP4/P4.4 |
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9 |
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40 |
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P0.5(/AIN5***) |
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EXTRG/STOUT/P4.5 |
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10 |
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39 |
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P0.4(/AIN4***) |
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SDA/P4.6 |
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11 |
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38 |
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P0.3(/AIN3***) |
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WKUP1/SCL/P4.7 |
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12 |
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37 |
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P0.2(/AIN2***) |
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13 |
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36 |
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P0.1(/AIN1***) |
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SS/P3.4 |
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MISO/P3.5 |
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14 |
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35 |
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P0.0(/AIN0***) |
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MOSI/P3.6 |
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15 |
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34 |
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Reserved* |
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SCK/WKUP0/P3.7 |
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16 |
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33 |
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Reserved* |
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |
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Reserved* |
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TINPA0/P2.0 TINPB0/P2.1 |
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TOUTA0/P2.2 TOUTB0/P2.3 |
TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 TOUTB1/P2.7 V |
V |
V |
**V |
(ICAPA0***/OCMPA0***/)P1.0 (ICAPA1***/OCMPA1***/P1.1 |
(ICAPB1***/ICAPB0***/)P1.2 |
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SS |
DD |
REG |
TEST |
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*Reserved for ST tests, must be left unconnected
**VTEST must be kept low in standard operating mode.
***Not emulated. Refer to Section 13.8 on page 424
15/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 10. ST92150C-Auto: Pin Configuration (Top-view PQFP100)
A17/P9.3
A18/P9.4
A19/P9.5
A20/P9.6
A21/P9.7
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
CLOCK2/P4.1
OCMPA1/P4.2
VSS
VDD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
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P9.2/A16 |
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P9.1/TDO |
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P9.0/RDI |
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HW0SW1 |
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RESET |
OSCOUT OSCIN V |
V P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 |
P7.5/AIN13/WKUP11 |
P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 |
P7.0/AIN8/CK AF AV |
AV P8.7/AIN7 |
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DD |
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 |
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P8.6/AIN6 |
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1 |
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80 |
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2 |
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79 |
P8.5/AIN5 |
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3 |
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78 |
P8.4/AIN4 |
|||||||||||||
4 |
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77 |
P8.3/AIN3 |
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5 |
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76 |
P8.2/AIN2 |
|||||||||||||
6 |
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75 |
P8.1/AIN1/WKUP15 |
|||||||||||||
7 |
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74 |
P8.0/AIN0/WKUP14 |
|||||||||||||
8 |
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73 |
NC |
|||||||||||||
9 |
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72 |
P6.5/WKUP10/INTCLK |
|||||||||||||
10 |
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71 |
P6.4/NMI |
|||||||||||||||
11 |
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70 |
P6.3/INT3/INT5 |
|||||||||||||||
12 |
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69 |
P6.2/INT2/INT4/DS2 |
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|||||||||||||||||
13 |
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68 |
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|||||||||||
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P6.1/INT6/RW |
|
||||||||||||||||
14 |
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67 |
P6.0/INT0/INT1/CLOCK2/8 |
|||||||||||||||
15 |
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ST92150C-Auto |
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66 |
P0.7/A7/D7 |
||||||||||||||||||||||||||||||||||||||||||
16 |
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65 |
VDD |
|||||||||||||||||||||||||||||||||||||||||||
17 |
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64 |
VSS |
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18 |
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63 |
P0.6/A6/D6 |
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19 |
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62 |
P0.5/A5/D5 |
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20 |
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61 |
P0.4/A4/D4 |
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21 |
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60 |
P0.3/A3/D3 |
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22 |
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59 |
P0.2/A2/D2 |
|||||||||||||||
23 |
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58 |
P0.1/A1/D1 |
|||||||||||||||
24 |
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57 |
P0.0/A0/D0 |
|||||||||||||||
25 |
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56 |
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AS |
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26 |
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55 |
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DS |
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27 |
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54 |
P1.7/A15 |
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28 |
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53 |
P1.6/A14 |
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29 |
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52 |
P1.5/A13 |
|||||||||||||||
30 |
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51 |
P1.4/A12 |
|||||||||||||||
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
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||||||
|
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REG |
|
RW |
TINPA0/P2.0 |
TINPB0/P2.1 |
|
TOUTA0/P2.2 |
TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 |
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SS |
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DD |
REG |
TEST |
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WKUP6 NC |
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|
V |
|
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TOUTA1/P2.6 TOUTB1/P2.7 V |
|
V |
V |
*V A8/P1.0 A9/P1.1 |
|
A10/P1.2 A11/P1.3 |
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* VTEST must be kept low in standard operating mode.
16/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 11. ST92150JD-Auto: Pin Configuration (Top-view PQFP100)
A17/P9.3
A18/P9.4
A19/P9.5
A20/P9.6
A21/P9.7
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
CLOCK2/P4.1
OCMPA1/P4.2
VSS
VDD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA/P4.6
WKUP1/SCL/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
|
|
P9.2/A16 |
|
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P9.1/TDO |
|
P9.0/RDI |
|
HW0SW1 |
|
RESET OSCOUT OSCIN V |
V P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 |
P7.5/AIN13/WKUP11 |
P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8/CK AF |
AV |
AV P8.7/AIN7 |
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DD |
SS |
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SS |
DD |
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||
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 |
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|
|
P8.6/AIN6 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 |
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80 |
||||||||||||||
2 |
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79 |
P8.5/AIN5 |
|||||||||||||
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3 |
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78 |
P8.4/AIN4 |
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4 |
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77 |
P8.3/AIN3 |
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5 |
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76 |
P8.2/AIN2 |
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6 |
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75 |
P8.1/AIN1/WKUP15 |
|||||||||||||
7 |
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74 |
P8.0/AIN0/WKUP14 |
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8 |
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73 |
VPWO |
|||||||||||||
9 |
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72 |
P6.5/WKUP10/INTCLK/VPW |
|||||||||||||
10 |
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71 |
P6.4/NMI |
|||||||||||||||
11 |
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70 |
P6.3/INT3/INT5 |
|||||||||||||||
12 |
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69 |
P6.2/INT2/INT4/DS2 |
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|||||||||||||||||
13 |
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68 |
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P6.1/INT6/RW |
|
||||||||||||||||
14 |
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67 |
P6.0/INT0/INT1/CLOCK2/8 |
|||||||||||||||
15 |
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ST92150JD-Auto |
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66 |
P0.7/A7/D7 |
|||||||||||||||||||||||||||||||||||||||||||||
16 |
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65 |
VDD |
||||||||||||||||||||||||||||||||||||||||||||||
17 |
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64 |
VSS |
|||||||||||||||
18 |
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63 |
P0.6/A6/D6 |
||||||||||||||||
19 |
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62 |
P0.5/A5/D5 |
|||||||||||||||
20 |
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61 |
P0.4/A4/D4 |
|||||||||||||||
21 |
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60 |
P0.3/A3/D3 |
|||||||||||||||
22 |
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59 |
P0.2/A2/D2 |
|||||||||||||||
23 |
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58 |
P0.1/A1/D1 |
|||||||||||||||
24 |
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57 |
P0.0/A0/D0 |
|||||||||||||||
25 |
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56 |
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AS |
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26 |
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55 |
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DS |
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27 |
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54 |
P1.7/A15 |
|||||||||||||||
28 |
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53 |
P1.6/A14 |
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29 |
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52 |
P1.5/A13 |
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30 |
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51 |
P1.4/A12 |
|||||||||||||||
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
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||||||||
|
|
REG |
|
RW |
TINPA0/P2.0 |
TINPB0/P2.1 |
|
TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 |
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SS |
DD |
REG |
TEST |
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RX1/WKUP6 TX1 |
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|
V |
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TOUTA1/P2.6 TOUTB1/P2.7 V |
V |
V |
*V A8/P1.0 A9/P1.1 A10/P1.2 |
|
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A11/P1.3 |
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|
* VTEST must be kept low in standard operating mode.
17/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 12. ST92150C-Auto: Pin Configuration (Top-view LQFP100)
|
|
|
P9.5/A19 |
P9.4/A18 |
P9.3/A17 P9.2/A16 P9.1/TDO |
P9.0/RDI |
HW0SW1 |
|
RESET OSCOUT OSCIN V |
V |
P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8/CKAF AV |
AV P8.7/AIN7 P8.6/AIN6 P8.5/AIN5 |
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DD |
SS |
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SS |
DD |
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|||||||||
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|
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 |
|||||||||||||
|
|
A20/P9.6 |
1 |
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A21/P9.7 |
2 |
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TX0/WAIT/WKUP5/P5.0 |
3 |
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RX0/WKUP6/WDOUT/P5.1 |
4 |
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||
|
SIN/WKUP2/P5.2 |
5 |
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WDIN/SOUT/P5.3 |
6 |
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TXCLK/CLKOUT/P5.4 |
7 |
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||
RXCLK/WKUP7/P5.5 |
8 |
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|
DCD/WKUP8/P5.6 |
9 |
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WKUP9/RTS/P5.7 |
10 |
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ICAPA1/P4.0 |
11 |
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|
CLOCK2/P4.1 |
12 |
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|
ST92150C-Auto |
|
|||||||
|
OCMPA1/P4.2 |
13 |
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||||||||
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||
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VSS |
14 |
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VDD |
15 |
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|
ICAPB1/OCMPB1/P4.3 |
16 |
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||
EXTCLK1/WKUP4/P4.4 |
17 |
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EXTRG/STOUT/P4.5 |
18 |
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SDA/P4.6 |
19 |
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WKUP1/SCL/P4.7 |
20 |
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ICAPB0/P3.1 |
21 |
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ICAPA0/OCMPA0/P3.2 |
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22 |
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OCMPB0/P3.3 |
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23 |
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EXTCLK0/SS/P3.4 |
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24 |
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MISO/P3.5 |
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25 |
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
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MOSI/P3.6 |
SCK/WKUP0/P3.7 |
V RW TINPA0/P2.0 |
TINPB0/P2.1 |
TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 |
TOUTB1/P2.7 |
V |
V |
V *V A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 WKUP6 NC A12/P1.4 A13/P1.5 A14/P1.6 |
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REG |
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SS |
DD |
REG TEST |
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75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
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53
52
51
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14 NC P6.5/WKUP10/INTCLK P6.4/NMI P6.3/INT3/INT5 P6.2/INT2/INT4/DS2 P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
VDD
VSS
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0 AS
DS P1.7/A15
* VTEST must be kept low in standard operating mode.
18/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 13. ST92150JD-Auto: Pin Configuration (Top-view LQFP100)
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P9.5/A19 |
P9.4/A18 |
P9.3/A17 P9.2/A16 P9.1/TDO |
P9.0/RDI HW0SW1 |
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RESET OSCOUT OSCIN V |
V |
P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8/CKAF AV |
AV P8.7/AIN7 P8.6/AIN6 P8.5/AIN5 |
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DD |
SS |
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SS |
DD |
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 |
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A20/P9.6 |
1 |
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A21/P9.7 |
2 |
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TX0/WAIT/WKUP5/P5.0 |
3 |
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RX0/WKUP6/WDOUT/P5.1 |
4 |
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SIN/WKUP2/P5.2 |
5 |
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WDIN/SOUT/P5.3 |
6 |
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TXCLK/CLKOUT/P5.4 |
7 |
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RXCLK/WKUP7/P5.5 |
8 |
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DCD/WKUP8/P5.6 |
9 |
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WKUP9/RTS/P5.7 |
10 |
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ICAPA1/P4.0 |
11 |
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CLOCK2/P4.1 |
12 |
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ST92150JD-Auto |
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OCMPA1/P4.2 |
13 |
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VSS |
14 |
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VDD |
15 |
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ICAPB1/OCMPB1/P4.3 |
16 |
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EXTCLK1/WKUP4/P4.4 |
17 |
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EXTRG/STOUT/P4.5 |
18 |
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SDA/P4.6 |
19 |
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WKUP1/SCL/P4.7 |
20 |
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ICAPB0/P3.1 |
21 |
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ICAPA0/OCMPA0/P3.2 |
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22 |
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OCMPB0/P3.3 |
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23 |
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EXTCLK0/SS/P3.4 |
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24 |
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MISO/P3.5 |
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25 |
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
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SCK/WKUP0/P3.7 |
REG |
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SS |
DD |
REG TEST |
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MOSI/P3.6 |
V RW TINPA0/P2.0 |
TINPB0/P2.1 TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 |
TOUTB1/P2.7 |
V |
V |
V *V A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 RX1/WKUP6 TX1 A12/P1.4 A13/P1.5 A14/P1.6 |
* VTEST must be kept low in standard operating mode.
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14 VPWO
P6.5/WKUP10/INTCLK/VPW
P6.4/NMI
P6.3/INT3/INT5 P6.2/INT2/INT4/DS2 P6.1/INT6/RW P6.0/INT0/INT1/CLOCK2/8 P0.7/A7/D7
VDD
VSS
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0 AS
DS P1.7/A15
19/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 14. ST92250-Auto: Pin Configuration (Top-view PQFP100)
SDA1/A17/P9.3
SCL1/A18/P9.4
A19/P9.5
A20/P9.6
A21/P9.7
TX0/WAIT/WKUP5/P5.0
RX0/WKUP6/WDOUT/P5.1
SIN/WKUP2/P5.2
WDIN/SOUT/P5.3
TXCLK/CLKOUT/P5.4
RXCLK/WKUP7/P5.5
DCD/WKUP8/P5.6
WKUP9/RTS/P5.7
ICAPA1/P4.0
CLOCK2/P4.1
OCMPA1/P4.2
VSS
VDD
ICAPB1/OCMPB1/P4.3
EXTCLK1/WKUP4/P4.4
EXTRG/STOUT/P4.5
SDA0/P4.6
WKUP1/SCL0/P4.7
ICAPB0/P3.1
ICAPA0/OCMPA0/P3.2
OCMPB0/P3.3
EXTCLK0/SS/P3.4
MISO/P3.5
MOSI/P3.6
SCK/WKUP0/P3.7
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P9.2/A16 |
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P9.1/TDO |
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P9.0/RDI |
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HW0SW1 |
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RESET |
OSCOUT OSCIN V |
V P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 |
P7.5/AIN13/WKUP11 |
P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 |
P7.0/AIN8/CKAF |
AV |
AV P8.7/AIN7 |
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DD |
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SS |
DD |
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 |
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P8.6/AIN6 |
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1 |
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80 |
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2 |
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79 |
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P8.5/AIN5 |
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3 |
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78 |
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P8.4/AIN4 |
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4 |
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77 |
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P8.3/AIN3 |
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5 |
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76 |
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P8.2/AIN2 |
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6 |
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75 |
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P8.1/AIN1/WKUP15 |
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7 |
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74 |
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P8.0/AIN0/WKUP14 |
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8 |
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73 |
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P3.0 |
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9 |
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72 |
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P6.5/WKUP10/INTCLK |
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10 |
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71 |
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P6.4/NMI |
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11 |
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70 |
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P6.3/INT3/INT5 |
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12 |
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69 |
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P6.2/INT2/INT4/DS2 |
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13 |
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68 |
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P6.1/INT6/RW |
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14 |
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67 |
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P6.0/INT0/INT1/CLOCK2/8 |
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15 |
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ST92250-Auto |
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66 |
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P0.7/A7/D7 |
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16 |
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65 |
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VDD |
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17 |
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64 |
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VSS |
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18 |
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63 |
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P0.6/A6/D6 |
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19 |
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62 |
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P0.5/A5/D5 |
|||||||||||||||
20 |
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61 |
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P0.4/A4/D4 |
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21 |
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60 |
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P0.3/A3/D3 |
|||||||||||||||
22 |
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59 |
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P0.2/A2/D2 |
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23 |
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58 |
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P0.1/A1/D1 |
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24 |
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57 |
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P0.0/A0/D0 |
|||||||||||||||
25 |
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56 |
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AS |
||||||||||||||||||||
26 |
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55 |
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DS |
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27 |
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54 |
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P1.7/A15 |
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28 |
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53 |
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P1.6/A14 |
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29 |
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52 |
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P1.5/A13 |
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30 |
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51 |
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P1.4/A12 |
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|||||||||||||||||||
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
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||||||
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REG |
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|
TINPA0/P2.0 |
TINPB0/P2.1 |
|
TOUTA0/P2.2 |
TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 |
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SS |
DD |
REG |
TEST |
|
A10/P1.2 |
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A11/P1.3 |
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P6.6 P6.7 |
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|||||||||||||||||||||||||||||||||||||||||||||||||||||
|
V |
RW |
|
TOUTA1/P2.6 TOUTB1/P2.7 V |
V |
V |
*V A8/P1.0 A9/P1.1 |
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* VTEST must be kept low in standard operating mode.
20/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Figure 15. ST92250-Auto: Pin Configuration (Top-view LQFP100)
|
|
|
P9.5/A19 |
P9.4/A18/SCL1 |
P9.3/A17/SDA1 P9.2/A16 P9.1/TDO |
P9.0/RDI |
HW0SW1 |
|
RESET OSCOUT OSCIN V |
V |
P7.7/AIN15/7/WKUP13 P7.6/AIN14/WKUP12 P7.5/AIN13/WKUP11 P7.4/AIN12/WKUP3 P7.3/AIN11 P7.2/AIN10 P7.1/AIN9 P7.0/AIN8/CKAF AV |
AV P8.7/AIN7 P8.6/AIN6 P8.5/AIN5 |
||||
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DD |
SS |
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SS |
DD |
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|||||||||
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 |
|||||||||||||
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A20/P9.6 |
1 |
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A21/P9.7 |
2 |
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TX/WAIT/WKUP5/P5.0 |
3 |
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RX/WKUP6/WDOUT/P5.1 |
4 |
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SIN/WKUP2/P5.2 |
5 |
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WDIN/SOUT/P5.3 |
6 |
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TXCLK/CLKOUT/P5.4 |
7 |
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RXCLK/WKUP7/P5.5 |
8 |
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DCD/WKUP8/P5.6 |
9 |
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WKUP9/RTS/P5.7 |
10 |
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ICAPA1/P4.0 |
11 |
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CLOCK2/P4.1 |
12 |
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ST92250-Auto |
|
|||||||
|
OCMPA1/P4.2 |
13 |
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VSS |
14 |
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VDD |
15 |
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ICAPB1/OCMPB1/P4.3 |
16 |
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EXTCLK1/WKUP4/P4.4 |
17 |
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EXTRG/STOUT/P4.5 |
18 |
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SDA0/P4.6 |
19 |
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WKUP1/SCL0/P4.7 |
20 |
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ICAPB0/P3.1 |
21 |
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ICAPA0/OCMPA0/P3.2 |
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22 |
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OCMPB0/P3.3 |
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23 |
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|
EXTCLK0/SS/P3.4 |
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24 |
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MISO/P3.5 |
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25 |
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
|||||||||||||
|
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|
SCK/WKUP0/P3.7 |
REG |
|
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|
SS |
DD |
REG TEST |
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||||||
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MOSI/P3.6 |
V RW TINPA0/P2.0 |
TINPB0/P2.1 |
TOUTA0/P2.2 TOUTB0/P2.3 TINPA1/P2.4 TINPB1/P2.5 TOUTA1/P2.6 |
TOUTB1/P2.7 |
V |
V |
V *V A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 P6.6 P6.7 A12/P1.4 A13/P1.5 A14/P1.6 |
75 |
P8.4/AIN4 |
||
74 |
P8.3/AIN3 |
||
73 |
P8.2/AIN2 |
||
72 |
P8.1/AIN1/WKUP15 |
||
71 |
P8.0/AIN0/WKUP14 |
||
70 |
P3.0 |
||
69 |
P6.5/WKUP10/INTCLK |
||
68 |
P6.4/NMI |
||
67 |
P6.3/INT3/INT5 |
|
|
66 |
P6.2/INT2/INT4/DS2 |
|
|
65 |
P6.1/INT6/RW |
||
64 |
P6.0/INT0/INT1/CLOCK2/8 |
||
63 |
P0.7/A7/D7 |
||
62 |
VDD |
||
61 |
VSS |
||
60 |
P0.6/A6/D6 |
||
59 |
P0.5/A5/D5 |
||
58 |
P0.4/A4/D4 |
||
57 |
P0.3/A3/D3 |
||
56 |
P0.2/A2/D2 |
||
55 |
P0.1/A1/D1 |
||
54 |
P0.0/A0/D0 |
||
53 |
AS |
||
52 |
DS |
||
51 |
P1.7/A15 |
* VTEST must be kept low in standard operating mode.
21/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Table 1. ST92124-Auto/150-Auto/250-Auto Power Supply Pins
Name |
Function |
LQFP64 |
PQFP100 |
LQFP100 |
|
|
|
|
|
|
|
|
|
- |
18 |
15 |
|
|
Main Power Supply Voltage |
|
|
|
|
VDD |
27 |
42 |
39 |
||
|
|
|
|
||
(Pins internally connected) |
- |
65 |
62 |
||
|
|||||
|
|
|
|
|
|
|
|
60 |
93 |
90 |
|
|
|
|
|
|
|
|
|
- |
17 |
14 |
|
|
Digital Circuit Ground |
|
|
|
|
VSS |
26 |
41 |
38 |
||
|
|
|
|
||
(Pins internally connected) |
- |
64 |
61 |
||
|
|||||
|
|
|
|
|
|
|
|
59 |
92 |
89 |
|
|
|
|
|
|
|
AVDD |
Analog Circuit Supply Voltage |
49 |
82 |
79 |
|
AVSS |
Analog Circuit Ground |
50 |
83 |
80 |
|
VTEST |
Must be kept low in standard operating mode |
29 |
44 |
41 |
|
VREG |
Stabilization capacitor(s) for internal voltage regulator |
28 |
31 |
28 |
|
|
|
|
43 |
40 |
Table 2. ST92124-Auto/150-Auto/250-Auto Primary Function Pins
|
Name |
Function |
LQFP64 |
PQFP100 |
LQFP100 |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AS |
|
|
|
|
Address Strobe |
- |
56 |
53 |
|
|
|
DS |
|
|
|
Data Strobe |
- |
55 |
52 |
||
|
|
|
|
|
|
|
|
||||
|
RW |
|
|
Read/Write |
- |
32 |
29 |
||||
|
|
|
|
|
|
||||||
|
OSCIN |
Crystal Oscillator Input |
61 |
94 |
91 |
||||||
|
|
|
|
|
|||||||
OSCOUT |
Crystal Oscillator Output |
62 |
95 |
92 |
|||||||
|
|
|
|
|
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RESET |
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Reset to initialize the Microcontroller |
63 |
96 |
93 |
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HW0SW1 |
Watchdog HW/SW enabling selection |
64 |
97 |
94 |
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VPWO1) |
J1850 JBLPD Output |
- |
73 |
70 |
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RX1/WKUP61) |
CAN1 Receive Data / Wake-up Line 6 |
- |
49 |
46 |
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TX11) |
CAN1 Transmit Data. |
- |
50 |
47 |
Note 1: ST92150JDV1-Auto only
22/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
The internal Voltage Regulator (VR) is used to power the microcontroller starting from the external power supply. The VR comprises a Main voltage regulator and a Low-power regulator.
–The Main voltage regulator generates sufficient current for the microcontroller to operate in any mode. It has a static power consumption (300 µA typ.).
–The separate Low-Power regulator consumes less power is used only when the microcontroller is in Low Power mode. It has a different design from the main VR and generates a lower,
Figure 16. Recommended Connections for VREG
non-stabilized and non-thermally-compensated voltage sufficient for maintaining the data in RAM and the Register File.
For both the Main VR and the Low-Power VR, stabilization is achieved by an external capacitor,
connected to one of the VREG pins. The minimum recommended value is 300 nF, and care must be
taken to minimize distance between the chip and the capacitor. Care should also be taken to limit the serial inductance to less than 60nH.
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PQFP100 |
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LQFP100 |
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QFP64 |
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Pin |
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31 |
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Pin 43 |
28 |
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Pin 40 |
Pin 28 |
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C |
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C |
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C |
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L |
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L |
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C = 300 to 600nF
L = Ferrite bead for EMI protection.
Suggested type: Murata BLM18BE601FH1: (Imp. 600 Ω at 100 MHz).
IMPORTANT: The VREG pin cannot be used to drive external devices.
Figure 17. Minimum Required Connections for VREG
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PQFP100 |
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LQFP100 |
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QFP64 |
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Pin 31 |
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Pin 43 |
Pin 28 |
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Pin 40 |
Pin 28 |
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C |
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C |
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C |
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C = 300 to 600nF
Note: Pin 31 of PQFP100 or pin 28 of LQFP100 can be left unconnnected. A secondary stabilization network can also be connected to these pins.
23/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Port 0, Port 1 and Port 9[7:2] provide the external memory interface. All the ports of the device can be programmed as Input/Output or in Input mode, compatible with TTL or CMOS levels (except where Schmitt Trigger is present). Each bit can be programmed individually (Refer to the I/O ports chapter).
Internal Weak Pull-up
As shown in Table 3, not all input sections implement a Weak Pull-up. This means that the pull-up must be connected externally when the pin is not used or programmed as bidirectional.
TTL/CMOS Input
For all those port bits where no input schmitt trigger is implemented, it is always possible to program the input level as TTL or CMOS compatible by programming the relevant PxC2.n control bit. Refer I/O Ports Chapter to the section titled “Input/ Output Bit Configuration”.
Schmitt Trigger Input
Two different kinds of Schmitt Trigger circuitries are implemented: Standard and High Hysteresis. Standard Schmitt Trigger is widely used (see Ta-
Table 3. I/O Port Characteristics
ble 3), while the High Hysteresis Schmitt Trigger is present on ports P4[7:6] and P6[5:4].
All inputs which can be used for detecting interrupt events have been configured with a “Standard” Schmitt Trigger, apart from the NMI pin which implements the “High Hysteresis” version. In this way, all interrupt lines are guaranteed as “edge sensitive”.
Push-Pull/OD Output
The output buffer can be programmed as pushpull or open-drain: attention must be paid to the fact that the open-drain option corresponds only to a disabling of P-channel MOS transistor of the buffer itself: it is still present and physically connected to the pin. Consequently it is not possible to increase the output voltage on the pin over VDD+0.3 Volt, to avoid direct junction biasing.
Pure Open-Drain Output
The user can increase the voltage on an I/O pin over VDD+0.3 Volt where the P-channel MOS transistor is physically absent: this is allowed on all “Pure Open Drain” pins. In this case, the push-pull option is not available and any weak pull-up must be implemented externally.
|
Input |
Output |
Weak Pull-Up |
Reset State |
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Port 0[7:0] |
TTL/CMOS |
Push-Pull/OD |
No |
Bidirectional |
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Port 1[7:3] |
TTL/CMOS |
Push-Pull/OD |
Yes |
Bidirectional WPU |
Port 1[2:0] |
TTL/CMOS |
Push-Pull/OD |
No |
Bidirectional |
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Port 2[1:0] |
Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
Port 2[3:2] |
TTL/CMOS |
Pure OD |
No |
Input CMOS |
Port 2[5:4] |
Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
Port 2[7:6] |
TTL/CMOS |
Push-Pull/OD |
Yes |
Input CMOS |
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Port 3[2:0] 1) |
Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
Port 3.3 |
TTL/CMOS |
Push-Pull/OD |
Yes |
Input CMOS |
Port 3[7:4] |
Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
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Port 4.0, Port 4.4 |
Schmitt trigger |
Push-Pull/OD |
No |
Input |
Port 4.1 |
Schmitt trigger |
Push-Pull/OD |
Yes |
Bidirectional WPU |
Port 4.2, Port 4.5 |
TTL/CMOS |
Push-Pull/OD |
Yes |
Input CMOS |
Port 4.3 |
Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
Port 4[7:6] |
High hysteresis Schmitt trigger |
Pure OD |
No |
Input |
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Port 5[2:0], Port 5[7:4] |
Schmitt trigger |
Push-Pull/OD |
No |
Input |
Port 5.3 |
TTL/CMOS |
Push-Pull/OD |
Yes |
Input CMOS |
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Port 6[3:0] |
Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
Port 6[5:4] |
High hysteresis Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
Port 6[7:6] 1) |
Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
Port 7[7:0] |
Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
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Port 8[1:0] |
Schmitt trigger |
Push-Pull/OD |
Yes |
Input |
Port 8[7:2] |
Schmitt trigger |
Push-Pull/OD |
Yes |
Bidirectional WPU |
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Port 9[7:0] |
Schmitt trigger |
Push-Pull/OD |
Yes |
Bidirectional WPU |
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Legend: WPU = Weak Pull-Up, OD = Open Drain.
24/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Note 1: Port 3.0 and Port6 [7:6] present on ST92250-Auto version only.
How to Configure the I/O Ports
To configure the I/O ports, use the information in Table 3, Table 4 and the Port Bit Configuration Table in the I/O Ports Chapter (See page 153).
Input Note = the hardware characteristics fixed for each port line in Table 3.
–If Input note = TTL/CMOS, either TTL or CMOS input level can be selected by software.
–If Input note = Schmitt trigger, selecting CMOS or TTL input by software has no effect, the input will always be Schmitt Trigger.
Alternate Functions (AF) = More than one AF cannot be assigned to an I/O pin at the same time:
An alternate function can be selected as follows.
AF Inputs:
– AF is selected implicitly by enabling the corresponding peripheral. Exception to this are ADC inputs which must be explicitly selected as AF input by software.
AF Outputs or Bidirectional Lines:
– In the case of Outputs or I/Os, AF is selected explicitly by software.
Example 1: SCI-M input
AF: SIN, Port: P5.2. Schmitt Trigger input.
Write the port configuration bits:
P5C2.2=1
P5C1.2=0
P5C0.2 =1
Enable the SCI peripheral by software as described in the SCI chapter.
Example 2: SCI-M output
AF: SOUT, Port: P5.3, Push-Pull/OD output.
Write the port configuration bits (for AF OUT PP):
P5C2.3=0
P5C1.3=1
P5C0.3 =1
Example 3: External Memory I/O
AF: A0/D0, Port : P0.0, Input Note: TTL/CMOS input.
Write the port configuration bits:
P0C2.0=1
P0C1.0=1
P0C0.0 =1
Example 4: Analog input
AF: AIN8, Port : 7.0, Analog input.
Write the port configuration bits:
P7C2.0=1
P7C1.0=1
P7C0.0 =1
25/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
All the ports in the following table are useable for general purpose I/O (input, output or bidirectional).
Table 4. I/O Port Alternate Functions
Port |
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Pin No. |
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Alternate Functions |
|
Name |
LQFP64 |
PQFP100 |
LQFP100 |
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P0.0 |
- |
57 |
54 |
A0/D0 |
I/O |
Address/Data bit 0 |
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35 |
- |
- |
AIN01) |
I |
Analog Data Input 0 |
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P0.1 |
- |
58 |
55 |
A1/D1 |
I/O |
Address/Data bit 1 |
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36 |
- |
- |
AIN11) |
I |
Analog Data Input 1 |
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P0.2 |
- |
59 |
56 |
A2/D2 |
I/O |
Address/Data bit 2 |
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37 |
- |
- |
AIN21) |
I |
Analog Data Input 2 |
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P0.3 |
- |
60 |
57 |
A3/D3 |
I/O |
Address/Data bit 3 |
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38 |
- |
- |
AIN31) |
I |
Analog Data Input 3 |
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P0.4 |
- |
61 |
58 |
A4/D4 |
I/O |
Address/Data bit 4 |
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39 |
- |
- |
AIN41) |
I |
Analog Data Input 4 |
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P0.5 |
- |
62 |
59 |
A5/D5 |
I/O |
Address/Data bit 5 |
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40 |
- |
- |
AIN51) |
I |
Analog Data Input 5 |
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P0.6 |
- |
63 |
60 |
A6/D6 |
I/O |
Address/Data bit 6 |
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41 |
- |
- |
AIN61) |
I |
Analog Data Input 6 |
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P0.7 |
- |
66 |
63 |
A7/D7 |
I/O |
Address/Data bit 7 |
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42 |
- |
- |
AIN71) |
I |
Analog Data Input 7 |
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- |
45 |
42 |
A8 |
I/O |
Address bit 8 |
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P1.0 |
30 |
- |
- |
ICAPA01) |
I |
Ext. Timer 0 - Input Capture A |
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OCMPA01) |
O |
Ext. Timer 0 - Output Compare A |
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- |
46 |
43 |
A9 |
I/O |
Address bit 9 |
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P1.1 |
31 |
- |
- |
ICAPA11) |
I |
Ext. Timer 1- Input Capture A |
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OCMPA11) |
O |
Ext. Timer 1- Output Compare A |
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- |
47 |
44 |
A10 |
I/O |
Address bit 10 |
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P1.2 |
32 |
- |
- |
ICAPB11) |
I |
Ext. Timer 1- Input Capture B |
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ICAPB01) |
I |
Ext. Timer 0- Input Capture B |
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P1.3 |
- |
48 |
45 |
A11 |
I/O |
Address bit 11 |
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P1.4 |
- |
51 |
48 |
A12 |
I/O |
Address bit 12 |
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P1.5 |
- |
52 |
49 |
A13 |
I/O |
Address bit 13 |
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P1.6 |
- |
53 |
50 |
A14 |
I/O |
Address bit 14 |
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P1.7 |
- |
54 |
51 |
A15 |
I/O |
Address bit 15 |
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P2.0 |
18 |
33 |
30 |
TINPA0 |
I |
Multifunction Timer 0 - Input A |
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P2.1 |
19 |
34 |
31 |
TINPB0 |
I |
Multifunction Timer 0 - Input B |
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P2.2 |
20 |
35 |
32 |
TOUTA0 |
O |
Multifunction Timer 0 - Output A |
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P2.3 |
21 |
36 |
33 |
TOUTB0 |
O |
Multifunction Timer 0 - Output B |
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P2.4 |
22 |
37 |
34 |
TINPA1 |
I |
Multifunction Timer 1 - Input A |
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26/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Port |
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Pin No. |
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Alternate Functions |
Name |
LQFP64 |
PQFP100 |
LQFP100 |
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P2.5 |
23 |
38 |
35 |
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TINPB1 |
I |
Multifunction Timer 1 - Input B |
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P2.6 |
24 |
39 |
36 |
|
TOUTA1 |
O |
Multifunction Timer 1 - Output A |
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P2.7 |
25 |
40 |
37 |
|
TOUTB1 |
O |
Multifunction Timer 1 - Output B |
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P3.0 2) |
- |
73 |
70 |
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P3.1 |
- |
24 |
21 |
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ICAPB0 |
I |
Ext. Timer 0 - Input Capture B |
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P3.2 |
- |
25 |
22 |
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ICAPA0 |
I |
Ext. Timer 0 - Input Capture A |
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OCMPA0 |
O |
Ext. Timer 0 - Output Compare A |
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P3.3 |
- |
26 |
23 |
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OCMPB0 |
O |
Ext. Timer 0 - Output Compare B |
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P3.4 |
- |
27 |
24 |
|
EXTCLK0 |
I |
Ext. Timer 0 - Input Clock |
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SS |
I |
SPI - Slave Select |
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P3.5 |
14 |
28 |
25 |
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MISO |
I/O |
SPI - Master Input/Slave Output Data |
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P3.6 |
15 |
29 |
26 |
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MOSI |
I/O |
SPI - Master Output/Slave Input Data |
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SCK |
I |
SPI - Serial Input Clock |
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P3.7 |
16 |
30 |
27 |
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WKUP0 |
I |
Wake-up Line 0 |
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SCK |
O |
SPI - Serial Output Clock |
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P4.0 |
- |
14 |
11 |
|
ICAPA1 |
I |
Ext. Timer 1 - Input Capture A |
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P4.1 |
- |
15 |
12 |
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CLOCK2 |
O |
CLOCK2 internal signal |
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P4.2 |
- |
16 |
13 |
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OCMPA1 |
O |
Ext. Timer 1 - Output Compare A |
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P4.3 |
- |
19 |
16 |
|
ICAPB1 |
I |
Ext. Timer 1 - Input Capture B |
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OCMPB1 |
O |
Ext. Timer 1 - Output Compare B |
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P4.4 |
- |
20 |
17 |
|
EXTCLK1 |
I |
Ext. Timer 1 - Input Clock |
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WKUP4 |
I |
Wake-up Line 4 |
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P4.5 |
10 |
21 |
18 |
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EXTRG |
I |
ADC Ext. Trigger |
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STOUT |
O |
Standard Timer Output |
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P4.6 |
11 |
22 |
19 |
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SDA0 |
I/O |
I2C 0 Data |
|
P4.7 |
12 |
23 |
20 |
|
WKUP1 |
I |
Wake-up Line 1 |
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||||
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SCL0 |
I/O |
I2C 0 Clock |
|||||
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||||
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|
I |
External Wait Request |
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WAIT |
|||
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P5.0 |
1 |
6 |
3 |
|
WKUP5 |
I |
Wake-up Line 5 |
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TX0 2) |
O |
CAN 0 output |
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WKUP6 |
I |
Wake-up Line 6 |
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P5.1 |
2 |
7 |
4 |
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RX0 2) |
I |
CAN 0 input |
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WDOUT |
O |
Watchdog Timer Output |
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P5.2 |
3 |
8 |
5 |
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SIN0 |
I |
SCI-M - Serial Data Input |
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WKUP2 |
I |
Wake-up Line 2 |
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P5.3 |
4 |
9 |
6 |
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WDIN |
I |
Watchdog Timer Input |
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SOUT |
O |
SCI-M - Serial Data Output |
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27/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Port |
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Pin No. |
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Alternate Functions |
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Name |
LQFP64 |
PQFP100 |
LQFP100 |
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P5.4 |
5 |
10 |
7 |
TXCLK |
I |
SCI-M - Transmit Clock Input |
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CLKOUT |
O |
SCI-M - Clock Output |
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P5.5 |
6 |
11 |
8 |
RXCLK |
I |
SCI-M - Receive Clock Input |
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WKUP7 |
I |
Wake-up Line 7 |
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P5.6 |
7 |
12 |
9 |
DCD |
I |
SCI-M - Data Carrier Detect |
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WKUP8 |
I |
Wake-up Line 8 |
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P5.7 |
8 |
13 |
10 |
WKUP9 |
I |
Wake-up Line 9 |
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RTS |
O |
SCI-M - Request To Send |
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INT0 |
I |
External Interrupt 0 |
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P6.0 |
43 |
67 |
64 |
INT1 |
I |
External Interrupt 1 |
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CLOCK2/8 |
O |
CLOCK2 divided by 8 |
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P6.1 |
- |
68 |
65 |
INT6 |
I |
External Interrupt 6 |
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O |
Read/Write |
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RW |
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INT2 |
I |
External Interrupt 2 |
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P6.2 |
44 |
69 |
66 |
INT4 |
I |
External Interrupt 4 |
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DS2 |
O |
Data Strobe 2 |
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P6.3 |
45 |
70 |
67 |
INT3 |
I |
External Interrupt 3 |
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INT5 |
I |
External Interrupt 5 |
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P6.4 |
46 |
71 |
68 |
NMI |
I |
Non Maskable Interrupt |
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WKUP10 |
I |
Wake-up Line 10 |
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P6.5 |
47 |
72 |
69 |
VPWI2) |
I |
JBLPD input |
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INTCLK |
O |
Internal Main Clock |
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P6.62) |
- |
49 |
46 |
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P6.72) |
- |
50 |
47 |
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P7.0 |
51 |
84 |
81 |
AIN8 |
I |
Analog Data Input 8 |
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CK_AF |
I |
Clock Alternative Source |
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P7.1 |
52 |
85 |
82 |
AIN9 |
I |
Analog Data Input 9 |
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P7.2 |
53 |
86 |
83 |
AIN10 |
I |
Analog Data Input 10 |
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P7.3 |
54 |
87 |
84 |
AIN11 |
I |
Analog Data Input 11 |
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P7.4 |
55 |
88 |
85 |
WKUP3 |
I |
Wake-up Line 3 |
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AIN12 |
I |
Analog Data Input 12 |
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P7.5 |
56 |
89 |
86 |
AIN13 |
I |
Analog Data Input 13 |
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WKUP11 |
I |
Wake-up Line 11 |
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P7.6 |
57 |
90 |
87 |
AIN14 |
I |
Analog Data Input14 |
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WKUP12 |
I |
Wake-up Line 12 |
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P7.7 |
58 |
91 |
88 |
AIN15 |
I |
Analog Data Input 15 |
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WKUP13 |
I |
Wake-up Line 13 |
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28/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Port |
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Pin No. |
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Alternate Functions |
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Name |
LQFP64 |
PQFP100 |
LQFP100 |
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P8.0 |
- |
74 |
71 |
AIN0 |
I |
Analog Data Input 0 |
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WKUP14 |
I |
Wake-up Line 14 |
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P8.1 |
- |
75 |
72 |
AIN1 |
I |
Analog Data Input 1 |
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WKUP15 |
I |
Wake-up Line 15 |
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P8.2 |
- |
76 |
73 |
AIN2 |
I |
Analog Data Input 2 |
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P8.3 |
- |
77 |
74 |
AIN3 |
I |
Analog Data Input 3 |
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P8.4 |
- |
78 |
75 |
AIN4 |
I |
Analog Data Input 4 |
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P8.5 |
- |
79 |
76 |
AIN5 |
I |
Analog Data Input 5 |
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P8.6 |
- |
80 |
77 |
AIN6 |
I |
Analog Data Input 6 |
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P8.7 |
- |
81 |
78 |
AIN7 |
I |
Analog Data Input 7 |
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P9.0 |
- |
98 |
95 |
RDI2) |
I |
SCI-A Receive Data Input |
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P9.1 |
- |
99 |
96 |
TDO2) |
O |
SCI-A Transmit Data Output |
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P9.2 |
- |
100 |
97 |
A16 |
O |
Address bit 16 |
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P9.3 |
- |
1 |
98 |
A17 3) |
O |
Address bit 17 |
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SDA12) |
I/O |
I²C 1 Data |
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P9.4 |
- |
2 |
99 |
A18 3) |
O |
Address bit 18 |
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SCL12) |
I/O |
I²C 1 Clock |
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P9.5 |
- |
3 |
100 |
A19 |
O |
Address bit 19 |
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P9.6 |
- |
4 |
1 |
A20 |
O |
Address bit 20 |
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P9.7 |
- |
5 |
2 |
A21 |
O |
Address bit 21 |
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Note1: The ST92F150-EMU2 emulator does not emulate ADC channels from AIN0 to AIN7 and extended function timers because they are not implemented on the emulator chip. See also Section 13.8 on page 424.
Note 2: Available on some devices only
Note 3: For the ST92250-Auto device, since A[18:17] share the same pins as SDA1 and SCL1 of I²C_1, these address bits are not available when the I²C_1 is in use (when I2CCR.PE bit is set).
29/430
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
To optimize the performance versus the power consumption of the device, the ST92124-Auto/ 150-Auto/250-Auto supports different operating modes that can be dynamically selected depending on the performance and functionality requirements of the application at a given moment.
RUN MODE: This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU).
SLOW MODE: Power consumption can be significantly reduced by running the CPU and the peripherals at reduced clock speed using the CPU Prescaler and CCU Clock Divider.
WAIT FOR INTERRUPT MODE: The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral and interrupt controller keep running at a frequency depending on the CCU programming.
LOW POWER WAIT FOR INTERRUPT MODE: Combining SLOW mode and Wait For Interrupt mode it is possible to reduce the power consumption by more than 80%.
STOP MODE: When the STOP is requested by executing the STOP bit writing sequence (see dedicated section on Wake-up Management Unit paragraph), and if NMI is kept low, the CPU and the peripherals stop operating. Operations resume after a wake-up line is activated (16 wake-up lines plus NMI pin). See the RCCU and Wake-up Man-
agement Unit paragraphs in the following for the details. The difference with the HALT mode consists in the way the CPU exits this state: when the STOP is executed, the status of the registers is recorded, and when the system exits from the STOP mode the CPU continues the execution with the same status, without a system reset.
When the MCU enters STOP mode the Watchdog stops counting. After the MCU exits from STOP mode, the Watchdog resumes counting from where it left off.
When the MCU exits from STOP mode, the oscillator, which was sleeping too, requires about 5 ms to restart working properly (at a 4 MHz oscillator frequency). An internal counter is present to guarantee that all operations after exiting STOP Mode, take place with the clock stabilised.
The counter is active only when the oscillation has already taken place. This means that 1-2 ms must be added to take into account the first phase of the oscillator restart.
In STOP mode, the oscillator is stopped. Therefore, if the PLL is used to provide the CPU clock before entering STOP mode, it will have to be selected again when the MCU exits STOP mode.
HALT MODE: When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt mode.
30/430