ST8024L
Smartcard interface
Datasheet − production data
Features
■ Designed to be compatible with the NDS
conditional access system (except
ST8024LTR)
■ ISO 7816, GSM11.11 and EMV 4.2 (payment
systems) compatible
■ IC card interface
■ 3 V or 5 V supply for the ST8024L device (V
■ Three specifically protected half-duplex
bi-directional buffered I/O lines to card contacts
C4, C7 and C8
■ Step-up converter for V
generation
CC
separately powered by a 5 V ± 20% supply
(V
and PGND)
DDP
■ 1.8 V ± 6.5%, 3 V or 5 V ± 5% regulated card
supply voltage (V
) with appropriate
CC
DD
)
■ Enhanced ESD protection on card side (>6 kV)
■ 26 MHz integrated crystal oscillator
■ Built-in debounce on card presence contacts
■ One multiplexed status signal OFF
■ Non-inverted control of RST via pin RSTIN
■ Clock generation for cards up to 20 MHz
decoupling has the following capabilities:
–I
< 80 mA at V
CC
– Handles current spikes of 40 nA up
= 4.75 to 6.5 V
DDP
■ Supply supervisor for spike-killing during
to 20 MHz
– Controls rise and fall times
– Filtered overload detection at ~120 mA
■ Thermal and short-circuit protection on all card
contacts
■ Automatic activation and deactivation
sequences; initiated by software or by
hardware in the event of a short-circuit, card
take-off, overheating, V
DD
or V
DDP
dropout
Table 1. Device summary
Order code
ST8024LCDR
ST8024LCTR
ST8024LACDR
PORADJ/
1.8 V function
(1)
(1)
PORADJ –25 to 85 °C SO-28 (tape and reel) 1000 parts per reel ST8024LC
PORADJ –25 to 85 °C TSSOP-28 (tape and reel) 2500 parts per reel ST8024LC
(1)
1.8 V –25 to 85 °C SO-28 (tape and reel) 1000 parts per reel ST8024LAC
ST8024LTR 1.8 V –25 to 85 °C TSSOP-20 (tape and reel) 2500 parts per reel ST8024L
ST8024LACTR
1. Certified by NDS.
(1)
1.8 V –25 to 85 °C TSSOP-28 (tape and reel) 2500 parts per reel ST8024LAC
Temperature
range
Applications
■ Smartcard readers for set-top boxes
■ IC card readers for banking
■ Identification, pay TV
SO-28
TSSOP-20
TSSOP-28
(divided by 1, 2, 4 or 8 through CLKDIV1 and
CLKDIV2 signals) with synchronous frequency
changes
power-on and power-off and power-on reset
(threshold fixed internally or externally by
a resistor divider)
Package Packaging
Package
top mark
May 2012 Doc ID 17709 Rev 5 1/35
This is information on a product in full production.
www.st.com
1
Contents ST8024L
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2.1 Without external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2.2 With an external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2.3 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3 Clock circuitry (only on SO-28 and TSSOP-28 packages) . . . . . . . . . . . . 20
6.4 I/O transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.6 Activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.7 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.8 Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.9 V
6.10 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.11 V
generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CC
selection settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CC
7 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/35 Doc ID 17709 Rev 5
ST8024L List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Electrical characteristics over recommended operating condition . . . . . . . . . . . . . . . . . . . 10
Table 7. Step-up converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Card supply voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Crystal connection (pins XTAL1 and XTAL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC, and AUX2UC) . . . . . . . . . . . . . . . . . 12
Table 11. Data lines to card reader (pins I/O, AUX1, and AUX2 with integrated 11 kΩ
pull-up resistor to V
Table 12. Data lines to microcontroller (pins I/OUC, AUX1UC, and AUX2UC with integrated
11 kΩ pull-up resistor to V
Table 13. Internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 14. Reset output to card reader (pin RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 15. Clock output to card reader (pin CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 16. Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC
and PORADJ/1.8V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 17. Card presence inputs (pins PRES and PRES
Table 18. Interrupt output (pin OFF NMOS drain with integrated 20 kΩ pull-up resistor to V
Table 19. Protection and limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 20. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 21. Clock frequency selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 22. Card presence indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 23. V
selection settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CC
Table 24. SO-28 small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 25. TSSOP-20 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 26. TSSOP-28 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 27. SO-28 tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 28. TSSOP-20 tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 29. TSSOP-28 tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 30. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DD
, RSTIN, 5V/3V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
) . . . . 16
DD
Doc ID 17709 Rev 5 3/35
List of figures ST8024L
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Definition of output and input transition times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. Activation sequence using RSTIN and CMDVCC
Figure 6. Activation sequence at t
Figure 7. Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Behavior of OFF
Figure 9. Emergency deactivation sequence (card extraction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. SO-28 small outline, package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. TSSOP-20 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. TSSOP-28 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14. SO-28 tape and reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. TSSOP-20 tape and reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. TSSOP-28 tape and reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
, CMDVCC, PRES, and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4/35 Doc ID 17709 Rev 5
ST8024L Description
1 Description
The ST8024L is a complete low-cost analog interface for asynchronous Class A, B, and C
smartcards. It can be placed between the card and the microcontroller with few external
components to perform all supply protection and control functions. The ST8024LCDR and
ST8024LCTR are compatible with the ST8024 (with the exception of V
th(ext)rise/fall
value).
Doc ID 17709 Rev 5 5/35
Diagram ST8024L
2 Diagram
Figure 1. Block diagram
6
6
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1. To be used with the PORADJ pin if needed.
2. Not available in the TSSOP-20L package.
3. ST8024LCDR, ST8024LCTR.
4. ST8024LACDR, ST8024LACTR, ST8024LTR.
6/35 Doc ID 17709 Rev 5
#36
ST8024L Pin configuration
3 Pin configuration
Figure 2. Pin connections
Table 2. Pin description
Symbol Name and function
CLKDIV1
CLKDIV2
Control of CLK frequency
(internal 11 kΩ
pull-up resistor connected to VDD)
Control of CLK frequency
(internal 11 kΩ
pull-down resistor connected to GND)
SO-28/
TSSOP-28
1N. A.
2N. A.
5 V or 3 V VCC selection for communication with the smartcard. Logic high
5V/3V
selects 5 V operation and logic low selects 3 V operation (for ST8024LACDR,
ST8024LACTR, and ST8024LTR: if the 1.8V pin is logic high, the 5V/3
a “don't care”). See Ta bl e 2 3 for a description of the V
selection settings.
CC
V pin is
31
PGND Power ground for step-up converter 4 2
C1+ External capacitor step-up converter 5 3
V
DDP
Power supply for step-up converter 6 4
C1– External capacitor step-up converter 7 5
V
PRES
Output of step-up converter 8 6
UP
Card presence input (active low) - bonding option 9 N. A.
PRES Card presence input (active high) 10 7
I/O
Data line to and from card (C7)
(internal 11 kΩ
pull-up resistor connected to VCC)
11 8
TSSOP-20
Doc ID 17709 Rev 5 7/35
Pin configuration ST8024L
Table 2. Pin description (continued)
Symbol Name and function
AUX2
Auxiliary line to and from card (C8)
(internal 11 kΩ
pull-up resistor connected to VCC)
AUX1 Auxiliary line to and from card (C4) (internal 11 kΩ pull-up resistor to V
)13N. A
CC
SO-28/
TSSOP-28
12 N. A.
TSSOP-20
CGND Ground for card signal (C5) 14 9
CLK Clock to card (C3) 15 10
RST Card reset (C2) 16 11
V
Supply voltage for the card (C1) 17 12
CC
PORADJ Power-on reset threshold adjustment input (ST8024LCDR, ST8024LCTR)
operation selection. Logic high selects 1.8 V operation and
CC
V pin. With an internal 11 kΩ pull-down
18
1.8V
1.8 V V
overrides any setting on the 5V/3
resistor to GND. (ST8024LACDR, ST8024LACTR and ST8024LTR)
CMDVCC
Start activation sequence input (active low) 19 14
RSTIN Card reset input from MCU 20 15
V
Supply voltage 21 16
DD
GND Ground 22 17
OFF
Interrupt to MCU (active low) 23 18
XTAL1 Crystal or external clock input 24 19
N. A.
13
XTAL2 Crystal connection (leave this pin open if external clock is used) 25 N.A
I/OUC MCU data I/O line (internal 11 kΩ
AUX1UC Non-inverting receiver input (internal 11 kΩ
AUX2UC Non-inverting receiver input (internal 11 kΩ
pull-up resistor connected to VDD)2620
pull-up resistor connected to VDD)27 N. A.
pull-up resistor connected to VDD)28 N. A.
8/35 Doc ID 17709 Rev 5
ST8024L Maximum ratings
4 Maximum ratings
Table 3. Absolute maximum ratings
(1)
Symbol Parameter Min. Max. Unit
V
DD, VDDP
Supply voltage -0.3 7 V
Voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC, AUX1UC,
V
I/OUC, CLKDIV1, CLKDIV2, PORADJ/1.8V, CMDVCC
n1
, PRES,
-0.3 VDD + 0.3 V
PRES, and OFF
V
V
ESD1 MIL-STD-883 class 3 on card contact pins, PRES
ESD2 MIL-STD-883 class 2 on µC contact pins and RSTIN
T
J(MAX)
T
STG
1. Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under
these conditions is not implied.
2. All card contacts are protected against any short with any other card contact.
3. Method 3015 (HBM, 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground.
Table 4. Thermal data
Symbol Parameter Condition SO-28
Voltage on card contact pins I/O, RST, AUX1, AUX2, and CLK -0.3 VCC + 0.3 V
n2
Voltage on pins VUP, C1+, and C1– 7 V
n3
and PRES
(2), (3)
(2), (3)
-6 6 kV
-2 2 kV
Maximum operating junction temperature 150 °C
Storage temperature range -40 150 °C
TSSOP-20
TSSOP-28
Unit
R
thJA
Table 5. Recommended operating conditions
Thermal resistance junction-ambient
temperature
Multilayer test board
(JEDEC standard)
56 50 °C/W
Symbol Parameter Test conditions Min. Typ. Max. Unit
T
Temperature range –25 85 °C
A
Doc ID 17709 Rev 5 9/35
Electrical characteristics ST8024L
5 Electrical characteristics
Table 6. Electrical characteristics over recommended operating condition
Symbol Parameter
V
DD
V
DDP
(1)
Test conditions Min. Typ. Max. Unit
Supply voltage 2.7 6.5 V
V
= 5 V; |ICC| < 80 mA 4.0 5 6.5
CC
V
= 3 V; |ICC| < 65 mA 4.0 5 6.5
Supply voltage for the
step-up converter
CC
V
= 5 V; |ICC| < 20 mA 3.0 6.5
CC
V
= 3 V; |ICC| < 20 mA 2.7 6.5
CC
= 1.8 V; |ICC| < 20 mA 2.7 6.5
V
CC
Card inactive 1.2
I
DD
Supply current
Card active; f
CLK
= f
; CL = 30 pF 1.5
XTAL
Inactive mode 0.1
I
DDP
V
th2
V
HYS2
V
th(ext)rise
V
th(ext)fall
V
HYS(ext)
Step-up converter supply
current
Falling threshold voltage
on V
DD
Hysteresis of threshold
voltage V
th2
External rising threshold
voltage at pin PORADJ
External falling threshold
voltage at pin PORADJ
Hysteresis of threshold
voltage V
th(ext)
Active mode; f
| = 0
|I
CC
V
= 5 V; |ICC| = 80 mA 50 200
CC
V
= 3 V; |ICC| = 65 mA 50 100
CC
= 1.8 V; |ICC| = 45 mA 30 60
V
CC
No external resistors at pin PORADJ;
V
level falling. See Figure 4.
DD
No external resistors at pin PORADJ.
See Figure 4.
External resistor divider at pin PORADJ;
V
level rising. See Section 6.2.2.
DD
External resistor divider at pin PORADJ;
V
level falling. See Section 6.2.2.
DD
External resistor divider at pin PORADJ.
See Section 6.2.2.
CLK
= f
XTAL
; CL = 30 pF;
2.35 2.45 2.55 V
50 100 150 mV
1.17 1.20 1.23 V
1.11 1.14 1.17 V
30 60 90 mV
Hysteresis of threshold
ΔV
HYS(ext)
voltage V
th(ext)
variation
External resistor divider at pin PORADJ 0.25 mV/K
with temperature
V
mA
10
mA
t
Width of internal power-
W
on reset pulse
PORADJ
External resistor divider at pin PORADJ 8 16 24
No external resistor divider at pin
I
P
TOT
1. VDD = 3.3 V, V
Leakage current on pin
L
PORADJ
Total power dissipation Continuous operation; TA = –25 to 85 °C 0.56 W
DDP
= 5 V, f
V
V
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
< 0.5 V –0.1 4 10
PORADJ
> 1.0 V –1 1
PORADJ
10/35 Doc ID 17709 Rev 5
4812
ms
µA
ST8024L Electrical characteristics
Table 7. Step-up converter
Symbol Parameter
f
CLK
V
th(vd-vf)
(1)
Test conditions Min. Typ. Max. Unit
Clock frequency Card active 2.2 3.2 MHz
Threshold voltage for
5 V card 5.2 5.8 6.2
step-up converter to
change to voltage
follower
1.8 V card 3.8 4.1 4.4
5 V card 5.2 5.7 6.2
V
Output voltage on pin
UP
V
(average value)
UP
1.8 V card 3.5 3.9 4.3
1. VDD = 3.3 V, V
Table 8. Card supply voltage characteristics
Symbol Parameter
C
VCC
= 5 V, f
DDP
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
(1)
External capacitance
on pin V
CC
(2)
See
Card inactive; |I
Card inactive; |I
Card active; |I
Card active; |I
Card active; |I
Test conditions Min. Typ. Max. Unit
CC
CC
| < 80 mA 5 V card 4.75 5 5.25
CC
| < 65 mA 3 V card 2.85 3 3.15
CC
| < 45 mA 1.8 V card 1.68 1.8 1.92
CC
Card active; single current
Card supply voltage
V
CC
(including ripple
voltage)
Card active; single current
pulse I
pulse I
= –100 mA; tp = 2 µs
P
= –100 mA; tp = 2 µs
P
Card active; single current
pulse I
= –100 mA; tp = 2 µs
P
Card active; current pulses,
Q
= 40 nAs
P
| = 0 mA
| = 1 mA
80 400 nF
5 V, 3 V and
1.8 V card
5 V, 3 V and
1.8 V card
-0.1 0 0.1
-0.1 0 0.3
5 V card 4.65 5 5.25
3 V card 2.76 3 3.20
1.8 V card 1.62 1.8 1.98
5 V card 4.65 5 5.25
3 V card 2.76 3 3.20
1.8 V card 1.62 1.8 1.98
V3 V card 3.8 4.1 4.4
V3 V card 3.5 3.9 4.3
V
V
CC
(RIPPLE)
(P-P)
Ripple voltage on
V
(peak-to-peak
CC
value)
Card active; current pulses
Q
= 40 nAs with
P
|I
| < 200 mA, tp < 400 ns
CC
f
= 20 kHz to 200 MHz 350 mV
RIPPLE
5 V card 4.65 5 5.25
3 V card 2.76 3 3.20
1.8 V card 1.62 1.8 1.98
Doc ID 17709 Rev 5 11/35
Electrical characteristics ST8024L
Table 8. Card supply voltage characteristics (continued)
Symbol Parameter
|ICC| Card supply current
S
1. VDD = 3.3 V, V
within limits but are tested only statistically for the temperature range. When a parameter is specified as a function of V
VCC it means their actual value at the moment of measurement.)
2. To meet these specifications, pin VCC should be decoupled to CGND using two 100 nF ceramic multilayer capacitors of
max. 350 mΩ ESR. If V
Slew rate
R
= 5 V, f
DDP
(1)
V
= 0 to 5 V 80
CC
= 0 to 3 V 65
V
CC
V
= 0 to 1.8 V 45
CC
V
short-circuit to GND 90 120
CC
Slew up or down, V
|I
| < 30 mA
CC
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C. (All parameters remain
XTAL
slew rate is not critical, the capacitance value can be up to 400 nF. (See Figure 10).
CC
Test conditions Min. Typ. Max. Unit
= 5 V; 3 V; 1.8 V;
CC
0.08 0.15 0.22 V/µs
DD
mA
or
Table 9. Crystal connection (pins XTAL1 and XTAL2)
Symbol Parameter
(1)
Test conditions Min. Typ. Max. Unit
External capacitance
C
XTAL1,2
on pins XTAL1,
Depends on type of crystal or resonator used - 15 pF
XTAL2
f
XTAL
f
XTAL1
V
IH
V
1. VDD = 3.3 V, V
Table 10. Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC, and AUX2UC)
Symbol Parameter
t
D(I/O-I/OUC),
t
D(I/OUC-I/O )
Crystal frequency 2 - 26 MHz
Frequency applied on
pin XTAL1
High level input
voltage on pin XTAL1
Low level input
IL
voltage on pin XTAL1
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
(1)
Test conditions Min. Typ. Max. Unit
0-26MHz
0.7
V
DD
-0.3 -
I/O to I/OUC, I/OUC
to I/O falling edge
- - 200 ns
delay
V
-
DD
+0.3
+0.3
V
DD
V
V
t
PU
f
I/O(MAX)
C
1. VDD = 3.3 V, V
Active pull-up pulse
width
Maximum frequency
on data lines
Input capacitance on
I
data lines
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
12/35 Doc ID 17709 Rev 5
- - 100 ns
--1MHz
- - 10 pF
ST8024L Electrical characteristics
Table 11. Data lines to card reader (pins I/O, AUX1, and AUX2 with integrated 11 kΩ pull-up
Symbol Parameter
resistor to V
CC
(1)
)
Test conditions Min. Typ. Max. Unit
No load 0 0.1
V
O(inactive)
I
O(inactive)
V
Output voltage Inactive mode
I
O(inactive)
= 1 mA 0.3
Output current Inactive mode; pin grounded -1 mA
High level output voltage
OH
No DC load 0.9 V
5 V and 3 V cards; I
1.8 V card I
< –40 µA 0.75 V
OH
< –40 µA 0.75 V
OH
CC
CC
CC
V
+0.1
CC
V
+0.1
CC
|IOH| ≥ 10 mA 0 0.4
I
= 1 mA 0 0.2
V
V
Low level output voltage
OL
High level input voltage
IH
OL
I
≥ 15 mA VCC–0.4 V
OL
5 V and 3 V cards 1.5 V
1.8 V card 0.6 V
CC
CC
CC
+0.3
5 V and 3 V cards 0.3 1.0
V
|I
LIH
Low level input voltage
IL
High level input leakage
|
current
1.8 V card 0 0.2
VIH = V
CC
10 µA
V
V
V
V
V
|I
| Low level input current VIL = 0 V 600 µA
IL
R
t
T(DI)
t
T(DO)
I
PU
1. VDD = 3.3 V, V
Integrated pull-up resistor Pull-up resistor to V
PU
CC
91113kΩ
Data input transition time VIL max. to VIH min. 1.2 µs
Data output transition
time
Current when pull-up
active
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
VO = 0 to VCC; CL ≤ 80 pF; 10% to
90%
V
= 0.9 VCC; CL = 80 pF -2 mA
OH
0.1 µs
Doc ID 17709 Rev 5 13/35
Electrical characteristics ST8024L
Table 12. Data lines to microcontroller (pins I/OUC, AUX1UC, and AUX2UC with integrated
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
|I
LIH
|I
| Low level input current VIL = 0 V 600 µA
L
R
PU
t
T(DI)
t
T(DO)
I
PU
1. VDD = 3.3 V, V
11 kΩ pull-up resistor to V
(1)
High level output voltage
)
DD
Test conditions Min. Typ. Max. Unit
5 V, 3 V and 1.8 V cards;
I
< –40 µA
OH
0.75 V
No DC load 0.9 V
DD
DD
V
DD
V
DD
Low level output voltage IOL = 1 mA 0 0.3 V
High level input voltage 0.7 V
DD
V
DD
Low level input voltage -0.3 0.3 V
High level input leakage
|
current
Internal pull-up resistance to
V
DD
Data input transition time V
Data output transition time
VIH = V
DD
Pull-up resistor to V
max. to V
IL
= 0 to VDD; CL < 30 pF;
V
O
min. 1.2 µs
IH
10% to 90%
DD
10 µA
91113kΩ
0.1 µs
Current when pull-up active VOH = 0.9 VDD; CL = 30 pF -1 mA
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
+0.1
+0.1
+0.3 V
DD
V
V
Table 13. Internal oscillator
Symbol Parameter
f
OSC(INT)
1. VDD = 3.3 V, V
Table 14. Reset output to card reader (pin RST)
Symbol Parameter
V
O(inactive)
I
O(inactive)
t
D(RSTIN-
RST)
V
OL
V
OH
t
R, tF
1. VDD = 3.3 V, V
(1)
Frequency of internal
oscillator
= 5 V, f
DDP
= 10 MHz, unless otherwise noted.Typical values are at TA = 25 °C.
XTAL
(1)
Output voltage in inactive
mode
Inactive mode 55 140 200 kHz
Active mode 2.2 2.7 3.2 MHz
I
No load 0 - 0.1
Test conditions Min. Typ. Max. Unit
Test conditions Min. Typ. Max. Unit
O(inactive)
= 1 mA 0 - 0.3
Output current Inactive mode; pin grounded 0 - -1 mA
RSTIN to RST delay RST enable - 2 µs
= 200 µA 0 - 0.2
I
Low level output voltage
High level output voltage
OL
I
= 20 mA (current limit) V
OL
= –200 µA 0.9 V
I
OH
I
= –20 mA (current limit) 0 - 0.4
OH
Rise and fall time CL = 100 pF - 0.1 µs
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
-0.4 - V
CC
CC
-V
CC
CC
V
V
V
14/35 Doc ID 17709 Rev 5
ST8024L Electrical characteristics
Table 15. Clock output to card reader (pin CLK)
Symbol Parameter
V
O(inactive)
I
O(inactive)
V
OL
V
OH
t
R, tF
δ Duty factor (except for f
S
R
1. VDD = 3.3 V, V
2. Transition time and duty factor definitions are shown in Figure 3; d = t
Table 16. Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V and PORADJ/1.8V)
Symbol Parameter
(1)
I
Output voltage in inactive
mode
Output current
Low level output voltage
High level output voltage
O(inactive)
No load 0 - 0.1
CLK inactive mode;
pin grounded
I
OL
I
OL
I
OH
I
OH
Rise and fall time CL = 30 pF
)CL = 30 pF
XTAL
Test conditions Min. Typ. Max. Unit
= 1 mA 0 - 0.3
0-–1mA
= 200 µA 0 - 0.3
= 70 mA (current limit) V
= –200 µA 0.9 V
-0.4 - V
CC
CC
-V
CC
CC
= –70 mA (current limit) 0 - 0.4
(2)
(2)
45 - 55 %
-16ns
V
V
V
Slew rate Slew up or down; CL = 30 pF 0.2 - V/ns
= 5 V, f
DDP
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
/(t1+ t2).
1
(1)
Test conditions Min. Typ. Max. Unit
V
V
|I
LIH
Low level input voltage –0.3 0.3 V
IL
High level input voltage 0.7 V
IH
High level input leakage
|
current
= V
V
IH
DD
V
= VDD, 1.8V and CLKDIV2
IH
pins with internal 11 kΩ pull-
DD
down resistor
V
= 0 -1 µA
|I
LIL
R
PD
R
PU
1. VDD = 3.3 V, V
Pin CMDVCC is active low; pin RSTIN is active high; for CLKDIV1 and CLKDIV2 functions (see Table 21).
Low level input leakage
|
current
Internal pull-down resistor to
GND
Internal pull-up resistor to
V
DD
= 5 V, f
DDP
XTAL
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
IL
V
= 0, CLKDIV1 pin with
IL
internal 11 kΩ pull-up resistor
Pull-down resistor to GND (1.8V
and CLKDIV2 pins)
Pull-up resistor to VDD
(CLKDIV1 pin)
-800 µA
91113kΩ
91113kΩ
DD
V
DD
V
V
1µA
800 µA
Doc ID 17709 Rev 5 15/35
Electrical characteristics ST8024L
Table 17. Card presence inputs (pins PRES and PRES)
Symbol Parameter
V
IL
V
IH
|I
LIH
|I
LIL
1. VDD = 3.3 V, V
Pin PRES is active low; pin PRES is active high, see Figure 8 and Figure 9; PRES has an integrated 1.25 µA current source
to GND. (PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active.
Table 18. Interrupt output (pin OFF NMOS drain with integrated 20 kΩ pull-up resistor to VDD)
Symbol Parameter
V
OL
V
OH
R
PU
1. VDD = 3.3 V, V
(1)
Test conditions Min. Typ. Max. Unit
Low level input voltage -0.3 - 0.3 V
High level input voltage 0.7 V
High level input leakage
|
current
Low level input leakage
|
current
= 5 V, f
DDP
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C
XTAL
(1)
VIH = V
DD
VIL = 0 - 5 µA
Test conditions Min. Typ. Max. Unit
DD
-V
DD
-5µA
Low level output voltage IOL = 2 mA 0 0.3 V
High level output voltage IOH = –15 µA 0.75 V
Integrated pull-up resistor 20 kΩ pull-up resistor to V
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
DD
DD
16 20 24 kΩ
DD
+0.3 V
V
V
Table 19. Protection and limitation
Symbol Parameter
|I
CC(SD)
I
I/O(lim)
I
CLK(lim)
I
RST(lim)
T
SD
1. VDD = 3.3 V, V
Table 20. Timing
Symbol Parameter
t
ACT
t
DE
t
3
t
5
t
debounce
1. VDD = 3.3 V, V
(1)
| Shutdown and limitation current pin V
Limitation current pins I/O, AUX1 and AUX2 –15 15 mA
Limitation current pin CLK –70 70 mA
Limitation current pin RST –20 20 mA
Shutdown temperature 150 °C
= 5 V, f
DDP
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
(1)
Activation time
Deactivation time (See Figure 7)5080100µs
Start of the window for sending CLK to card (See Figure 6)130µs
End of the window for sending CLK to card (See Figure 6) 140 µs
Debounce time pins PRES and PRES (See Figure 8)5811ms
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are at TA = 25 °C.
XTAL
CC
Test conditions Min. Typ. Max. Unit
90 120 mA
Test conditions Min. Typ. Max. Unit
For V
(See Figure 5)
CC
= 5 V
50 220 µs
16/35 Doc ID 17709 Rev 5
ST8024L Electrical characteristics
Figure 3. Definition of output and input transition times
CS13450
Doc ID 17709 Rev 5 17/35
Functional description ST8024L
6 Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816
terminology.
6.1 Power supply
The supply pins for the ST8024L are VDD and GND. VDD should be in the range of 2.7 to
6.5 V. All signals interfacing with the system controller are referred to V
should also supply the system controller. All card reader contacts remain inactive during
power-on or power-off.
, therefore VDD
DD
The internal circuits are kept in the reset state until V
duration of the internal power-on reset pulse, t
(see Figure 4). When VDD falls below V
W
an automatic deactivation of the contacts is performed.
A step-up converter is incorporated to generate the 1.8 V (for those devices with the
1.8V pin), 3 V, or 5 V card supply voltage (V
separately by V
and PGND. Due to the possibility of large transient currents, the two
DDP
). The step-up converter should be supplied
CC
100 nF capacitors of the step-up converter should be located as near as possible to the
ST8024L and have an ESR less than 350 mΩ
During power-up, the V
supply voltage must be applied prior to the V
DD
.
or at the same time
After powering the device, OFF
During power-off, OFF
falls low when VDD is below the falling threshold voltage.
remains low until CMDVCC is set high.
6.2 Voltage supervisor
6.2.1 Without external divider on pin PORADJ
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8 ms
(t
) is used internally to keep the ST8024L inactive during power-on or power-off of the VDD
W
supply (see Figure 4).
As long as V
is less than V
DD
levels on the command lines. This state also lasts for the duration of t
reached a level higher than V
sequence of the contacts is performed.
th2
th2
+ V
+ V
, the ST8024L remains inactive regardless of the
HYS2
. When VDD falls below V
HYS2
reaches V
DD
+V
th2
W
, a deactivation
th2
and for the
HYS2
supply voltage
DDP
after VDD has
th2
,
18/35 Doc ID 17709 Rev 5
ST8024L Functional description
Figure 4. Voltage supervisor
6.2.2 With an external divider on pin PORADJ
In this case, a resistor divider is connected to the PORADJ pin (see Figure 1). V
and V
voltages on pin PORADJ that switch the device on and off. By knowing these values and
using the formula:
it is possible to set R1 and R2 in order to get suitable values for VDD undervoltage (UVLO)
thresholds, in order to turn the device on and off (R
In particular, R
microcontroller off, the smartcard must also be switched off properly. The same is true for
the microcontroller startup - in such case the smartcard must be turned on after the
microcontroller. The reset pulse width t
Input PORADJ is biased internally with a pull-down current source of 4 µA which is removed
when the voltage on pin PORADJ exceeds 1 V.
This ensures that after detection of the external divider by the ST8024L during power-on,
the input current on pin PORADJ does not cause inaccuracy of the divider voltage.
Note: The V
of the ST8024 device. If, for example, the microcontroller is shut down at 2.5 V, the
appropriate external resistor values must be chosen to ensure proper deactivation of the
ST8024L device.
th(ext) fall
th(ext)
are the external rising threshold voltage and the external falling threshold
UVLO threshold (falling) = (R1+R2)/R2 x V
V
DD
V
UVLO threshold (rising) = (R1+R2)/R2 x V
DD
+ R2 = 100 kΩ typ.).
1
and R2 must be set so that, when VDD is getting low, before turning the
1
is doubled to approximately 16 ms.
W
th(ext)fall
th(ext)rise
threshold of the ST8024L is slightly lower (by 80 mV typ.) than it was in the case
th(ext) rise
6.2.3 Application examples
The voltage supervisor is used as power-on reset and as supply dropout detection during
a card session. Supply dropout detection is to ensure that a proper deactivation sequence is
followed before the voltage is too low. For the internal voltage supervisor to function, the
system microcontroller should operate down to 2.35 V to ensure a proper deactivation
sequence. If this is not possible, external resistor values can be chosen to overcome the
problem.
Doc ID 17709 Rev 5 19/35
Functional description ST8024L
6.3 Clock circuitry (only on SO-28 and TSSOP-28 packages)
The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from
a crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be f
XTAL
, 1/2 x f
XTAL
, 1/4 x f
XTAL
, or 1/8 x f
. Frequency selection
XTAL
is made via inputs CLKDIV1 and CLKDIV2 (see Tabl e 2 1).
Table 21. Clock frequency selection
CLKDIV1 CLKDIV2 f
00f
01f
11f
10f
1. The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum
between changes is needed. The minimum duration of any state of CLK is eight periods of XTAL1.
(1)
CLK
XTAL
XTAL
XTAL
XTAL
/8
/4
/2
The frequency change is synchronous, which means that during transition no pulse is
shorter than 45% of the smallest period, and that the first and last clock pulses regarding the
instant of change have the correct width.
When changing the frequency dynamically, the change is effective for only eight periods of
XTAL1 after the command. The duty factor of f
depends on the signal present at pin
XTAL
XTAL1. In order to reach a 45 to 55% duty factor on pin CLK, the input signal on pin XTAL1
should have a duty factor of 48 to 52% and transition times of less than 5% of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be 45 to 55% depending on the circuit
layout and on the crystal characteristics and frequency. In other cases, the duty factor on pin
CLK is guaranteed between 45 and 55% of the clock period.
The crystal oscillator runs as soon as the ST8024L is powered up. If the crystal oscillator is
used, or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card
as shown in the activation sequences in Figure 5 and Figure 6.
If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse is
applied to the card when it is sent by the system microcontroller (after completion of the
activation sequence).
20/35 Doc ID 17709 Rev 5
ST8024L Functional description
6.4 I/O transceivers
The three data lines I/O, AUX1, and AUX2 are identical. The idle state is realized by both I/O
and I/OUC lines being pulled high via an 11 kΩ resistor (I/O to V
I/O is referenced to V
equal to V
. The first side of the transceiver to receive a falling edge becomes the master.
DD
, and pin I/OUC to VDD, therefore allowing operation when VCC is not
CC
and I/OUC to VDD). Pin
CC
An anti-latch circuit disables the detection of falling edges on the line of the other side, which
then becomes a slave. After a time delay t
, an N transistor on the slave side is turned
d(edge)
on, therefore transmitting the logic 0 present on the master side. When the master side
returns to logic 1, a P transistor on the slave side is turned on during the time delay t
PU
and
then both sides return to their idle states. This active pull-up feature ensures fast low to high
transitions; it is able to deliver more than 1 mA, at an output voltage of up to 0.9 V
, into an
CC
80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the
internal pull-up resistor and the load current. The current to and from the card I/O lines is
limited internally to 15 mA and the maximum frequency on these lines is 1 MHz.
6.5 Inactive mode
After a power-on reset, the circuit enters inactive mode. A minimum number of circuits are
active while waiting for the microcontroller to start a session:
– All card contacts are inactive (approximately 200 Ω to GND)
– Pins I/OUC, AUX1UC, and AUX2UC are in the high impedance state (11 kΩ pull-up
resistor to V
– Voltage generators are stopped
– XTAL oscillator is running
– Voltage supervisor is active
– The internal oscillator is running at its low frequency.
). Applies only to SO-28 and TSSOP-28 packages.
DD
6.6 Activation sequence
After power-on and after the internal pulse width delay, the system microcontroller can
check the presence of a card using the signals OFF
If the card is in the reader (this is the case if PRES
microcontroller can start a card session by pulling CMDVCC
then occurs (see Figure 6):
1. CMDVCC
2. The step-up converter is started (between t
3. V
CC
T is 64 times the period of the internal oscillator (approximately 25 µs).
4. I/O, AUX1, and AUX2 are enabled (t
moment).
5. CLK is applied to the C3 contact of the card reader (t
6. RST is enabled (t
is pulled low and the internal oscillator changes to its high frequency (t0).
rises from 0 to 5 V (or 1.8 V, 3 V) with a controlled slope (t2 = t1 + 1.5 x T) where
= t1 + 7T).
5
and CMDVCC, as shown in Ta bl e 2 2.
or PRES is active), the system
low. The following sequence
and t1).
0
= t1 + 4T) (these were pulled low until this
3
).
4
Doc ID 17709 Rev 5 21/35
Functional description ST8024L
The clock may be applied to the card using the following sequence (see Figure 5):
1. Set RSTIN high.
2. Set CMDVCC
3. Reset RSTIN low between t
4. RST remains low until t
5. After t
5
low.
and t5; CLK starts at this moment.
3
, when RST is enabled to be the copy of RSTIN.
5
, RSTIN has no further affect on CLK; this allows a precise count of CLK
pulses before toggling RST.
If the applied clock is not needed, then CMDVCC
case, CLK starts at t
(minimum 200 ns after the transition on I/O), and after t5, RSTIN may
3
may be set low with RSTIN low. In this
be set high in order to obtain an “answer to request” (ATR) from the card.
Activation should not be performed with RSTIN held permanently high.
Note: It is recommended that no control smartcard signals are to be shared with any other
devices. Sharing may result in inadvertent activation or deactivation of the smartcard.
Table 22. Card presence indicator
OFF CMDVCC Indication
H H Card present
L H Card not present
Figure 5. Activation sequence using RSTIN and CMDVCC
22/35 Doc ID 17709 Rev 5
ST8024L Functional description
Figure 6. Activation sequence at t
3
6.7 Active mode
When the activation sequence is completed, the ST8024L is in its active mode. Data are
exchanged between the card and the microcontroller via the I/O lines.
The ST8024L is designed for cards without V
the internal non-volatile memory).
6.8 Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit
then executes an automatic deactivation sequence by counting the sequencer back and
finishing in the inactive mode (see Figure 7):
1. RST goes low (t
2. CLK is held low (t
oscillator (approximately 25 µs).
3. I/O, AUX1, and AUX2 are pulled low (t
4. V
starts to fall towards zero (t14 = t10 + 1.5 x T).
CC
5. The deactivation sequence is complete at t
6. All card contacts become low impedance to GND; I/OUC, AUX1UC, and AUX2UC
remain at V
7. The internal oscillator returns to its lower frequency.
).
10
= t10 + 0.5 x T) where T is 64 times the period of the internal
12
(pulled-up via an 11 kΩ resistor).
DD
(the voltage required to program or erase
PP
= t10 + T).
13
, when VCC reaches its inactive state.
DE
Doc ID 17709 Rev 5 23/35
Functional description ST8024L
Figure 7. Deactivation sequence
6.9 VCC generator
The VCC generator has a capacity to supply up to 80 mA (max.) continuously at 5 V,
65 mA (max.) at 3 V, and 45 mA (max.) at 1.8 V. An internal overload detector operates at
approximately 120 mA. Current samples to the detector are internally filtered, allowing
spurious current pulses up to 200 mA with a duration in the order of µs to be drawn by the
card without causing deactivation. The average current must stay below the specified
maximum current value. For reasons of V
ESR < 350 mΩ should be tied to CGND near to pin V
same ESR should be tied to CGND near card reader contact C1.
voltage accuracy, a 100 nF capacitor with an
CC
, and a 100 nF capacitor with the
CC
24/35 Doc ID 17709 Rev 5
ST8024L Functional description
6.10 Fault detection
The following fault conditions are monitored:
● Short-circuit or high current on V
Removal of a card during a transaction
●
● V
● Step-up converter operating out of the specified values (V
● Overheating
● There are two different cases (see Figure 8):
dropping
DD
V
too high)
UP
–CMDVCC
high outside a card session. Output OFF is low if a card is not in the
card reader, and high if a card is in the reader. A voltage drop on the V
detected by the supply supervisor, this generates an internal power-on reset pulse
but does not act upon OFF
card is not powered-up.
–CMDVCC
low within a card session. Output OFF goes low when a fault condition
is detected. As soon as this occurs, an emergency deactivation is performed
automatically (see Figure 9). When the system controller resets CMDVCC
it may sense the OFF
distinguishes between a hardware problem or a card extraction (OFF
again if a card is present).
CC
too low or current from
DDP
supply is
DD
. No short-circuit or overheating is detected because the
to high,
level again after completing the deactivation sequence. This
goes high
Depending on the type of card-present switch within the connector (normally closed or
normally open) and on the mechanical characteristics of the switch, bouncing may occur on
the PRES signals at card insertion or withdrawal.
There is a debounce feature in the device with an 8 ms typical duration (see Figure 8).
When a card is inserted, output OFF
goes high only at the end of the debounce time.
When the card is extracted, an automatic deactivation sequence of the card is performed on
the first true/false transition on PRES or PRES
Figure 8. Behavior of OFF
, CMDVCC, PRES, and V
and output OFF goes low.
CC
Doc ID 17709 Rev 5 25/35
Functional description ST8024L
Figure 9. Emergency deactivation sequence (card extraction)
6.11 VCC selection settings
The ST8024L supports three smartcard VCC voltages: 1.8 V, 3 V, and 5 V. The VCC selection
is controlled by the 1.8V and 5V/3
priority over the 5V/3
setting on the 5V/3
When the 1.8V pin is taken low, the 5V/3
taken high, then V
Table 23. VCC selection settings
5V/3V pin 1.8V pin VCC output
00 3 V
10 5 V
x1 1.8 V
V. When the 1.8 V pin is taken high, VCC is 1.8 V and it overrides any
V pin.
is 5 V, and if the 5V/3V pin is taken low then VCC is 3 V.
CC
V signals as shown in Table 23. The 1.8V signal has
V pin selects the 5 V or 3 V VCC. If the 5V/3V pin is
26/35 Doc ID 17709 Rev 5
ST8024L Applications
7 Applications
Figure 10. Hardware hookup
1. These capacitors must be < 350 mΩ ESR and be placed near the IC (within 10 mm).
2. ST8024L and the microcontroller must use the same V
3. Make short, straight connections between CGND, C5, and the ground connection to the capacitor.
4. Mount one ESR-type (< 350 mΩ) 100 nF capacitor close to pin V
5. Mount one ESR-type (< 350 mΩ) 100 nF capacitor close to C1 contact.
6. The connection to C3 should be routed as far as possible from C2, C7, C4, and C8 and, if possible, surrounded by
grounded tracks.
7. This is the optional resistor divider for changing the threshold of V
required, pin 18 should be connected to ground.
supply.
DD
.
CC
when using the PORADJ function. If this divider is not
DD
Doc ID 17709 Rev 5 27/35
Package mechanical data ST8024L
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Figure 11. SO-28 small outline, package mechanical drawing
0016572_F
Table 24. SO-28 small outline, package mechanical data
Dimensions
Symbol
Min. Typ. Max. Min. Typ. Max.
A 2.65 0.104
a1 0.1 0.3 0.004 0.012
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.012
C 0.5 0.020
c1 45° (typ.)
D 17.70 18.10 0.697 0.713
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 16.51 0.650
F 7.40 7.60 0.291 0.300
L 0.50 1.27 0.020 0.050
S8° (max.)
mm. inches
28/35 Doc ID 17709 Rev 5
ST8024L Package mechanical data
Figure 12. TSSOP-20 package mechanical drawing
A2
A
A1
b
e
D
K
c
E1
L
E
PIN 1 IDENTIFICATION
Table 25. TSSOP-20 package mechanical data
1
0087225_D
Dimensions
Symbol
mm. inches
Min. Typ. Max. Min. Typ. Max.
A1.20.047
A1 0.05 0.15 0.002 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0079
D 6.4 6.5 6.6 0.252 0.256 0.260
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0° 8°0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
Doc ID 17709 Rev 5 29/35
Package mechanical data ST8024L
Figure 13. TSSOP-28 package mechanical drawing
0128292_D
Table 26. TSSOP-28 package mechanical data
Dimensions
Symbol
mm. inches
Min. Typ. Max. Min. Typ. Max.
A1.20.047
A1 0.05 0.15 0.002 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0079
D 9.6 9.7 9.8 0.378 0.382 0.386
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0° 8°0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
30/35 Doc ID 17709 Rev 5
ST8024L Package mechanical data
Figure 14. SO-28 tape and reel schematic
Note: Drawing is not to scale.
Table 27. SO-28 tape and reel mechanical data
Dimensions
Symbol
mm. inches
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T30.41.197
A
O
B
O
K
O
P
O
10.8 11.0 0.425 0.433
18.2 18.4 0.716 0.724
2.9 3.1 0.114 0.122
3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
Doc ID 17709 Rev 5 31/35
Package mechanical data ST8024L
Figure 15. TSSOP-20 tape and reel schematic
Note: Drawing is not to scale.
Table 28. TSSOP-20 tape and reel mechanical data
Dimensions
Symbol
mm. inches
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T22.40.882
A
O
B
O
K
O
P
O
6.8 7 0.268 0.276
6.9 7.1 0.272 0.280
1.7 1.9 0.067 0.075
3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
32/35 Doc ID 17709 Rev 5
ST8024L Package mechanical data
Figure 16. TSSOP-28 tape and reel schematic
Note: Drawing is not to scale.
Table 29. TSSOP-28 tape and reel mechanical data
Dimensions
Symbol
mm. inches
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T22.40.882
A
O
B
O
K
O
P
O
6.8 7 0.268 0.276
10.1 10.3 0.398 0.406
1.7 1.9 0.067 0.075
3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
Doc ID 17709 Rev 5 33/35
Revision history ST8024L
9 Revision history
Table 30. Document revision history
Date Revision Changes
19-Jul-2010 1 Initial release.
30-Jul-2010 2 Updated Description, Table 6.
27-Sep-2010 3
09-Feb-2012 4
04-May-2012 5
Updated Features, Tab l e 1 , 6, 8, 19, 20, Section 6.1,
Section 6.2.2, Section 6.6, Section 6.9, footnotes of Figure 10.
Added ST8024LACTR device, updated Features, Ta b l e 1 ,
Section 1: Description (moved to page 5), Figure 1,Figure 2,
Ta b le 2 , Ta bl e 6 ,Ta b l e 8 , Section 6.1 to Section 6.3, Figure 10
and Disclaimer, minor text corrections throughout document.
Updated Figure 1, Ta bl e 2 , Ta b le 3 , Tab le 6 , Tab l e 8 , Ta b l e 1 4 ,
Ta b le 1 6 , Ta b le 1 7 , Section 6.1, moved notes from Section 5
below Table 3, Ta b l e 8 , Table 15, Ta bl e 1 6, Ta b l e 1 7 , minor
text corrections throughout document.
34/35 Doc ID 17709 Rev 5
ST8024L
y
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Doc ID 17709 Rev 5 35/35
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