Features
■ Designed to be compatible with the NDS
conditional access system
■ IC card interface
■ 3 or 5 V supply for the IC (V
■ Three specifically protected half-duplex bi-
directional buffered I/O lines to card contacts
C4, C7 and C8
■ DC-DC converter for V
CC
separately powered from a 5 V ± 20% supply
(V
and PGND)
DDP
■ 3 or 5 V ± 5 % regulated card supply voltage
(V
) with appropriate decoupling has the
CC
following capabilities:
–I
< 80 mA at V
CC
DDP
– Handles current spikes of 40 nA up to 20
MHz
– Controls rise and fall times
– Filtered overload detection at
approximately 120 mA
■ Thermal and short-circuit protection on all card
contacts
■ Automatic activation and deactivation
sequences; initiated by software or by
hardware in the event of a short-circuit, card
take-off, overheating, V
■ Enhanced ESD protection on card side (> 6 kV)
■ 26 MHz integrated crystal oscillator
■ Clock generation for cards up to 20 MHz
DD
(divided by 1, 2, 4 or 8 through CLKDIV1 and
CLKDIV2 signals) with synchronous frequency
changes
■ Non-inverted control of RST via pin RSTIN
and GND)
DD
generation
= 4 to 6.5 V
or V
DDP
drop-out
ST8024
Smartcard interface
SO-28
■ ISO 7816, GSM11.11 and EMV (payment
systems) compatibility
■ Supply supervisor for spike-killing during
power-on and power-off and power-on reset
(threshold fixed internally or externally by a
resistor bridge)
■ Built-in debounce on card presence contacts
■ One multiplexed status signal off
Description
The ST8024 is a complete low cost analog
interface for asynchronous 3 V and 5 V smart
cards. It can be placed between the card and the
microcontroller with few external components to
perform all supply protection and control
functions. ST8024 is a direct replacement of
ST8004.
Main applications are: smartcard readers for settop-box, IC card readers for banking,
identification, pay TV.
TSSOP28
Table 1. Device summary
Order codes Temperature range Packages Packaging
ST8024CDR - 25 to 85 °C SO-28 (tape and reel) 1000 parts per reel
ST8024CTR - 25 to 85 °C TSSOP28 (tape and reel) 2500 parts per reel
March 2009 Rev 8 1/31
www.st.com
31
Contents ST8024
Contents
1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.1 Without external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.2 With an external divider on pin PORADJ . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.3 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 I/O transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 Inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6 Activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.8 Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.9 V
5.10 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CC
6 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
ST8024 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Electrical characteristics over recommended operating condition . . . . . . . . . . . . . . . . . . . . 9
Table 7. Step-up converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Card supply voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Crystal connection (pins XTAL1 and XTAL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC AND AUX2UC). . . . . . . . . . . . . . . . . 11
Table 11. Data lines to card reader (pins I/O, AUX1 AND AUX2 with integrated
11 kΩ pull-up resistor to V
Table 12. Data lines to microcontroller (pins I/OUC, AUX1UC AND AUX2UC with
integrated 11 kΩ pull-up resistor to V
Table 13. Internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 14. Reset output to card reader (pin RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 15. Clock output to card reader (pin CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 16. Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5 V / 3 V . . . . . . . . . . . . 14
Table 17. Card presence inputs (pins PRES and PRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 18. Interrupt output (pin OFF NMOS drain with integrated 20 kΩ pull-up resistor to V
Table 19. Protection and limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 20. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 21. Clock frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 22. Card presence indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DD
); . . . 14
DD
3/31
List of figures ST8024
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Definition of output and input transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Activation sequence using RSTIN and CMDVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Activation sequence at t
Figure 7. Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Behavior of OFF, CMDVCC, PRES and V
Figure 9. Emergency deactivation sequence (card extraction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CC
4/31
ST8024 Diagram
1 Diagram
Figure 1. Block diagram
5/31
Pin configuration ST8024
2 Pin configuration
Figure 2. Pin connections
Table 2. Pin description
Pin n° Symbol Name and function
1 CLKDIV1 Control of CLK frequency
2 CLKDIV2 Control of CLK frequency
35V/3V
4 PGND Power ground for step-up converter
5 C1+ External cap. for step-up converter
6V
DDP
7 C1- External cap. step-up converter
8V
UP
9PRES
10 PRES Card presence input (active high)
11 I/O Data line to and from card (C7) (internal 11 kΩ pull-up resistor connected to V
12 AUX2 Auxiliary line to and from card (C8) (internal 11 kΩ pull-up resistor connected to V
13 AUX1 Auxiliary line to and from card (C4) (internal 11 kΩ pull-up resistor connected to V
14 CGND Ground for card signal (C5)
15 CLK Clock to card (C3)
16 RST Card reset (C2)
17 V
18 V
CC
THSEL
VCC selection pin
Power supply for step-up converter
Output of step-up converter
Card presence input (active low)
Supply voltage for the card (C1)
Deactivation threshold selector pin (under voltage lock-out)
CC
)
)
CC
)
CC
6/31
ST8024 Pin configuration
Table 2. Pin description (continued)
Pin n° Symbol Name and function
19 CMDVCC
Start activation sequence input (active low)
20 RSTIN Card reset input from MCU
21 V
DD
Supply voltage
22 GND Ground
23 OFF
Interrupt to MCU (active low)
24 XTAL1 Crystal or external clock input
25 XTAL2 Crystal connection (leave this pin open if external clock is used)
26 I/OUC MCU data I/O line (internal 11 kΩ pull-up resistor connected to V
DD
)
27 AUX1UC Non-inverting receiver input (internal 11 kΩ pull-up resistor connected to V
28 AUX2UC Non-inverting receiver input (internal 11 kΩ pull-up resistor connected to V
DD
DD
)
)
7/31
Maximum ratings ST8024
3 Maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
V
DD, VDDP
Supply voltage -0.3 7 V
Voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC,
V
V
V
ESD1
ESD2
T
J(MAX)
T
STG
1. All card contacts are protected against any short with any other card contact
2. Method 3015 (HBM, 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground.
AUX1UC, I/OUC, CLKDIV1, CLKDIV2, PORADJ, CMDVCC
n1
n2
n3
, PRES and OFF
PRES
Voltage on card contact pins I/O, RST, AUX1, AUX2 and CLK -0.3 VCC + 0.3 V
Voltage on pins VUP, S1 and S2 7 V
MIL-STD-883 class 3 on card contact pins, PRES
(2)
MIL-STD-883 class 2 on microcontroller contact pins and
(1) (2)
RSTIN
and PRES
Maximum operating junction temperature 150 °C
Storage temperature range -40 150 °C
,
(1)
-0.3 VDD + 0.3 V
-6 6 kV
-2 2 kV
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4. Thermal data
Symbol Parameter Condition SO-28 TSSOP28 Unit
R
Thermal resistance junction-ambient temperature
thJA
Multilayer test board
(Jedec standard)
56 50 °K/W
Table 5. Recommended operating conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
T
8/31
Temperature range -25 85 °C
A
ST8024 Electrical characteristics
4 Electrical characteristics
VDD = 3.3 V, V
T
= 25 °C.
A
Table 6. Electrical characteristics over recommended operating condition
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
DDP
DD
Supply voltage 2.7 6.5 V
= 5V; |ICC| < 80 mA 4.0 5 6.5
V
Supply voltage for the
voltage doubler
CC
= 5V; |ICC| < 20 mA 3.0 6.5
V
CC
Card Inactive 1.2
I
DD
Supply current
Card Active; f
CLK
= f
; CL = 30pF 1.5
XTAL
Inactive mode 0.1
= f
; CL = 30pF; |ICC|
XTAL
10
2.35 2.45 2.55 V
1.25 1.28 1.31 V
1.19 1.22 1.25 V
I
DDP
V
th2
V
HYS2
V
th(ext)rise
V
th(ext)fall
V
HYS(ext)
DC-DC converter supply
current
Falling threshold voltage
on V
DD
Hysteresis of threshold
voltage V
th2
External rising threshold
voltage on V
DD
External falling threshold
voltage on V
DD
Hysteresis of threshold
voltage V
th(ext)
Active mode; f
CLK
= 0
= 5V; |ICC| = 80 mA 200
V
CC
V
= 3V; |ICC| = 65 mA 100
CC
no external resistors at pin PORADJ;
VDD level falling
no external resistors at pin PORADJ 50 100 150 mV
external resistor bridge at pin PORADJ;
level rising
V
DD
external resistor bridge at pin PORADJ;
VDD level falling
external resistor bridge at pin PORADJ 30 60 90 mV
Hysteresis of threshold
ΔV
HYS(ext)
voltage V
th(ext)
variation
external resistor bridge at pin PORADJ 0.25 mV/K
with temperature
t
W
I
P
TOT
Width of internal PowerOn reset pulse
Leakage current on pin
L
PORADJ
Total power dissipation Continuous operation; Ta = -25 to 85°C 0.56 W
no external resistor at pin PORADJ 4 8 12
external resistor bridge at pin PORADJ 8 16 24
V
V
< 0.5 V -0.1 4 10
PORADJ
> 1.0 V -1 1
PORADJ
V
mA
mA
ms
µA
9/31
Electrical characteristics ST8024
VDD = 3.3 V, V
T
= 25 °C.
A
Table 7. Step-up converter
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
Symbol Parameter Test conditions Min. Typ. Max. Unit
f
CLK
V
th(vd-vf)
V
UP(av)
Table 8. Card supply voltage characteristics
Clock frequency Card active 2.2 3.2 MHz
Threshold voltage for step-
5 V card 5.2 5.8 6.2
up converter to change to
voltage follower
Output voltage on pin VUP
(average value)
VDD = 3.3 V, V
T
= 25 °C (Note 1).
A
DDP
3 V card 3.8 4.1 4.4
= 5 V 5.2 5.7 6.2
V
CC
V
= 5 V, f
= 3 V; V
CC
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
= 3.3 V 3.5 3.9 4.3
DDP
Symbol Parameter Test conditions Min. Typ. Max. Unit
C
VCC
External capacitance
on pin V
CC
Card supply voltage
V
(including ripple
CC
voltage)
V
CC
(RIPPLE)
(P-P)
Ripple voltage on V
(Peak to Peak value)
|ICC| Card supply current
S
Slew rate Slew up or down 0.08 0.15 0.22 V/µs
R
Note 2 and Note 3 80 220 nF
Card Inactive; |I
Card Inactive; |I
Card Active; |I
Card Active; |I
Card Active; single current
pulse I
=-100 mA; tp=2 µs
P
Card Active; single current
pulse I
=-100 mA; tp =2 µs
P
Card active; current pulses,
= 40 nAs
Q
P
Card Active; current pulses
=40 nAs with
Q
P
| < 200mA, tp < 400 ns
|I
CC
CC
f
= 20 kHz to 200 MHz 350 mV
RIPPLE
= 0 to 5V 80
V
CC
= 0 to 3V 65
CC
short circuit to GND 90 120
V
CC
| = 0 mA 5 and 3V card -0.1 0 0.1
CC
| = 1 mA 5 and 3V card -0.1 0 0.3
CC
| < 80 mA 5 V card 4.75 5 5.25
CC
| < 65 mA 3 V card 2.85 3 3.15
CC
5 V card 4.65 5 5.25
3 V card 2.76 3 3.20
5 V card 4.65 5 5.25
3 V card 2.76 3 3.20
5 V card 4.65 5 5.25
3 V card 2.76 3 3.20
V
V
V
mAV
10/31
ST8024 Electrical characteristics
VDD = 3.3 V, V
T
= 25 °C.
A
Table 9. Crystal connection (pins XTAL1 and XTAL2)
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
Symbol Parameter Test conditions Min. Typ. Max. Unit
C
XTAL1,2
f
XTAL
f
XTAL1
V
V
Table 10. Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC AND AUX2UC)
External capacitance on pins XTAIL1,
XTAIL2
Crystal frequency 2 26 MHz
Frequency applied on pin XTAL1 0 26 MHz
High level input voltage on pin XTAIL1 0.7 V
IH
Low level input voltage on pin XTAIL1 -0.3 +0.3V
IL
VDD = 3.3 V, V
T
= 25 °C.
A
DDP
= 5 V, f
XTAL
Depends on type of
crystal or resonator used
DD
15 pF
VDD+0.3 V
DD
= 10 MHz, unless otherwise noted. Typical values are to
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
D(I/O-I/OUC),
t
D(I/OUC-I/O)
t
pu
f
I/O(MAX)
C
I/O to I/OUC, I/OUC to I/O falling edge
delay
Active pull-up pulse width 100 ns
Maximum frequency on data lines 1 MHz
Input capacitance on data lines 10 pF
I
200 ns
V
VDD = 3.3 V, V
T
= 25 °C.
A
Table 11. Data lines to card reader (pins I/O, AUX1 AND AUX2 with integrated 11 kΩ pull-up
resistor to V
CC
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
Symbol Parameter Test conditions Min. Typ. Max. Unit
NO LOAD 0 0.1
V
O(inactive)
I
O(inactive)
V
V
V
V
|I
LIH
Output voltage Inactive mode
I
O(inactive)
=1mA 0.3
Output current Inactive mode; pin grounded -1 mA
No DC Load 0.9 V
High level output voltage
OH
|I
| ≥ 10mA 0 0.4
OH
I
= 1 mA 0 0.2
Low level output voltage
OL
High level input voltage 1.5 VCC+0.3 V
IH
Low level input voltage 0.3 0.8 V
IL
High level input leakage
|
current
OL
≥ 15 mA VCC-0.4 V
I
OL
= V
V
IH
CC
< - 40µA 0.75 V
OH
CC
CC
VCC+0.1
VCC+0.1
CC
10 µA
|IIL| Low level input current VIL = 0 V 600 µA
V
V5 and 3 V cards; I
V
11/31
Electrical characteristics ST8024
Table 11. Data lines to card reader (pins I/O, AUX1 AND AUX2 with integrated 11 kΩ pull-up
resistor to V
Symbol Parameter Test conditions Min. Typ. Max. Unit
CC
R
t
T(DI)
t
T(DO)
I
Table 12. Data lines to microcontroller (pins I/OUC, AUX1UC AND AUX2UC with integrated 11
Integrated pull-up resistor Pull-up resistor to V
PU
CC
91113kΩ
Data input transition time VIL max to VIH min. 1.2 µs
V
= 0 to VCC; CL ≤ 80 pF; 10%
Data output transition time
Current when pull-up active VOH = 0.9VCC; CL = 80 pF -1 mA
PU
VDD = 3.3 V, V
T
= 25 °C.
A
DDP
= 5 V, f
kΩ pull-up resistor to V
O
to 90%
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
DD
0.1 µs
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
V
|I
LIH
High level output voltage
OH
Low level output voltage IOL = 1 mA 0 0.3 V
OL
High level input voltage 0.7 V
IH
Low level input voltage -0.3 0.3 V
IL
High level input leakage
|
current
No DC Load 0.9 V
= V
V
IH
DD
5 and 3 V card; IOH < − 40µA 0.75 V
DD
DD
DD
VDD+0.1
VDD+0.1
VDD+0.3 V
DD
10 µA
V
V
|IL| Low level input current VIL = 0 V 600 µA
R
t
T(DI)
t
T(DO)
I
Internal pull-up resistance to
PU
V
DD
Data input transition time V
Data output transition time
Current when pull-up active VOH = 0.9VDD; CL = 30 pF -1 mA
PU
Pull-up resistor to V
to V
IL(max)
= 0 to VDD; CL < 30 pF;
V
O
IH(min)
10% to 90%
DD
91113kΩ
1.2 µs
0.1 µs
VDD = 3.3 V, V
T
= 25 °C.
A
Table 13. Internal oscillator
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
Symbol Parameter Test conditions Min. Typ. Max. Unit
Inactive mode 55 140 200 kHz
f
OSC(INT)
Frequency of internal oscillator
Active mode 2.2 2.7 3.2 MHz
12/31
ST8024 Electrical characteristics
VDD = 3.3 V, V
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to TA =
XTAL
25 °C.
OL
Output voltage in inactive
mode
I
O(inactive)
No Load 0 0.1
= 1 mA 0 0.3
Output current Inactive mode; pin grounded 0 -1 mA
RSTN to RST Delay RST Enable 2 µs
I
= 200 µA 0 0.2
Low level output voltage
High level output voltage
OL
= 20 mA (current limit) VCC-0.4 V
I
OL
I
= -200 µA 0.9V
OH
= -20 mA (current limit) 0 0.4
I
OH
CC
CC
V
CC
Rise and fall time CL = 100 pF; VCC = 5 or 3 V 0.1 µs
VDD = 3.3 V, V
T
= 25 °C.
A
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
Table 14. Reset output to card reader (pin RST)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
O(inactive)
I
O(inactive)
t
D(RSTIN-RST)
V
V
OH
t
R, tF
Table 15. Clock output to card reader (pin CLK)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
V
V
O(inactive)
I
O(inactive)
V
OL
V
OH
t
R, tF
Output voltage in inactive mode
Output current
Low level output voltage
High level output voltage
Rise and fall time CL = 30 pF (Note 4)16ns
δ Duty factor (except for f
S
R
Slew rate
I
O(inactive)
= 1 mA 0 0.3
No Load 0 0.1
CLK Inactive mode; pin
grounded
0-1mA
IOL = 200 µA 0 0.3
I
= 70 mA (current
OL
limit)
I
= -200 µA 0.9V
OH
I
= -70 mA (current
OH
limit)
)CL = 30 pF (Note 4)45 55%
XTALS
Slew up or down;
= 30 pF
C
L
-0.4 V
V
CC
CC
CC
V
CC
00.4
0.2 V/ns
V
V
V
13/31
Electrical characteristics ST8024
VDD = 3.3 V, V
T
= 25 °C (Note 5)
A
Table 16. Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5 V / 3 V
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
V
|I
LIH
|I
Input voltage low -0.3 0.3V
IL
Input voltage high 0.7V
IH
| Input leakage current high VIH = V
| Input leakage current low VIL = 0 1 µA
LIL
VDD = 3.3 V, V
DDP
= 5 V, f
DD
= 10 MHz, unless otherwise noted. Typical values are to TA =
XTAL
DD
DD
V
DD
1µA
25 °C (Note 6)
Table 17. Card presence inputs (pins PRES and PRES)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
V
IH
|I
LIH
|I
LIL
Input voltage low -0.3 0.3 V
Input voltage high 0.7 V
| Input leakage current high VIH = V
DD
DD
DD
VDD+0.3 V
5µA
| Input leakage current low VIL = 0 5 µA
V
V
V
VDD = 3.3 V, V
T
= 25 °C
A
Table 18. Interrupt output (pin OFF NMOS drain with integrated 20 kΩ pull-up resistor to VDD);
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
OL
V
OH
R
PU
Table 19. Protection and limitation
Low level output voltage IOL = 2 mA 0 0.3 V
High level output voltage IOH = -15 µA 0.75 V
Integrated pull-up resistor 20kΩ Pull-up resistor to V
VDD = 3.3 V, V
T
= 25 °C.
A
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
DD
DD
16 20 24 kΩ
V
Symbol Parameter Test conditions Min. Typ. Max. Unit
Shutdown and limitation current pin
|I
CC(SD)
I
I/O(lim)
I
CLK(lim)
I
RST(lim)
T
SD
|
V
CC
limitation current pins I/O, AUX1
and AUX2
limitation current pin CLK -70 70 mA
limitation current pin RST -20 20 mA
Shut down temperature 150 °C
90 120 mA
-15 15 mA
14/31
ST8024 Electrical characteristics
VDD = 3.3 V, V
T
= 25 °C.
A
Table 20. Timing
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
ACT
t
DE
t
3
t
5
t
debounce
Activation time (See Figure 5) 180 220 µs
Deactivation time (See Figure 7) 60 80 100 µs
Start of the windows for sending
CLK to card
End of the windows for sending
CLK to card
Debounce time pins PRES and
PRES
DDP
= 5 V, f
= 10 MHz, unless otherwise noted. Typical values are to
XTAL
(See Figure 6) 130 µs
(See Figure 6) 140 µs
(See Figure 8) 140 µs
Note: 1 All parameters remain within limits but are tested only statistically for the temperature
range. When a parameter is specified as a function of V
or VCC it means their actual value
DD
at the moment of measurement.
2 To meet these specifications, pin V
should be decoupled to CGND using two ceramic
CC
multilayer capacitors of low ESR both with values of 100 nF and 100 nF (see Figure 10).
3 Permitted capacitor values are 100 + 100 nF, or 220 nF.
4 Transition time and duty factor definitions are shown in Figure 3; δ = t
5 Pin CMDVCC
is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2
/(t1+ t2).
1
functions see Ta b le 2 0
6 Pin PRES
integrated 1.25 µA current source to GND. (PRES to V
at least one of the inputs PRES
is active LOW; pin PRES is active HIGH see Figure 8 and Figure 9; PRES has an
); the card is considered present if
DD
or PRES is active.
Figure 3. Definition of output and input transition times
15/31
Functional description ST8024
5 Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816
terminology.
5.1 Power supply
The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All
signals interfacing with the system controller are referred to V
supply the system controller. All card reader contacts remain inactive during power-on or
power-off.
, therefore VDD should also
DD
The internal circuits are maintained in the reset state until V
the duration of the internal power-on reset pulse, t
V
, an automatic deactivation of the contacts is performed.
th2
(see Figure 4). When VDD falls below
W
A DC-DC converter is incorporated to generate the 5 or 3 V card supply voltage (V
DC-DC converter should be supplied separately by V
DDP
reaches V
DD
th2
+V
hys2
and for
). The
CC
and PGND. Due to the possibility
of large transient currents, the two 100 nF capacitors of the DC-DC converter should be
located as near as possible to the IC and have an ESR less than 100 mΩ.
The DC-DC converter functions as a voltage doubler or a voltage follower according to the
respective values of V
CC
and V
(both have thresholds with a hysteresis of 100 mV).
DDP
The DC-DC converter function changes as follows:
= 5 V and V
V
CC
V
= 5 V and V
CC
V
= 3 V and V
CC
V
= 3 V and V
CC
Supply voltages V
After powering the device, OFF remains LOW until CMDVCC
During power off, OFF falls LOW when V
> 5.8 V; voltage follower
DDP
< 5.7 V; voltage doubler
DDP
> 4.1 V; voltage follower
DDP
< 4.0 V; voltage doubler.
DDP
DD
and V
may be applied to the IC in any sequence.
DDP
is set HIGH.
is below the falling threshold voltage.
DD
5.2 Voltage supervisor
5.2.1 Without external divider on pin PORADJ
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8 ms
(t
) is used internally to keep the IC inactive during power-on or power-off of the VDD supply
W
(see Figure 4).
As long as V
command lines. This state also lasts for the duration of t
higher than V
contacts is performed.
16/31
is less than V
DD
+ V
th2
hys2
th2
+ V
, the IC remains inactive whatever the levels on the
hys2
. When VDD falls below V
th2
after VDD has reached a level
W
, a deactivation sequence of the
ST8024 Functional description
Figure 4. Voltage supervisor
5.2.2 With an external divider on pin PORADJ
If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Figure 1), then the
following occurs:
– The internal threshold voltage V
hysteresis, therefore:
V
th2(ext)(rise)
V
th2(ext)(fall)
where V
– The reset pulse width t
= (1 + R1/R2) x (V
= (1 + R1/R2) x (V
= 1.25 V typ. and V
bridge
is doubled to approximately 16 ms.
W
Input PORADJ is biased internally with a pull-down current source of 4 µA which is removed
when the voltage on pin PORADJ exceeds 1 V.
is overridden by the external voltage and by the
th2
+ V
bridge
bridge - Vhys(ext)
hys(ext)
/2)
hys(ext)
/2)
= 60 mV typ.
This ensures that after detection of the external bridge by the IC during power-on, the input
current on pin PORADJ does not cause inaccuracy of the bridge voltage.
The minimum threshold voltage should be higher than 2 V. The maximum threshold voltage
may be up to V
DD
.
5.2.3 Application examples
The voltage supervisor is used as power-on reset and as supply dropout detection during a
card session. Supply dropout detection is to ensure that a proper deactivation sequence is
followed before the voltage is too low. For the internal voltage supervisor to function, the
system microcontroller should operate down to 2.35 V to ensure a proper deactivation
sequence. If this is not possible, external resistor values can be chosen to overcome the
problem.
5.3 Clock circuitry
The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a
crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be f
is made via inputs CLKDIV1 and CLKDIV2 (see Tab le 2 1).
XTAL
, 1/2 x f
XTAL
, 1/4 x f
XTAL
or 1/8 x f
. Frequency selection
XTAL
17/31
Functional description ST8024
Table 21. Clock frequency selection
CLKDIV1 CLKDIV2 f
00f
01f
11f
10f
1. The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1.
(1)
CLK
XTAL
XTAL
XTAL
XTAL
/8
/4
/2
The frequency change is synchronous, which means that during transition no pulse is
shorter than 45 % of the smallest period, and that the first and last clock pulses about the
instant of change have the correct width.
When changing the frequency dynamically, the change is effective for only eight periods of
XTAL1 after the command. The duty factor of f
depends on the signal present at pin
XTAL
XTAL1. In order to reach a 45 to 55 % duty factor on pin CLK, the input signal on pin XTAL1
should have a duty factor of 48 to 52 % and transition times of less than 5 % of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be 45 to 55 % depending on the circuit
layout and on the crystal characteristics and frequency. In other cases, the duty factor on pin
CLK is guaranteed between 45 and 55 % of the clock period.
The crystal oscillator runs as soon as the IC is powered up. If the crystal oscillator is used,
or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card as
shown in the activation sequences shown in Figure 5 and Figure 6
If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse will
be applied to the card when it is sent by the system microcontroller (after completion of the
activation sequence).
5.4 I/O transceivers
The three data lines I/O, AUX1 and AUX2 are identical.The idle state is realized by both I/O
and I/OUC lines being pulled HIGH via a 11 kΩ resistor (I/O to V
I/O is referenced to V
equal to V
. The first side of the transceiver to receive a falling edge becomes the master.
DD
An anti-latch circuit disables the detection of falling edges on the line of the other side, which
then becomes a slave. After a time delay t
on, thus transmitting the logic 0 present on the master side. When the master side returns to
logic 1, a P transistor on the slave side is turned on during the time delay t
sides return to their idle states. This active pull-up feature ensures fast LOW-to-HIGH
transitions; it is able to deliver more than 1 mA at an output voltage of up to 0.9 V
80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the
internal pull-up resistor and the load current. The current to and from the card I/O lines is
limited internally to 15 mA and the maximum frequency on these lines is 1 MHz.
CC
and I/OUC to VDD). Pin
CC
, and pin I/OUC to VDD, thus allowing operation when VCC is not
, an N transistor on the slave side is turned
d(edge)
and then both
pu
into an
CC
18/31
ST8024 Functional description
5.5 Inactive mode
After a power-on reset, the circuit enters the inactive mode. A minimum number of circuits
are active while waiting for the microcontroller to start a session:
– All card contacts are inactive (approximately 200 Ω to GND)
– Pins I/OUC, AUX1UC and AUX2UC are in the high-impedance state (11 kΩ pull-up
resistor to V
DD
)
– Voltage generators are stopped
– XTAL oscillator is running
– Voltage supervisor is active
– The internal oscillator is running at its low frequency.
5.6 Activation sequence
After power-on and after the internal pulse width delay, the system microcontroller can
check the presence of a card using the signals OFF
and CMDVCC as shown in Ta bl e 2 2.
If the card is in the reader (this is the case if PRES
microcontroller can start a card session by pulling CMDVCC
or PRES is active), the system
LOW. The following sequence
then occurs (see Figure 6):
1. CMDVCC
2. The voltage doubler is started (between t
3. V
CC
is pulled LOW and the internal oscillator changes to its high frequency (t0).
and t1).
0
rises from 0 to 5 V (or 3 V) with a controlled slope (t2 = t1 + 1.5 x T) where T is
64 times the period of the internal oscillator (approximately 25 µs).
4. I/O, AUX1 and AUX2 are enabled (t
= t1 + 4T) (these were pulled LOW until this
3
moment).
5. CLK is applied to the C3 contact of the card reader (t
6. RST is enabled (t
= t1 + 7T).
5
).
4
The clock may be applied to the card using the following sequence (see Figure 5):
1. Set RSTIN HIGH.
2. Set CMDVCC
3. Reset RSTIN LOW between t
4. RST remains LOW until t
5. After t
5
LOW.
and t5; CLK will start at this moment.
3
, when RST is enabled to be the copy of RSTIN.
5
, RSTIN has no further affect on CLK; this allows a precise count of CLK
pulses before toggling RST.
If the applied clock is not needed, then CMDVCC
case, CLK will start at t
(minimum 200 ns after the transition on I/O), and after t5, RSTIN
3
may be set LOW with RSTIN LOW. In this
may be set HIGH in order to obtain an Answer To Request (ATR) from the card.
Activation should not be performed with RSTIN held permanently HIGH
Table 22. Card presence indicator
OFF CMDVCC Indication
H H Card present
L H Card not present
19/31
Functional description ST8024
Figure 5. Activation sequence using RSTIN and CMDVCC
Figure 6. Activation sequence at t
3
20/31
ST8024 Functional description
5.7 Active mode
When the activation sequence is completed, the ST8024 will be in its active mode. Data are
exchanged between the card and the microcontroller via the I/O lines.
The ST8024 is designed for cards without V
internal non-volatile memory).
5.8 Deactivation sequence
When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit
then executes an automatic deactivation sequence by counting the sequencer back and
finishing in the inactive mode (see Figure 7):
1. RST goes LOW (t
2. CLK is held LOW (t
oscillator (approximately 25 µs).
3. I/O, AUX1 and AUX2 are pulled LOW (t
4. V
starts to fall towards zero (t14 = t10 + 1.5 x T).
CC
5. The deactivation sequence is complete at t
6. V
falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND;
UP
I/OUC, AUX1UC and AUX2UC remain at V
7. The internal oscillator returns to its lower frequency.
Figure 7. Deactivation sequence
).
10
= t10 + 0.5 x T) where T is 64 times the period of the internal
12
(the voltage required to program or erase the
PP
= t10 + T).
13
, when VCC reaches its inactive state.
de
(pulled-up via a 11 kΩ resistor).
DD
5.9 VCC generator
The VCC generator has a capacity to supply up to 80 mA continuously at 5 V and 65 mA at 3
V. An internal overload detector operates at approximately 120 mA. Current samples to the
21/31
Functional description ST8024
detector are internally filtered, allowing spurious current pulses up to 200 mA with a duration
in the order of µs to be drawn by the card without causing deactivation. The average current
must stay below the specified maximum current value. For reasons of V
a 100 nF capacitor with an ESR < 100 mΩ should be tied to CGND near to pin V
voltage accuracy,
CC
, and 100
CC
nF capacitor with the same ESR should be tied to CGND near card reader contact C1.
5.10 Fault detection
The following fault conditions are monitored:
– Short-circuit or high current on V
– Removal of a card during a transaction
–V
dropping
DD
– DC-DC converter operating out of the specified values (V
V
too high)
UP
–Overheating.
– There are two different cases (see Figure 8):
–CMDVCC
HIGH outside a card session. Output OFF is LOW if a card is not in the
card reader, and HIGH if a card is in the reader. A voltage drop on the V
detected by the supply supervisor, this generates an internal Power-on reset pulse
but does not act upon OFF
card is not powered-up.
–CMDVCC
LOW within a card session. Output OFF goes LOW when a fault condition
is detected. As soon as this occurs, an emergency deactivation is performed
automatically (see Figure 9). When the system controller resets CMDVCC
may sense the OFF
level again after completing the deactivation sequence. This
distinguishes between a hardware problem or a card extraction (OFF
again if a card is present).
CC
too low or current from
DDP
supply is
DD
. No short-circuit or overheating is detected because the
to HIGH it
goes HIGH
Depending on the type of card-present switch within the connector (normally-closed or
normally-open) and on the mechanical characteristics of the switch, bouncing may occur on
the PRES signals at card insertion or withdrawal.
There is a debounce feature in the device with an 8 ms typical duration (see Figure 8).
When a card is inserted, output OFF
goes HIGH only at the end of the debounce time.
When the card is extracted, an automatic deactivation sequence of the card is performed on
the first true/false transition on PRES or PRES
Figure 8. Behavior of OFF
, CMDVCC, PRES and V
and output OFF goes LOW.
CC
22/31
ST8024 Functional description
Figure 9. Emergency deactivation sequence (card extraction)
23/31
Application ST8024
6 Application
Figure 10. Application diagram
CLKDIV1
CLKDIV2
10µF
+5V
100nF
100nF
+3.3V
100nF
(1)
(1)
R100K
5/3V
PGND
C1 +
VDDP
C1 -
VUP
PRES
PRES
I/O
AUX2
AUX1
CGND
(3)
1
2
3
4
5
6
7
ST8024
8
9
10
11
12
13
14 15
(4)
100nF
CARD READER
(normally closed type)
(5)
100nF
C1
C5
C2
C6
C3
C7
C4
C8
K1
K2
AUX2UC
28
AUX1UC
27
I/OUC
26
XTAL2
25
XTAL1
24
OFF
23
GND
22
VDD
21
RSTIN
20
CMDVCC
19
PORADJ
18
VCC
17
RST
16
CLK
(6)
100nF
15pF
10µF
+3.3V
+3.3V
Vdd
(7)
+3.3 V POWERED
MICROCONTROLLER
(2)
R1
R2
(1) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm).
(2) ST8024 and the microcontroller must use the same V
supply.
DD
(3) Make short, straight connections between CGND, C5 and the ground connection to the capacitor.
(4) Mount one low ESR-type 100 nF capacitor close to pin V
CC
.
(5) Mount one low ESR-type 100 nF capacitor close to C1 contact.
(6) The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by
grounded tracks.
(7) Optional resistor bridge for changing the threshold of V
connected to ground.
. If this bridge is not required pin 18 should be
DD
24/31
ST8024 Package mechanical data
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
®
packages, depending on their level of environmental compliance. ECOPACK®
25/31
Package mechanical data ST8024
SO-28 mechanical data
Dim.
Min. Typ. Max. Min. Typ. Max.
A 2.65 0.104
a1 0.1 0.3 0.004 0.012
b 0.350.49 0.014 0.019
b1 0.23 0.32 0.009 0.012
C 0.5 0.020
c1 45° (typ.)
D 17.70 18.10 0.697 0.713
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 16.51 0.650
F 7.40 7.60 0.2910.300
L 0.50 1.27 0.020 0.050
S8° (max.)
mm. inch.
26/31
0016023
ST8024 Package mechanical data
TSSOP28 mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c0.09 0.20 0.004 0.0079
D 9.6 9.7 9.8 0.378 0.3820.386
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0° 8°0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
0128292B
27/31
Package mechanical data ST8024
Tape & reel SO-28 mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N60 2.362
T 30.4 1.197
Ao 10.8 11.0 0.425 0.433
Bo 18.2 18.4 0.716 0.724
Ko 2.93.1 0.114 0.122
Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
28/31
ST8024 Package mechanical data
Tape & reel TSSOP28 mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N60 2.362
T 22.4 0.882
Ao 6.8 7 0.268 0.276
Bo 10.1 10.3 0.398 0.406
Ko 1.7 1.9 0.067 0.075
Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
29/31
Revision history ST8024
8 Revision history
Table 23. Document revision history
Date Revision Changes
18-Mar-2004 4 Pag. 10, fig. 4, RSTIN ==> CLK.
27-Jun-2006 5 Add package TSSOP28.
13-Dec-2006 6 Removed: the comment point 5 on page 22.
03-Jun-2008 7 Added: Table 1 on page 1.
30-Mar-2009 8 Modified: Figure 10 on page 24.
30/31
ST8024
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