ST ST7MC1, ST7MC2 User Manual

查询ST7FMC1K2B6供应商

ST7MC1/ST7MC2

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC ,
BR USHLESS MO T OR CONTROL , FIVE TIMERS , SPI, LINSCI

PRODUCT PREVIEW

■

Memories

– 8K to 60K dual voltage FLASH Program mem-

ory or ROM with read-out protection capabili­ty. In-Application Programming and In-Circuit

Programming.
– 384 to 1.5K RAM
– HDFlash endurance: 100 cycles, data reten-

TQFP80

14 x 14

tion: 20 years

■

Clock, Re set And Supply Manag em ent

– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonat or os-

cillators an d by- pass for ext erna l cl ock, c lock

security system.
– Four power saving modes: Halt, Active-Halt,

Wait and Slow

■

Interrupt Management

– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– MCES top level interrupt pin
– 16 external interrupt lines (on 3 vectors)

■

Up to 60 I/O Ports

– up to 60 multifunctional bidirectional I/O lines
– up to 41 alternate function lines
– up to 11 high sink outputs

■

5 Timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilit ies
– Configurable window watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input, PWM and

pulse generator modes
– 8-bit PWM Auto-Reload timer with: 2 input

captures, 4 PWM outputs, output compare

and time base interrupt, external clock with

event detector

■

■

■

■

■

■

TQFP32

7 x 7

2 Communication Interfaces

– SPI synchronous serial interface
–

LIN

SCI asynchronous serial interface

Brushless Motor Control Periphe ral

– 6 high sink PWM output channels for sine-

wave or trapezoidal inverter control

– Motor safety including asynchronous emer-

gency stop and write-once registers

– 4 analog inputs for rotor position detection

(sensorless/hall/tacho/encoder)

– Permanent magnet motor coprocessor includ-

ing multiplier, programmable f ilters, blanking
windows and event counters

– Operational amplifier and comparator for c ur-

rent/voltage mode regulation and limitation

Analog peripheral

– 10-bit ADC with 16 input pins

In-circuit Debug
Instruction Set

– 8- bit D ata Ma nipulation
– 63 Basic Instruct ion s
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
– True Bit Manipulation

Development Tools

– Full hardware/software development package

Device Summary

Features ST7MC1 ST7MC2

Progra m m emo ry - by tes 8K 16K 24K 32K 48K 60K
RAM (stac k) - bytes 384 (256) 768 (256) 1024 (256 ) 1024 (256) 1536 (256 ) 1536 (256)

Peripherals
Operating

Supply vs. Frequency
Temperature Range
Package SDIP32/TQFP32 TQFP44 SDIP56/TQFP64 TQFP64 TQFP80

Watchdog, 16-bit Ti m er A, LINSCI

-

-40°C to + 85°C

/ -40°C to +125°C



, 10-bit ADC, MTC, 8-bit PWM ART, ICD

SPI, 16-bi t Timer B

4.5 to 5.5V with f

CPU

TQFP64

14 x 14

SDIP56

≤8MHz

-40°C to +85 °C

TQFP44

10 x 10

SDIP32

Rev. 2.1

April 2004 1/294

This is preliminary information on a new product now in development. Details are subject to change without notice.

1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.4 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 32

6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.2 MASKING AND PROCESSI NG FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 43

7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7

7.4 ACTI VE-HA L T AND H ALT MO DES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.3 I/O PORT IMPLEMENTAT IO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6

9.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.2 PWM AU T O-RELOA D T I M E R (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.4 SERIAL PERIPHERAL INTERFACE ( SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.5 LINSCI SERIAL COMMUNICATION IN TERFACE ( LIN MAST ER/SL AVE) . . . . . . . . . 10 3

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Table of Contents

9.6 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

9.7 OPERATIONAL AMPLIFIER (OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

9.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2

10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 7

10.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

10.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

11.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

11.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 4

11.3 6OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

11.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

11.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

11.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

11.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

11.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

11.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

11.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

11.11 COMMUNICATION INTERFA CE CHARACTERIS TI CS . . . . . . . . . . . . . . . . . . . . . . . . 266

11.12 MOTOR CONTROL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

11.13 OPERATIO NAL AMPLIF IER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

11.14 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

12 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

12.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

12.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

12.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

13 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . 284

13.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

13.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 286

13.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

13.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

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ST7MC1/ST7MC2

1 INTRODUCTION

The ST7MCx device is member of the ST7 micro­controller family designed for mid-range applica­tions with a Motor Control dedicated peripheral.

All devices are based on a common industry­standard 8-bit core, featuring an enhanced instruc­tion set and are available with FLASH, ROM or
FASTROM program memory.

Under software control, all devices can b e placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.

Figure 1. Device Block Diagram

8-BIT CO RE

RESET

V

PP

V

SS

V

DD

OSC1
OSC2

ALU

CONTROL

LVD

AVD

OSC

SCI/LIN

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro­controllers feature true bit manipulation, 8x8 un­signed multiplication and indirect addressing
modes.

The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.

PROGRAM

MEMORY

(8K - 60K Bytes)

RAM

(384 - 15 36 B ytes)

1)

PORT H

ADDRESS AND DATA BUS

PORT G

WATCHDOG

1)

1)

PH7:0

(8-bits)

PG7:0

(8-bits)

1)

PORT D

PD7:0

(8-bits)

V

AREF

V

SSA

PE5:0

(6-bits)

PF5:0

(6-bits)

On some devices only, see Table 1, “ST 7MC Devi ce Pin De scription,” on page 11

TIME R A

10-BIT ADC

1

PORT E

PORT F

1

1

TIMER B

MCC/RTC/BEEP

1

PWM ART

PORT A

PORT B

MTC VOLT INPUT

1

SPI

PORT C

MOTOR CONTROL

DEBUG MODULE

PA7:0

(8-bits)

PB7:0

(8-bits)

PC7:0
(8-bits)

MCES

1)

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1

2 PIN DESCRI PTION

Figure 2. 80-Pin TQFP 14x14 Package Pinout

VPP/ICCSEL

PE5

77

76

25

PE4 / EX T CLK_B

PE3 / ICAP1_B

75

ei2

262827

PE2 / ICAP2_B

(HS) MCO3
(HS) MCO4
(HS) MCO5

MCES

PG0
PG1
PG2

PG3
OSC1
OSC2

VSS_1
VDD_1

PWM3 / PA0

PWM2 / (HS) PA1

PWM1 / PA2

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

AIN2 / PA7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

ei1

MCO2 (HS)

80

ei1

21

MCO1 (HS)

MCO0 (HS)

78

79

222423

ST7MC1/ST7MC2

PH7

PH6

70

31

69

32

PH5

PH4

ei2

33

67

34

VDD_2

666865

35

PD7 (HS) / TDO

PD6 (HS) / RDI

36

64

37

63

38

ei0

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

61

62

39

40

PD3 / ICAP1_A / AIN13

60

PD2 / ICAP2_A / AIN12

59

PD1 (HS) / OCMP1_A

58

PD0 / OCMP2_A / AIN11

57

PH3

56

PH2

55

PH1

54

PH0

53
52

PF5 (HS)

PF4 (HS)

51

PF3 (HS) / BEEP

50

PF2 / MCO / AIN10

49

PF1 / M CZEM / AIN 9

48

PF0 / MCDEM / AIN8

47

RESET

46
45

V

DD_0

VSS_0

44

VSSA

43

VAREF

42

PC7 / MCPWMW / AIN7

41

VSS_2

PE1 / OCMP1_B

PE0 (HS) / OCMP2_B

71

727473

30

29

PG7

PG4

PG5

PG6

(HS) PC0

MCIA / PB1

MCIB / PB2

MISO / PB4

MCIC / PB3

MCVREF / PB0

(HS) 20mA high sink cap ability
eix associated external interrupt vector
* Once the MTC peripheral i s ON , the pin PC4 is con figured to an alternate function. PC4 is no l onger usable as a digita l I/ O

AIN3 / MOSI / PB5

SCK / (HS) PB6

AIN4 /SS /(HS) PB7

OAP / PC2

OAN / PC3

MCPWMV/ PC6

MCPWMU/ PC5

* MCCREF / PC4

AIN5 / MCCFI 0/ PC1

AIN6 / MCCFI 1/ OAZ

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1

ST7MC1/ST7MC2

Figure 3. 64-Pin TQFP 14x14 Package Pinout

(HS) MCO3
(HS) MCO4
(HS) MCO5

MCES

OSC1
OSC2
V

SS

_1

V

DD

PWM3 / PA0

PWM2 / (HS) PA1

PWM1 / PA2

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

AIN2 / PA7

ICCSEL

PP /

PE5 /

PE4 / EXTCLK_B

PE3 / ICAP1_B

MCO2 (HS)

MCO1 (HS)

MCO0 (HS)

V

PE2 / ICAP2_B

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1
2
3
4
5
6

_1

7
8
9
10
11
12

ei1

13
14

ei1

15
16

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

AIN3 / MOSI / PB5

/(HS) PB7

SCK / (HS) PB6

AIN4 / SS

MCVREF / PB0

MCIA / PB1

MCIB / PB2

MCIC / PB3

MISO / PB4

ei2

_2

_2

DD

PE1 / OCMP1_B

(HS) PC0

SS

PE0 (HS) / OCMP2_B

V

V

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

PD3 / ICAP1_A / AIN13

48

PD2 / ICAP2_A / AIN12

47

PD1 (HS) / OCMP1_A

46

ei0

OAP / PC2

OAN / PC3

MCPWMU / PC5

* MCCREF / PC4

AIN5 / MCCFI0 / PC1

AIN6 / MCCFI1 / OAZ

PD0 / OCMP2_A / AIN11

45

PF5 (HS)

44

PF4 (HS)

43

PF3 (HS) / BEEP

42

PF2 / MCO / AIN10

41

PF1 / MCZEM / AIN9

40

PF0 / MCDEM / AIN8

39

RESET

38

V

37

DD_0

V

SS_0

36

V

35

SSA

V

AREF

34

PC7 / MCPWMW / AIN7

33

MCPWMV/ PC6

(HS) 20mA high sink capability
eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alte rnate function. PC4 is no lo nger usable as a digital I/O

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1

Figure 4. 32-Pin SDIP Package Pinouts

ST7MC1/ST7MC2

ICCSEL / V

MCO0
MCO1
MCO2
MCO3
MCO4
MCO5
MCES
OSC1
OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

MCIA / PB1
MCIB / PB2
MCIC / PB3

PP

1
2
3
4
5
6
7
8
9
10
11

ei1

12
13
14
15
16

ei0

ei2

32

PD7 (HS) / TDO

31

PD6 (HS) / RDI

30

PD5 / AIN15 / ICCDATA

29

PD4 / EX TCLK_A / AIN14 / ICCCLK

28

PD3 / ICAP1_A / AIN13

27

PD2 / ICAP2_A / MCZEM / A IN12

26

PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

25

PD0 / OCMP2_A / MCPWMW / AIN11

24

RESET

23

V

DD_0

22

V

SS_0

21

V

AREF

20

PC4 / MCCREF *

19

OAZ / MCCFI1 / AIN6

18

PC3 / OAN

17

PC2 / OAP

(HS) 20mA high sink capability
eix associated external interrupt vector
* Once the MTC peripheral i s ON , the pin PC4 is con figured to an alternate function. PC4 is no l onger usable as a digita l I/ O

7/294

1

ST7MC1/ST7MC2

Figure 5. 56-Pin SDIP Package Pinouts

OCMP1_B / PE1

ICAP2_B / PE2

ICAP1_B / PE3

/ICCSEL

V

PP

(HS) MCO0
(HS) MCO1
(HS) MCO2
(HS) MCO3
(HS) MCO4
(HS) MCO5

MCES

OSC1
OSC2

Vss_1

Vdd_1

PWM2 / (HS) PA1

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

MCVREF / PB0

MCIA / PB1

MCIB / PB2
MCIC / PB3
MISO / PB4

AIN3 / MOSI / PB5

SCK / (HS) PB6

AIN4 / SS

/(HS) PB7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

ei1

ei1

ei2

ei0

ei2

56

PE0 (HS) / OCMP2_B
55
54
53
52
51
50
49
48
47

46

45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

_2

V

DD

_2

V

SS

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS ) / OC M P 1_A

PD0 / OCMP2_A / AIN11

PF3 (HS) / BEEP

PF1 / MCZEM / AIN9
PF0 / M CDEM / AIN8
RESET
V

DD_0

V

SS_0

V

SSA

V

AREF

PC7 / MCPWMW / AIN7
PC6 / MCPWMV

PC5 / MCPWMU

PC4 / MCCREF *
OAZ / MCCFI 1 / AI N6

PC3 / OAN
PC2 / OAP
PC1 / MCCFI0/AIN5
PC0(HS)

(HS) 20mA high sink capability
eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alte rnate function. PC4 is no lo nger usable as a digital I/O

8/294

1

Figure 6. 44-Pin TQFP Package Pinouts

MCO2 (HS)

MCO1 (HS)

(HS) MCO3
(HS) MCO4
(HS) MCO5

MCES

OSC1
OSC2

V

SS

V

DD

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

44 43 42 41 40 39 38 37 36 35 34

1
2
3
4
5
6

_1

7

_1

8
9

ei1

10
11

12 13 14 15 16 17 18 19 20 21 22

ST7MC1/ST7MC2

ICCSEL

/

PP

PE3 / ICAP1_B

MCO0 (HS)

PE2 / ICAP2_B

V

PE1 / OCMP1_B

ei2

PE0 (HS) / OC M P 2_B

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

33

ei0

PD3 / ICAP1_A / AIN13

32

PD2 / ICAP2_A / MCZEM / AIN12

31

PD1 (HS) / OCMP1_A / MCPWMV/MCDEM

30

PD0 / OCMP 2_A / A I N11

29

RESET

28

V

27

DD_0

V

26

SS_0

V

25

SSA

V

24

AREF

PC7 / MCPWMW / AIN7

23

/(HS) PB7

OAP / PC2

MCIA / PB1

MCIB / PB2

MISO / PB4

MCIC / PB3

SCK / (HS) PB6

(HS) 20mA high sink capability
eix associatedexternal interrupt vector

* Once the MTC peripheral i s ON , the pin PC4 is con figured to an alternate function. PC4 is no l onger usable as a digital I/ O

AIN3 / MOSI / PB5

OAN / PC3

* MCCREF / PC4

AIN4 / SS

AIN6 / MCC FI1 / OA Z

9/294

1

ST7MC1/ST7MC2

Figure 7. 32-Pin TQFP 7x7 Package Pinout

MCO2 (HS)

MCO1 (HS)

(HS) MCO3
(HS) MCO4
(HS) MCO5

MCES

OSC1
OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

32 31 30 29 28 27 26 25

1
2
3
4
5
6
7

ei1

8

9 10111213141516

/ICCSEL

PP

MCO0 (HS)

PD7 (HS) / TDO

V

ei2

ei0

PD4 /EXTCLK_A / AIN14 / ICCCLK

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

24

PD3 / ICAP1_A / AIN13

23

PD2 / ICAP2_A / MCZEM / AIN12

22

PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

21

PD0 / OCMP2_A / MCPWMW /AIN11

20

RESET

19

V

DD_0

18

V

SS_0

17

V

AREF

OAP / PC2

MCIA / PB1

MCIB / PB2

MCVREF / PB0

(HS) 20mA high sink capability
eix associated external interrupt vector

* Once the MTC peripheral i s ON, the pin PC4 is configur ed to an alternate function. PC4 is no lo nger usable as a digital I/O

OAN / PC3

MCIC / PB3

* MCCREF / PC4

AIN6 / MCCFI1 / OAZ

10/294

1

ST7MC1/ST7MC2

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, See “ELECTRICAL CHARACTERISTICS” on page 243.

Legend / Abbreviations for Tab le 1 :

Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output le v el: C

Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:

– Input: float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt
– Output: OD = open drain, PP = push-pull

Refer to “I/O PORTS” on page 50 for more details on the software configuration of the I/O ports.
The RESET con figur atio n of each pin is shown i n bol d wh ich i s val id as long as the devi ce is i n re set stat e.

Table 1. ST7MC Device Pin Description

= CMOS 0.3VDD/0.7VDD with Schmitt trigger

T

T

= Refer to the G&H ports Characteristics in section 11.8.1 on page 260

T

1)

, ana = analog

Pin n°

Level Port

Main

Outp

ut

OD

function

(after

reset)

PP

Alternate function

TQFP80

TQFP64

SDIP56

TQFP44

SDIP32

TQFP32

Pin Name

Input

Type

Input

Output

int

wpu

float

ana

118151MCO3 (HS) O HS XMotor Control Output 3
229262MCO4 (HS) O HS XMotor Control Output 4
3 3 10 3 7 3 MCO5 (HS) O HS X Motor Control Output 5
4411484MCES
5-----PG0 I/OT
6-----PG1 I/OT
7-----PG2 I/OT
8-----PG3 I/OT

9512595OSC1

106136106OSC2
11 7 14 7 - - V
12 8 15 8 - - V
139----PA0/PWM3 I/OC
14 10 16 - - - PA1/PWM2 I/O C
1511----PA2PWM1 I/OC

16 12 17 9 11 7

17 13 18 - - -

18 14 19 10 12 8

19 15 20 - - - PA6 / ARTIC2 I/O C
2016----PA7/AIN2 I/OC

3)

4)

4)

ss_1
dd_1

PA3/PWM0/
AIN0

PA4 (HS)/ART­CLK

PA5 / ARTIC1/
AIN1

IC

I

T
T
T
T
T

input wpd + int MTC Emergency Stop

X XXXPort G0
X XXXPort G1
X XXXPort G2
X XXXPort G3

External clock input or Resonator os­cillator inverter input

I/O Resonator oscillator inverter output

S Digital Ground Voltage

S Digital Main Supply Voltage

X X X X Port A0 PWM Output 3

HS X X X X Port A1 PWM Output 2

X X X X Port A2 PWM Output 1
X ei1 X X X Port A3

PWM Out­put 0

HS X X X X Port A4 PWM-ART External Clock

I/O C

I/O C

T
T
T

T

T

PWM-ART

I/O C

T

X ei1 X X X Port A5

Input Cap­ture 1

T
T

X ei1 X X Port A6 PWM-ART Input Capture 2
X ei1 X X X Port A7 ADC Analog Input 2

2)

ADC Ana­log Input 0

ADC Analog

Input 1

11/294

1

ST7MC1/ST7MC2

Pin n°

Level Port

Pin Name

Type

TQFP80

TQFP64

SDIP56

TQFP44

SDIP32

TQFP32

21 17 21 11 13 9 PB0/MCVREF I/O C
22 18 22 12 14 10 PB1/MCIA I/O C
23 19 23 13 15 11 PB2/MCIB I/O C
24 20 24 14 16 12 PB3/MCIC I/O C

25 21 25 15 - - PB4/MISO I/O C

26 22 26 16 - -

PB5/MOSI/
AIN3

27 23 27 17 - - PB6/SCK I/O C

28 24 28 18 - - PB7/SS

/AIN4 I/O CTHS X ei2 X X Port B7

29-----PG4 I/OT
30-----PG5 I/OT
31-----PG6 I/OT
32-----PG7 I/OT
33 25 29 - - - PC0 I/O C

5)

34 26 30 - - -

PC1/MCCFI0
/AIN5

35 27 31 19 17 13 PC2/OAP I/O C
36 28 32 20 18 14 PC3/OAN I/O C

37 29 33 21 19 15

OAZ/
MCCFI1

5)

/

Input

T
T
T
T

T

I/O C

T

T

T
T
T
T
T

I/O C

T

T
T

I/O X

AIN6

38 30 34 22 20 16 PC4/MCCREF I/O C

39 31 35 - - -

40 32 36 - - -

PC5/MCPW­MU

PC6/
MCPWMV

7)

I/O C

I/O C

T

T

T

PC7/

41 33 37 23 - -

MCPWMW7)/

I/O C

T

AIN7
42 34 38 24 21 17 V
43 35 39 25 - - V
44 36 40 26 22 18 V
45 37 41 27 23 19 V

AREF
SSA
SS_0
DD_0

46 38 42 28 24 20 RESET

I Analog Reference Voltage for ADC
S Analog Ground Voltage
S Digital Ground Voltage
S Digital Main Supply Voltage

I/O C

T

Outp

ut

OD

function

(after

reset)

PP

Alternate function

Output

float

Input

wpu

int

ana

X X X X X Port B0 MTC Voltage Reference
X X X X X Port B1 MTC Input A
X X X X X Port B2 MTC Input B
X X X X X Port B3 MTC Input C

Main

X XXXPort B4

X XXXPort B5

SPI Master In / Slave Out
Data

SPI Master
Out / Slave
In Data

ADC Ana­log Input 3

HS X ei2 X X Port B6 SPI Serial Clock

SPI Slave
Select (ac­tive low)

ADC Ana­log Input 4

X XXXPort G4
X XXXPort G5
X XXXPort G6
X XXXPort G7

HS X ei2 X X Port C0

MTC Cur-

X ei2 XXXPort C1

rent Feed­back Input

5)

0

ADC Ana­log Input 5

X ei2 X X X Port C2 OPAMP Positive Input
X ei2 X X X Port C3 OPAMP Negative Input

MTC Cur­Opamp
Output

X X XXXPort C4

rent Feed-

back Input

5)

1

MTC Current Feedback

Reference

ADC analog
Input 6

9)

X X X X Port C5 MTC PWM Output U

X X X X Port C6 MTC PWM Output V

X X XXXPort C7

MTC PWM

Output W

ADC Analog

7)

Input 7

Top priority non maskable interrupt

2)

7)

12/294

1

ST7MC1/ST7MC2

Pin n°

Level Port

Pin Name

Type

TQFP80

TQFP64

SDIP56

TQFP44

SDIP32

TQFP32

Input

PF0/

47 39 43 - - -

MCDEM6)/

I/O C

T

AIN8

6)

48 40 44 - - -

4941----

PF1/MCZEM
AIN9

PF2/MCO/

AIN10
50 42 45 - - - PF3/BEEP I/O C
5143----PF4 I/OC
5244----PF5 I/OC
53-----PH0 I/OT
54-----PH1 I/OT
55-----PH2 I/OT
56-----PH3 I/OT

/

I/O C

I/O C

T

T

T
T
T
T
T
T
T

PD0/
57 45 46 29 25 21

OCMP2_A/

MCPWMW

I/O C

7)

/

T

AIN11

PD1 (HS)/
58 46 47 30 26 22

OCMP1_A/

MCPWMV

MCDEM

6)

I/O CTHS X ei0 X X Port D1

7)

/

PD2/ICAP2_A/
59 47 48 31 27 23

MCZEM5) /

I/O C

T

AIN12

60 48 49 32 28 24

PD3/ICAP1_A/

AIN13

I/O C

T

PD4/
61 49 50 33 29 25

EXTCLK_A/IC-

I/O C

T

CCLK/AIN14

62 50 51 34 30 26
63 51 52 35 31 27 PD6/RDI I/O C

64 52 53 36 32 28 PD7/TDO I/O C
65 53 54 - - - V
66 54 55 - - - V
67-----PH4 I/OT
68-----PH5 I/OT
69-----PH6 I/OT
70-----PH7 I/OT

PD5/ICCDA-

TA/AIN15

SS_2
DD_2

I/O C

T

T
T

S Digital Ground Voltage
S Digital Main Supply Voltage

T
T
T
T

Outp

Output

float

Input

wpu

ut

int

PP

OD

ana

X X X X X Port F0

X X X X X Port F1

X X X X X Port F2

function

(after

reset)

Alternate function

MTC De­magnetiza­tion Output

MTC BEMF
Output

Main Clock
Out (f

osc

6)

/2)

ADC Ana­log Input 8

6)

ADC Ana­log Input 9

ADC Ana­log Input 10

2)

HS X X X X Port F3 Beep Signal Output
HS X XXXPort F4
HS X XXXPort F5

X XXXPort H0
X XXXPort H1
X XXXPort H2
X XXXPort H3

Timer A Output Compare 2

Main

X XXXPort D0

MTC PWM Output W

7)

ADC Analog Input 11
Timer A Output Compare 1

MTC PWM Output V

7)

MTC Demagnetization6)
Timer A Input Capture 2

X ei0 XXXPort D2

MTC BEMF

6)

ADC Analog Input 12

X ei0XXXPort D3

Timer A In­put Capture
1

ADC Analog
Input 13

Timer A External Clock
source

X ei0 XXXPort D4

ICC Clock Output
ADC Analog Input 14

X ei0 XXXPort D5

ICC Data Input

ADC Analog Input 15
HS X ei0 X X Port D6 SCI Receive Data In
HS X X X X Port D7 SCI Transmit Data Output

X XXXPort H0
X XXXPort H10
X XXXPort H2
X XXXPort H3

13/294

1

ST7MC1/ST7MC2

Pin n°

Pin Name

TQFP64

SDIP56

TQFP80

71 55 56 37 - -

7256138- ­73 57 2 39 - - PE2/ICAP2_B I/O C

74 58 3 40 - - PE3/ICAP1_B/ I/O C
7559---­7660----PE5 I/OC

77 61 4 41 1 29

78 62 5 42 2 30 MCO0 (HS) O HS X MTC Output Channel 0
79 63 6 43 3 31 MCO1 (HS) O HS X MTC Output Channel 1
80 64 7 44 4 32 MCO2 (HS) O HS X MTC Output Channel 2

TQFP44

SDIP32

TQFP32

PE0/
OCMP2_B

PE1/
OCMP1_B

PE4/
EXTCLK_B

V

/ICCSEL

PP

Level Port

Input

Type

Input

Output

I/O CTHS X X X X Port E0 Tim er B Ou t p ut C om p a r e 2

I/O C

T

T
T

I/O C

T

T

I

wpu

float

X X X X X Port E1 Timer B Output Compare 1
X X X X Port E2 Timer B Input Capture 2

X X X X X Port E3 Timer B Input Capture 1
X XXXPort E4
X X X X X Port E5

Outp

int

ana

Main

function

ut

(after

reset)

PP

OD

Must be tied low. In the programming
mode when available, this pin acts as
the programming voltage input V
ICC mode pin. See section 11.9.2 on

page 264

Alternate function

Timer B External Clock

source

2)

PP

./

Notes:

1. In the interrupt input column, “eiX ” defines the associated ex ternal in terrupt vecto r. If the weak pul l-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.

2. If two alternate func tion output s are enabled at the sa me time on a given pin (for instance, MCP WMV
and MCDEM on PD1 on TQFP32), the two signals will be ORed on the output pin.

4. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscilla­tor; se e Section 1 INTRODUCTION and Section 11.5 CLOCK AND TIMING CHARACTERISTICS for
more details.

5. MCCFI can be mapped on 2 different pins on 80 ,64 and 56-pin packages. This allows:

- either to use PC1 as a standard I/O and m ap M CCFI on AOZ with or without using the operational am­plifier (selected case after reset),

- or to map MCCFI on PC1 and use the amplifier for another function.
The mapping can be selected in MREF register of motor control cell. See section MOTOR CONTROL for

more details.

6. MCZEM is mapped on PF1 on 80, 64 and 56-pin packages and on PD2 on 44 and 32-pins.
MCDEM is mapped on PF0 on 80, 64 and 56-pin packages and on PD1 on 44 and 32-pin packages.

7. MCPWMV is mappe d on PC 6 on 8 0 and 64 -pin p ackages an d on P D1 on 44 ,and 32-p ins packag es.
MCPWMW is mapped on PC7 on 80, 64 and 44-pin packages and on PD0 on 32-pins package .

8. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up
configuration after reset. The configuration of these pads must be k ept at reset state to avoi d added cur­rent consumption.

9. Once the MTC peripheral is ON (bits CKE=1 or DAC=1 in the regist er MCRA), the pin PC4 i s configured
to an alternate function. PC4 is no longer usable as a digital I/O.

14/294

1

3 REGISTER & MEMORY MAP

ST7MC1/ST7MC2

As sho wn in Figure 8, the MCU is capable of ad­dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128
bytes of register locations, up to 2Kbytes of RAM
and up to 60Kbytes of user program memory. The
RAM space includes up to 256 byt es fo r the stack
from 0100h to 01FFh.

Figure 8. Me m ory Map

0000h

007Fh
0080h

067Fh
0680h

0FFFh

1000h

FFDFh
FFE0h

FFFFh

HW Registers

(see Table 2)

RAM

(1536/1024

768/384 Bytes)

Reserved

Program Memory

(60K, 48K, 32K, 24K, 8K)

Interrupt & Reset Vectors

(see Table 8)

0080h

00FFh

0100h

01FFh

0200h

01FFh
or 037Fh
or 047Fh
or 067Fh

The highest address by tes contain the user reset
and interrupt vectors.

IMPORTANT: Memory locations marked as “Re-
served” must never be ac ces sed. A ccessi ng a re­seved area can have unpredictable e ffects on the
device.

Short Addressing
RAM (zero page)

256 Bytes Stack

16-bit Addressing

RAM

1000h

4000h

8000h

A000h

E000h

FFFFh

60 KBytes

48 KBytes

32 KBytes
24 KBytes

8 KBytes

As sho wn in Figure 9, the MCU is capable of ad­dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128
bytes of register locations, up to 1536 bytes of
RAM and up to 60 Kbytes of user program memo-

ry. The RAM space includes up to 256 bytes for
the stack from 0100h to 01FFh.

The highest address by tes contain the user reset
and interrupt vectors.

15/294

1

ST7MC1/ST7MC2

Table 2. Hardware Register Map

Address Block

0000h
0001h

Port A

0002h
0003h

0004h

Port B

0005h

0006h
0007h

Port C

0008h
0009h

000Ah

Port D

000Bh

000Ch
000Dh

Port E

000Eh
000Fh

0010h

Port F

0011h

0012h
0013h

Port G

0014h

Register

Label

PADR
PADDR
PAOR

PBDR
PBDDR
PBOR

PCDR
PCDDR
PCOR

PDDR
PDDDR
PDOR

PEDR
PEDDR
PEOR

PFDR
PFDDR
PFOR

PGDR
PGDDR
PGOR

Register Name

Port A Data Register
Port A Data Direction Register
Port A Option Register

Port B Data Register
Port B Data Direction Register
Port B Option Register

Port C Data Register
Port C Data Direction Register
Port C Option Register

Port D Data Register
Port D Data Direction Register
Port D Option Register

Port E Data Register
Port E Data Direction Register
Port E Option Register

Port F Data Register
Port F Data Direction Register
Port F Option Register

Port G Data Register
Port G Data Direction Register
Port G Option Register

Reset

Status

1)

00h

00h
00h

1)

00h

00h
00h

1)

00h

00h
00h

1)

00h

00h
00h

1)

00h

00h
00h

1)

00h

00h
00h

1)

00h

00h
00h

Remarks

R/W
R/W

2)

R/W
R/W

R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W

R/W

2)

R/W

2)

R/W
R/W

R/W
R/W

R/W
R/W
R/W

0015h
0016h
0017h

0018h

0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh

Port H

LIN

SCI

PHDR
PHDDR
PHOR

SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCICR3
SCIERPR
SCIETPR

Port H Data Register
Port H Data Direction Register
Port H Option Register

SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Control Register 3
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register

0020h Reserved Area (1 Byte)

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

SPI

ITC

SPIDR
SPICR
SPICSR

ITSPR0
ITSPR1
ITSPR2
ITSPR3
EICR

SPI Data I/O Register
SPI Control Register
SPI Control/Status Register

Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register

00h

00h
00h

C0h

xxh
00h
xxh
00h
00h
00h
00h

xxh
0xh
00h

FFh
FFh
FFh
FFh

00h

1)

R/W
R/W
R/W

Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W

R/W
R/W
R/W

R/W
R/W
R/W
R/W
R/W

16/294

1

ST7MC1/ST7MC2

Address Block

0029h FLASH FSCR Flash Control/Status Register 00h R/W

002Ah
002Bh

002Ch
002Dh

002Eh
002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh

WATCHDOG

MCC

ADC

TIMER A

Register

Label

WWDGCR Window Watchdog Control Register 7Fh R/W
WWDGWR Window Watchdog Window Register 7Fh R/W

MCCSR
MCCBCR

ADCCSR
ADCDRMSB
ADCDRLSB

TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR

Main Clock Control / Status Register
Main Clock Controller: Beep Control Register

Control/Status Register
Data Register MSB
Data Register LSB

Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register

Register Name

Reset

Status

00h
00h

00h
00h
00h

00h
00h
xxh
xxh
xxh
80h

00h
FFh
FCh
FFh
FCh

xxh

xxh

80h

00h

Remarks

R/W
R/W

R/W
Read Only
Read Only

R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

0040h SIM SICSR System Integrity Control/Status Register 000x000x b R/W

0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h

0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh

TIMER B

TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register

00h
00h
xxh
xxh
xxh
80h

00h
FFh
FCh
FFh
FCh

xxh

xxh

80h

00h

R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

17/294

1

ST7MC1/ST7MC2

Address Block

0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h

0059h
005Ah
005Bh
005Ch
005Dh
005Eh

MTC

(page 0)

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h
006Ah

Register

Label

MTIM
MTIML
MZPRV
MZREG
MCOMP
MDREG
MWGHT
MPRSR
MIMR
MISR
MCRA
MCRB
MCRC
MPHST
MDFR
MCFR
MREF
MPCR
MREP
MCPWH
MCPWL
MCPVH
MCPVL
MCPUH
MCPUL
MCP0H
MCP0L

Register Name

Timer Counter High Register
Timer Counter Low Register
Capture Z
Capture Z
Compare C

Register

n-1

Register

n

Register

n+1

Demagnetization Register
A

Weight Register

n

Prescaler & Sampling Register
Interrupt Mask Register
Interrupt Status Register
Control Register A
Control Register B
Control Register C
Phase State Register
D event Filter Register
Current feedback Filter Register
Reference Register
PWM Control Register
Repetition Counter Register
Compare Phase W Preload Register High
Compare Phase W Preload Register Low
Compare Phase V Preload Register High
Compare Phase V Preload Register Low
Compare Phase U Preload Register High
Compare Phase U Preload Register Low
Compare Phase 0 Preload Register High
Compare Phase 0 Preload Register Low

Reset

Status

00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h

0Fh

00h
00h
00h
00h
00h
00h
00h
00h
00h

00h
0Fh
FFh

Remarks

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0050h
0051h
0052h
0053h
0054h
0055h
0056h

0057h to

006Ah

006Bh
006Ch
006Dh
006Eh
006Fh

0070h

MTC

(page 1)

DM

MDTG
MPOL
MPWME
MCONF
MPAR
MZRF
MSCR

DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L

Dead Time Generator Enable
Polarity Register
PWM Register
Configuration Register
Parity Register
Z event Filter Register
Sampling Clock Register

Reserved Area (4 Bytes)

Debug Control Register
Debug Status Register
Debug Breakpoint 1 MSB Register
Debug Breakpoint 1 LSB Register
Debug Breakpoint 2 MSB Register
Debug Breakpoint 2 LSB Register

FFh
3Fh

00h

02h

00h
0Fh

00h

00h

10h
FFh
FFh
FFh
FFh

see MTC
description

R/W
Read Only
R/W
R/W
R/W
R/W

18/294

1

ST7MC1/ST7MC2

Address Block

0074h
0075h
0076h
0077h
0078h

0079h
007Ah
007Bh

007Ch
007Dh
007Eh

007Fh OPAMP OACSR OPAMP Control/Status Registe r 00h R/W

PWM ART

Register

Label

PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR

ARTCSR
ARTCAR
ARTARR

ARTICCSR
ARTICR1
ARTICR2

Register Name

PWM AR Timer Duty Cycle Register 3
PWM AR Timer Duty Cycle Register 2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register

Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register

AR Timer Input Capture Control/Status Reg.
AR Timer Input Capture Register 1
AR Timer Input Capture Register 2

Reset

Status

00h
00h
00h
00h
00h

00h
00h
00h

00h
00h
00h

Remarks

R/W
R/W
R/W
R/W
R/W

R/W
R/W
R/W

R/W
Read Only
Read Only

Legend: x=unde fined, R/W=rea d/write
Notes:

1. The contents of the I/O p ort D R registers are read able only i n out put conf iguration. In input configura­tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

19/294

1

ST7MC1/ST7MC2

4 FLASH PROGRAM MEMORY

4.1 Introduc tion

The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu­al sectors and programmed on a Byte-by-Byte ba­sis using an external V

supply.

PP

The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).

The array matrix organ isation allows each sector
to be erased and reprogrammed wi thout affecting
other sectors.

4.2 Main Features

■

Three Flash programming modes:
– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro­grammed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro­grammed or erased without removing the de­vice from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro­grammed or erased without removing the de­vice from the appli cation board a nd wh ile the
application is running.

■

ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■

Read-out protection against piracy

■

Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 S tructure

Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flas h memory when only a
partial erasing is required.

The first two sectors have a fixed siz e of 4 K bytes
(see Figure 9). They are mapped in the upper part
of the ST7 addressing space so the reset and in­terrupt vectors are located in Sector 0 (F000h­FFFFh).

Table 3. Sectors available in Flash devices

Flash Size (bytes) Available Sectors

4K Sector 0
8K Sectors 0,1

> 8K Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a
protection against Program Memory content ex­traction and against write access to Flash memo­ry.

In Flash devices, this protection is removed by re­programming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.

Read-out protection selection depends on the de­vice type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

The Flash memory is organised in sectors and can
be used for both code and data storage.

Figure 9. Me m ory Map and Sec t or Address

4K 10K 24K 48K

1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh

20/294

8K 16K 32K 60K

2Kbytes

8Kbytes 40 Kbytes

16 Kbytes
4 Kbytes
4 Kbytes

1

24 Kbytes

FLASH
MEMORY SIZE

SECTOR 2

52 Kbytes

SECTOR 1
SECTOR 0

FLASH PROGRAM MEMORY (Cont’d)

ST7MC1/ST7MC2

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure

10). These pins are:

– RESET
– V

: device reset

: device power supply ground

SS

Figure 10. Ty pi c al IC C Interface

PROGRAMMING TOOL

APPLICATION
POWER SUPPLY

(See Note 3)

C

L2

DD

V

OSC2

OPTIONAL
(See Note 4)

C

L1

OSC1

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal i solation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented i n case another de­vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val­ues.

2. During the ICC session, the programming tool
must control the RESET
flicts between the programming tool and the appli­cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate th e appli­cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-

pin. This can lead to con-

– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/V

: programming voltage

PP

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

– V

: application board power supply (option-

DD

al, see Figure 10, Note 3)

ICC CONNECTOR

975 3

10kΩ

SS

V

ICCSEL/VPP

ICC Cabl e

1
246810

RESET

ICCCLK

HE10 CONNECTOR TYPE

ICCDATA

APPLICATION BOARD

ICC CONNECTOR

APPLICATION
RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

agement IC with open drain outpu t and pull-up re­sistor>1K, no additional com ponents are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.

3. The use of Pin 7 of the ICC con nector de pends
on the Programming Tool architecture. This pin
must be connected when using most ST Program­ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.

4. Pin 9 has to be connecte d to the OSC1 or OS ­CIN pin of the ST7 when the clock is not available
in the application or if the selec ted clock option is
not programmed in the opt ion byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.

21/294

1

ST7MC1/ST7MC2

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.

Depending on the ICP code dow nloaded in RAM,
Flash memory programming can be fully custom­ized (number of bytes to prog ram, program loca­tions, or selection serial communication interface
for downloading).

When using an STMicroelect ronics or third-party
programming tool that supp orts ICP and the spe­cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap­plication board (see Figure 10). For more details
on the pin locations, refer to the device pinout de­scription.

4.6 IAP (In-Application Pr ogrammi ng)

This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).

This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us­er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase pro­tected to allow recovery in case errors occur dur­ing the programming operation.

4.7 Related Documentation

For details on Flash program ming and I CC proto­col, refer to the ST7 Flash Programming Refer­ence Manual and to th e ST7 ICC Protocol Refer­ence Manual

.

4.8 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write
Reset Value: 0000 0000 (00h)

70

00000000

This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.

22/294

1

5 SUPPLY, RESET AND CLOCK MANAGEMENT

ST7MC1/ST7MC2

The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re­ducing the number of external components. An
overview is shown in Figure 11.

For more details, refer to dedicated parametric
section.

Main features
Figure 11. Clock, Reset and Supply Block Diagram

CLOCK SECURITY SYSTEM

OSC2

OSCILLATOR

OSC1

f

1/2

OSC

■

Reset Sequence Manager (RSM)

■

1 Crystal/ C e ra m ic res o nator osc illat o r

■

System Integrity Management (SI)

– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt

capability for mon ito ring the ma in supply

– Clock Security System (CSS) wit h the VCO of

the PLL, providing a backup safe oscillator

– Clock Detector
– PLL which can be used to multiply the fre-

quency by 2 if the clock frequency input is
8MHz

8Mhz

SYSTEM

PLL

Safeosc

INTEGRITY MANAGEMENT

f

OSC

f

MAIN CLOCK

CLK

CONTROLLER

16Mhz

lock

WITH REALTIME

CLOCK (MCC/RTC)

CKSELDIV2 OPT

f

f

CPU

MTC

RESET

V

SS

V

DD

RESETSEQUENCE

MANAGER

(RSM)

Clock Detector

SICSR, page 0

PA

AVD AVD

GE

SICSR, page 1

PA

0

GE

AVD Interrupt Request

LVD

F

IE

AUXILIARY VOLTAGE

0

RF

LOW VOLTAG E

DETECTOR

(LVD)

DETECTOR

(AVD)

VCO

LOCKPLL

EN

CSS

CSSDWDG

IE

CSS Interrupt Request

EN

RF

0

CK

0

SEL

WATCHDOG

TIMER (WDG)

23/294

1

ST7MC1/ST7MC2

5.1 OSCILLATOR

The main clock of t he ST7 can be gene rated by a
crystal or ce ramic reso nato r oscilla tor o r an exter ­nal source.

The associated hardware configurations are
shown in Table 4. Refer to the electrical character­istics section for more details.

External Clock Source

In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin wh ile the O SC2 pin is not connect­ed.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of pro­ducing a very accurate rate on the main clock of
the ST7. In this mode, the reson ator and the load
capacitors have to be placed as clo se as pos sibl e
to the oscillator pins in order to minimize output
distortion and start-up stabilization time.

This oscillator is not stopped during the RESET
phase to avoid losing time in its start-up phase.

See Electrical Characteristics for more details.

Table 4. ST7 Clock Sources

Hardware Configuration

ST7

OSC1 OSC2

External ClockCrystal/Ceramic Resonators

EXTERNAL

SOURCE

OSC1 OSC2

C

L1

CAPACITORS

ST7

LOAD

NC

C

L2

24/294

1

5.2 RESET SEQUENCE MANAGER (RSM)

ST7MC1/ST7MC2

5.2.1 Introd uc ti on

The reset sequence manager in cludes three RE­SET sources as shown in Figure 13:

■

External RESET source pulse

■

Internal LVD RESET (Low Voltage Detection)

■

Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists o f 3 p has es

as shown in F igure 12:

■

Active Phase depending on the RESET source

■

256 or 4096 CPU clock cycle delay (selected by
opti on by t e)

■

RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset st ate. T he short er
or longer clock cycle delay should be selected by
option byte to correspond to the stabilizat ion time
of the external oscillator used in the application.

Figure 13. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock
cycles.

Figure 12. RESET Sequence Phases

RESET

Active Phase

INTERNAL RE SE T

256 or 4096 CLOCK CYCLES

5.2.2 Async hronous External R ESET

The RESET
output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

ON

FETCH

VECTOR

pin

This pull-up has no fixed value but varies in ac­cordance with the input voltage. It

can be pulled
low by external circuitry to reset the dev ice. See
Electrical Characteristic section for more details.

A RESET signal originating from an external
source must have a duration of at least t

h(RSTL)in

in
order to be recognized (see Figure 14). This de­tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.

RESET

V

DD

R

ON

Filter

PULSE

GENERATOR

INTERNAL
RESET

WATCHDOG RESET
LVD RESET

25/294

1

ST7MC1/ST7MC2

RESET SEQUENCE MANAGER (Cont’d)

The RESET
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical charact eris­tics section.

5.2.3 External Power-On RESET

If the LVD is disabled by option byte, to s tart up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f

A proper reset signal for a slow rising V
can generally be provided by an ext ernal RC net ­work connected to the RESET

Figure 14. RESET Sequences

pin is an asynchronous signal which

is over the m inimum

DD

frequency.

OSC

supply

DD

pin.

V

DD

5.2.4 Internal Low Voltage Detector (LVD)
RESET

Two differen t RESET sequences caused by the in­ternal LVD circuitry can be distinguished:

■

Power-On RESET

■

Voltage Drop RESET

The device RESET
pulled low when V
V

DD<VIT-

(falling edge) as shown in Figure 14.

The LVD filters spikes on V

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

DD

g(VDD)

to

avoid parasitic resets.

5.2.5 Internal Watchdog RESET

The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.

Starting from the Watchdog counter underflow, the
device RESET
low during at least t

pin acts as an output that is pulled

w(RSTL)out

.

V

IT+(LVD)

V

IT-(LVD)

EXTERNAL
RESET
SOURCE

RESET PIN

WATCHDOG
RESET

RUN

LVD

RESET

ACTIVE PHASE

RUN

t

h(RSTL)in

EXTERNAL

RESET

ACTIVE
PHASE

WATCHDOG UNDERFLOW

RUN RUN

INTERNAL RESET (256 or 4096 T
VECTOR FETCH

WATCHDOG

RESET

ACTIVE

PHASE

t

w(RSTL)out

CPU

)

26/294

1

5.3 SYSTEM INTEGRITY MANAGEMENT (SI)

ST7MC1/ST7MC2

The System Integrity Managem ent block contains
the Low Voltage Detector (LVD), Auxiliary Voltage
Detector (AVD) and Clock Security System (CSS)
functions. It is managed by the SICSR register.

5.3.1 Low Voltage Detector (LVD)

The Low Voltage Detector funct ion (LVD) gener­ates a static reset when the V
below a V

reference value. This m eans that it

IT-

supply voltage is

DD

secures the power-up as well as the power-dow n
keeping the ST7 in reset.

The V
than the V
to avoid a parasitic reset when the MCU starts run-

reference value for a voltage drop is lower

IT-

reference value for power-on in order

IT+

ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a res et when

is below:

V

DD

– V

when VDD is rising

IT+

when VDD is falling

– V

IT-

Figure 15. Low Voltage Detector vs Reset

V

DD

The LVD function is illustrated in Figure 15.
Provided the minimum V

the oscillator frequency) is above V

value (guaranteed for

DD

, the MCU

IT-

can only be in two modes:

– under full software control
– in static safe reset

In these conditions, secure operation is always en­sured for the application without the need for ex­ternal reset hardware.

During a Low Voltage Detector Reset, the RESET
pin is held low, thus p ermitting the MCU to reset
other devices.

Notes:
The LVD allows the device to be used without any

external RESET circuitry.
The LVD is an optional func tion which can be se-

lected by option byte.

V
V

RESET

IT+
IT-

V

hys

27/294

1

ST7MC1/ST7MC2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

5.3.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) i s based on
an analog comparison between a V
V

IT+(AVD)

ply. The V
lower than the V

reference value and the VDD main sup-

reference value for f alling voltage is

IT-

reference value for rising volt-

IT+

IT-(AVD)

age in order to avoid parasitic detection (hystere­sis).

The output of the AVD comparator is directly read­able by the application software through a real
time status bit (AVDF) in t he SI CSR register. This
bit is read only.

Caution: The AVD function is active only if the
LVD is enabled through the option byte (see sec-

tion 13.1 on page 284).

5.3.2.1 Monitoring the V

Main Su pply

DD

If the AVD interrupt is enabled, an interrupt is gen­erated when the voltage crosses the V
V

IT-(AVD)

threshold (AVDF bit toggles).

and

IT+(AVD)

or

In the case of a drop i n v oltage, t he A VD i nterrupt
acts as an early warning, allowing software to shut
down safely before the LVD re sets the microcon­troller. See Fi gure 16.

The interrupt on the rising edge is used to inform
the application that the V

If the voltage rise time t

warning state is over.

DD

is less than 256 or 4096

rv

CPU cycles (depending on the reset delay select­ed by option byte), no AVD interrupt will be gener­ated when V

If t

is greater than 256 or 4096 cycles then:

rv

IT+(AVD)

is reached.

– If the AVD interrupt is enabled before the

V

IT+(AVD)

threshold is reached, then 2 AVD inter­rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.

– If the AVD interrupt is enabled after the V

IT+(AVD)

threshold is reached then only one AVD interrupt
will occur.

Figure 16. Using the AVD to Monitor V

V

DD

DD

Early Warning Interr upt

(Power has dropped, MCU not
not yet in reset)

V

V

IT+(AVD)

V

IT-(AVD)

V

IT+(LVD)

V

IT-(LVD)

AVDF bit 0 01

AVD INTERRUPT
REQUEST

IF AVDIE bit = 1

LVD RESET

hyst

INTERRUPT PROCESS

t

VOLTAGE RISE TIME

rv

INTERRUPT PROCESS

28/294

1

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

5.3.3 Clock Security System (CSS)

The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in­tegration of the security features in the applica­tions, it is based on a PLL which can provide a
backup clock. The PLL can be enabled or disabled
by option byte or by software. It requires an 8-MHz
input clock and provides a 16-MHz output clock.

5.3.3.1 Safe Oscillator Control

The safe oscillator of the CSS block is made of a
PLL.

If the clock signal disappears (due to a broken or
disconnected resonator...) the PLL continues to
provide a lower frequency, which allows the ST7 to
perform some rescue operations.

Automatically, the ST7 clock source switches back
from the saf e os cilla tor if the orig inal c lock sou rce
recovers.

5.3.3.2 Limitation detection

The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the SICSR
register. An interrupt can be gen erated if the CS­SIE bit has been previously set.
These two bits are described in the SICSR register
description.

ST7MC1/ST7MC2

5.3.4 Low Power Modes

Mode Description

WAIT

HALT

5.3.4.1 Interrupts

The CSS or AVD i nterrupt events generat e an in­terrupt if the corresponding Enable Control Bit
(CSSIE or AVDIE) is set and the interrupt mask in
the CC register is reset (RIM instruction).

Interrupt Event

CSS event detection
(safe oscillator acti­vated as main clock)

AVD event AVDF AVDIE Yes Yes

No effect on SI. CSS and AVD interrupts
cause the device to exit from Wait mode.

The CRSR register is frozen.
The CSS (including the safe oscillator) is
disabled until HALT mode is exited. The
previous CSS configuration resumes when
the MCU is woken up by an interrupt with
“exit from HALT mode” capability or from
the counter reset value when the MCU is
woken up by a RESET. The AVD remains
active, and an AVD interrupt can be used to
exit from Halt mode.

Flag

Enable

Control

Bit

Event

CSSD CSSIE Yes No

Exit
from
Wait

Exit

from

Halt

1)

Note 1: This interrupt a llows to exit fro m active­halt mode.

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ST7MC1/ST7MC2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

5.3.5 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, pa g e 0)

Read/Write
Reset Value: 000x 000x (00h)

70

AVD

PAG

E

IE

AVDFLVD

RF

CSSIECSSDWDG

0

RF

Bit 7 = PAGE SICSR Register Page Selection
This bit selects the SICSR regi ster page. It is set
and cleared by software
0: Access to SICSR register mapped in page 0.
1: Access to SICSR register mapped in page 1.

Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa­tion is automatically cleared when software enters
the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the VDIE bit is set, an interrupt request is gener­ated when the AVDF bit changes value.
0: V
1: V

DD
DD

over V

under V

IT+ (AVD)

IT-(AVD)

threshold

threshold

Bit 4 = L VDRF LVD reset flag
This bit indicates that the last Reset was generat­ed by the LVD block. It is set by hardware (LVD re­set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.

Bit 3 = Reserved, must be kept cleared.

is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the PLL is disabled (PLLE N=0), the CSS IE
bit has no effect.

Bit 1 = CSSD Clock security system detection
This bit indicates a disturbance on t he main clock
signal (f

): the clock stops (at least for a few c y-

OSC

cles). It is set by hardware and cleared by reading
the SICSR register when the original oscillator re­covers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the PLL is d isabled (PLLEN=0), t he CSSD
bit value is forced to 0.

Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat­ed by the Watchdog p eripheral. It is set by hard­ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.

RESET Sources LVDRF WDGRF

External RESET pin 0 0

Watchdog 0 1

LVD 1 X

Application notes

The LVDRF flag is not cleared when another RE­SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi­nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.

.

Bit 2 = CSSIE Clock security syst

interrupt enable

This bit enables the interrupt when a disturbance

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