ST ST7MC1, ST7MC2 User Manual

Download

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC , BR USHLESS MO T OR CONTROL , FIVE TIMERS , SPI, LINSCI

PRODUCT PREVIEW

■

Memories

– 8K to 60K dual voltage FLASH Program mem-

ory or ROM with read-out protection capability. In-Application Programming and In-Circuit

Programming. – 384 to 1.5K RAM – HDFlash endurance: 100 cycles, data reten-

TQFP80

14 x 14

tion: 20 years

■

Clock, Re set And Supply Manag em ent

– Enhanced reset system – Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability – Clock sources: crystal/ceramic resonat or os-

cillators an d by- pas s fo r ext ern al cl ock, c lock

security system. – Four power saving modes: Halt, Active-Halt,

Wait and Slow

■

Interrupt Management

– Nested interrupt controller – 14 interrupt vectors plus TRAP and RESET – MCES top level interrupt pin – 16 external interrupt lines (on 3 vectors)

■

Up to 60 I/O Ports

– up to 60 multifunctional bidirectional I/O lines – up to 41 alternate function lines – up to 11 high sink outputs

■

5 Timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilit ies – Configurable window watchdog timer – Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input, PWM and

pulse generator modes – 8-bit PWM Auto-Reload timer with: 2 input

captures, 4 PWM outputs, output compare

and time base interrupt, external clock with

event detector

■

TQFP32

7 x 7

2 Communication Interfaces

– SPI synchronous serial interface

LIN

SCI asynchronous serial interface

–

Brushless Motor Control Periphe ral

– 6 high sink PWM output channels for sine-

wave or trapezoidal inverter control

– Motor safety including asynchronous emer-

gency stop and write-once registers

– 4 analog inputs for rotor position detection

(sensorless/hall/tacho/encoder)

– Permanent magnet motor coprocessor includ-

ing multiplier, programmable f ilters, blanking windows and event counters

– Operational amplifier and comparator for c ur-

rent/voltage mode regulation and limitation

Analog peripheral

– 10-bit ADC with 16 input pins

In-circuit Debug Instruction Set

– 8- bit D ata Ma nipulation – 63 Basic Instruct ion s – 17 main Addressing Modes – 8 x 8 Unsigned Multiply Instruction – True Bit Manipulation

Development Tools

– Full hardware/software development package

Device Summary

Features ST7MC1 ST7MC2

Progra m m em ory - by tes 8K 16K 24K 32K 48K 60K RAM (stac k) - bytes 384 (256) 768 (256) 1024 (256 ) 1024 (256) 1536 (256 ) 1536 (256)

Peripherals Operating

Supply vs. Frequency Temperature Range Package SDIP32/TQFP32 TQFP44 SDIP56/TQFP64 TQFP64 TQFP80

Watchdog, 16-bit Ti m er A, LINSCI

-40°C to + 85°C

/ -40°C to +125°C



, 10-bit ADC, MTC, 8-bit PWM ART, ICD

SPI, 16-bi t Timer B

4.5 to 5.5V with f

CPU

TQFP64

14 x 14

SDIP56

≤8MHz

-40°C to +85 °C

TQFP44

10 x 10

SDIP32

April 2004 1/294

This is preliminary information on a new product now in development. Details are subject to change without notice.

Rev. 2.1

Table of Contents

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.4 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 32

6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.2 MASKING AND PROCESSI NG FLO W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 43

7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.4 ACTI VE-HALT AND HALT MO D ES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.3 I/O PORT IMPLEMENTAT IO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.2 PWM AU T O-RELOA D T I M ER (AR T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.4 SERIAL PERIPHERAL INTERFACE ( SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.5 LINSCI SERIAL COMMUNICATION IN TERFACE ( L IN MASTER/SL AVE) . . . . . . . . . 10 3

294

2/294

Table of Contents

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.6 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

9.7 OPERATIONAL AMPLIFIER (OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

9.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

10.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

10.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

11.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

11.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

11.3 6OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

11.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

11.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

11.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

11.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

11.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

11.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

11.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

11.11 COMMUNICATION INT ERFA CE CHARACTERIS TI CS . . . . . . . . . . . . . . . . . . . . . . . . 266

11.12 MOTOR CONTROL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

11.13 OPERATIO NAL AMPLIF IER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

11.14 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

12 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

12.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

12.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

12.3 SOLDERING AND GLUEABILITY INFORMATI ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

13 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . 284

13.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

13.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 286

13.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

13.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

3/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

1 INTRODUCTION

The ST7MCx device is member of the ST7 microcontroller family designed for mid-range applications with a Motor Control dedicated peripheral.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH, ROM or FASTROM program memory.

Under software control, all devices can b e placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state.

Figure 1. Device Block Diagram

8-BIT CO RE

RESET

OSC1 OSC2

ALU

CONTROL

LVD

AVD

OSC

SCI/LIN

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

PROGRAM

MEMORY

(8K - 60K Bytes)

RAM

(384 - 15 36 B ytes)

PORT H

ADDRESS AND DATA BUS

PORT G

WATCHDOG

PH7:0

(8-bits)

PG7:0

(8-bits)

PORT D

PD7:0

(8-bits)

AREF

SSA

PE5:0

(6-bits)

PF5:0

(6-bits)

On some devices only, see Table 1, “ST 7MC Devi ce Pin De scription,” on page 11

TIME R A

10-BIT ADC

PORT E

PORT F

TIMER B

MCC/RTC/BEEP

PWM ART

PORT A

PORT B

MTC VOLT INPUT

SPI

PORT C

MOTOR CONTROL

DEBUG MODULE

PA7:0

(8-bits)

PB7:0

(8-bits)

PC7:0 (8-bits)

MCES

4/294

2 PIN DESCRI PTION

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Figure 2. 80-Pin TQFP 14x14 Package Pinout

VPP/ICCSEL

PE5

PE4 / EX T CLK_B

PE3 / ICAP1_B

ei2

262827

PE2 / ICAP2_B

(HS) MCO3 (HS) MCO4 (HS) MCO5

MCES

PG0 PG1 PG2

PG3 OSC1 OSC2

VSS_1 VDD_1

PWM3 / PA0

PWM2 / (HS) PA1

PWM1 / PA2

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

AIN2 / PA7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

ei1

MCO2 (HS)

ei1

MCO1 (HS)

MCO0 (HS)

222423

ST7MC1/ST7MC2

PH7

PH6

PH5

PH4

ei2

VDD_2

666865

PD7 (HS) / TDO

PD6 (HS) / RDI

ei0

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS) / OCMP1_A

PD0 / OCMP2_A / AIN11

PH3

PH2

PH1

PH0

53 52

PF5 (HS)

PF4 (HS)

PF3 (HS) / BEEP

PF2 / MCO / AIN10

PF1 / M CZEM / AIN 9

PF0 / MCDEM / AIN8

RESET

46 45

DD_0

VSS_0

VSSA

VAREF

PC7 / MCPWMW / AIN7

VSS_2

PE1 / OCMP1_B

PE0 (HS) / OCMP2_B

727473

MCIA / PB1

MCVREF / PB0

(HS) 20mA high sink c ap ability eix associated external interrupt vector * Once the MTC peripheral i s ON , the pin PC4 is configured t o an alternate function. PC4 is no l onger usable as a digital I/ O

MCIB / PB2

PG7

PG4

PG5

PG6

(HS) PC0

MISO / PB4

MCIC / PB3

SCK / (HS) PB6

AIN3 / MOSI / PB5

AIN4 /SS /(HS) PB7

OAP / PC2

OAN / PC3

MCPWMV/ PC6

MCPWMU/ PC5

* MCCREF / PC4

AIN5 / MCCFI 0/ PC1

AIN6 / MCCFI 1/ OAZ

5/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Figure 3. 64-Pin TQFP 14x14 Package Pinout

ICCSEL

PP /

PE5 /

PE4 / EXTCLK_B

PE3 / ICAP1_B

AIN3 / MOSI / PB5

PE2 / ICAP2_B

/(HS) PB7

SCK / (HS) PB6

AIN4 / SS

MCO2 (HS)

MCO1 (HS)

MCO0 (HS)

(HS) MCO3 (HS) MCO4 (HS) MCO5

MCES

OSC1 OSC2 V

PWM3 / PA0

PWM2 / (HS) PA1

PWM1 / PA2

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

AIN2 / PA7

(HS) 20mA high sink capability eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alte rnate function. PC4 is no lo nger usable as a digital I/O

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1 2 3 4 5 6

8 9 10 11 12

ei1

13 14

ei1

15 16

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

MCIA / PB1

MCIB / PB2

MISO / PB4

MCIC / PB3

MCVREF / PB0

ei2

PE1 / OCMP1_B

PE0 (HS) / OCMP2_B

(HS) PC0

AIN5 / MCCFI0 / PC1

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS) / OCMP1_A

ei0

OAP / PC2

OAN / PC3

MCPWMU / PC5

* MCCREF / PC4

AIN6 / MCCFI1 / OAZ

PD0 / OCMP2_A / AIN11

PF5 (HS)

PF4 (HS)

PF3 (HS) / BEEP

PF2 / MCO / AIN10

PF1 / MCZEM / AIN9

PF0 / MCDEM / AIN8

RESET

DD_0

SS_0

SSA

AREF

PC7 / MCPWMW / AIN7

MCPWMV/ PC6

6/294

Figure 4. 32-Pin SDIP Package Pinouts

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

ICCSEL / V

MCO0 MCO1 MCO2 MCO3 MCO4 MCO5 MCES OSC1 OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

MCIA / PB1 MCIB / PB2 MCIC / PB3

1 2 3 4 5 6 7 8 9 10 11

ei1

12 13 14 15 16

ei0

ei2

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 / EX TCLK_A / AIN14 / ICCCLK

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / MC ZEM / AIN12

PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

PD0 / OCMP2_A / MCPWMW / AIN11

RESET

DD_0

SS_0

AREF

PC4 / MCCREF *

OAZ / MCCFI1 / AIN6

PC3 / OAN

PC2 / OAP

(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral i s ON , the pin PC4 is configured t o an alternate function. PC4 is no l onger usable as a digital I/ O

7/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Figure 5. 56-Pin SDIP Package Pinouts

OCMP1_B / PE1

ICAP2_B / PE2

ICAP1_B / PE3

/ICCSEL

(HS) MCO0 (HS) MCO1 (HS) MCO2 (HS) MCO3 (HS) MCO4 (HS) MCO5

MCES

OSC1 OSC2

Vss_1

Vdd_1

PWM2 / (HS) PA1

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

MCVREF / PB0

MCIA / PB1

MCIB / PB2 MCIC / PB3 MISO / PB4

AIN3 / MOSI / PB5

SCK / (HS) PB6

AIN4 / SS

/(HS) PB7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

ei1

ei2

ei0

ei2

PE0 (HS) / OCMP2_B 55 54 53 52 51 50 49 48 47

45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS ) / OCM P1_A

PD0 / OCMP2_A / AIN11

PF3 (HS) / BEEP

PF1 / MCZEM / AIN9 PF0 / M CDEM / AIN8 RESET V

DD_0

SS_0

SSA

AREF

PC7 / MCPWMW / AIN7 PC6 / MCPWMV

PC5 / MCPWMU

PC4 / MCCREF * OAZ / MCCFI 1 / AI N6

PC3 / OAN PC2 / OAP PC1 / MCCFI0/AIN5 PC0(HS)

(HS) 20mA high sink capability eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alte rnate function. PC4 is no lo nger usable as a digital I/O

8/294

Figure 6. 44-Pin TQFP Package Pinouts

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

MCO2 (HS)

MCO1 (HS)

(HS) MCO3 (HS) MCO4 (HS) MCO5

MCES

OSC1 OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

44 43 42 41 40 39 38 37 36 35 34

1 2 3 4 5 6

8 9

ei1

10 11

12 13 14 15 16 17 18 19 20 21 22

ST7MC1/ST7MC2

ICCSEL

PE3 / ICAP1_B

PE2 / ICAP2_B

MCO0 (HS)

PE1 / OCMP1_B

ei2

PE0 (HS) / OC M P 2_B

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

ei0

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / MCZEM / AIN12

PD1 (HS) / OCMP1_A / MCPWMV/MCDEM

PD0 / OCMP 2_A / A I N11

RESET

DD_0

SS_0

SSA

AREF

PC7 / MCPWMW / AIN7

/(HS) PB7

OAP / PC2

MCIA / PB1

MCIB / PB2

MISO / PB4

MCIC / PB3

SCK / (HS) PB6

(HS) 20mA high sink capability eix associatedexternal interrupt vector

* Once the MTC peripheral i s ON , the pin PC4 is con figured to an alternate fun ct i on. PC4 is no longer usable as a digital I/ O

AIN3 / MOSI / PB5

OAN / PC3

* MCCREF / PC4

AIN4 / SS

AIN6 / MCC FI1 / OAZ

9/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Figure 7. 32-Pin TQFP 7x7 Package Pinout

MCO2 (HS)

MCO1 (HS)

(HS) MCO3 (HS) MCO4 (HS) MCO5

MCES

OSC1 OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

32 31 30 29 28 27 26 25

1 2 3 4 5 6 7

ei1

9 10111213141516

/ICCSEL

MCO0 (HS)

PD7 (HS) / TDO

ei2

ei0

PD4 /EXTCLK_A / AIN14 / ICCCLK

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / MCZEM / AIN12

PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

PD0 / OCMP2_A / MCPWMW /AIN11

RESET

DD_0

SS_0

AREF

OAP / PC2

MCIA / PB1

MCIB / PB2

MCVREF / PB0

(HS) 20mA high sink capability eix associated external interrupt vector

* Once the MTC peripheral i s O N, the pin PC4 is co nf i gured to an alternate function. PC4 i s no longer usable as a digit al I/ O

OAN / PC3

MCIC / PB3

* MCCREF / PC4

AIN6 / MCCFI1 / OAZ

10/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

PIN DESCRIPTION (Cont’d) For external pin connection guidelines, See “ELECTRICAL CHARACTERISTICS” on page 243.

Legend / Abbreviations for Tab le 1:

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output le v el: C

Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, wpd = weak pull-down, int = i nterrupt – Output: OD = open drain, PP = push-pull

Refer to “I/O PORTS” on page 50 for more details on the software configuration of the I/O ports. The RESET con figu ratio n of each pin is shown i n bo ld wh ich is val id as long a s th e devi ce i s in r eset stat e.

Table 1. ST7MC Device Pin Description

= CMOS 0.3VDD/0.7VDD with Schmitt trigger

= Refer to the G&H ports Characteristics in section 11.8.1 on page 260

, ana = analog

Pin n°

Level Port

Main

Outp

function

(after

reset)

Alternate function

TQFP80

TQFP64

SDIP56

TQFP44

SDIP32

TQFP32

Pin Name

Input

Type

Input

Output

int

wpu

float

ana

118151MCO3 (HS) O HS XMotor Control Output 3 229262MCO4 (HS) O HS XMotor Control Output 4 3 3 10 3 7 3 MCO5 (HS) O HS X Motor Control Output 5 4411484MCES 5-----PG0 I/OT 6-----PG1 I/OT 7-----PG2 I/OT 8-----PG3 I/OT

9512595OSC1

106136106OSC2 11 7 14 7 - - V 12 8 15 8 - - V 139----PA0/PWM3 I/OC 14 10 16 - - - PA1/PWM2 I/O C 1511----PA2PWM1 I/OC

16 12 17 9 11 7

17 13 18 - - -

18 14 19 10 12 8

19 15 20 - - - PA6 / ARTIC2 I/O C 2016----PA7/AIN2 I/OC

ss_1 dd_1

PA3/PWM0/ AIN0

PA4 (HS)/ARTCLK

PA5 / ARTIC1/ AIN1

T T T T T

input wpd + int MTC Emergency Stop

X XXXPort G0 X XXXPort G1 X XXXPort G2 X XXXPort G3

External clock input or Resonator oscillator inverter input

I/O Resonator oscillator inverter output

S Digital Ground Voltage

S Digital Main Supply Voltage

X X X X Port A0 PWM Output 3

HS X X X X Port A1 PWM Output 2

X X X X Port A2 PWM Output 1 X ei1 X X X Port A3

PWM Output 0

HS X X X X Port A4 PWM-ART External Clock

I/O C

T T T

PWM-ART

I/O C

X ei1 X X X Port A5

Input Capture 1

T T

X ei1 X X Port A6 PWM-ART Input Capture 2 X ei1 X X X Port A7 ADC Analog Input 2

ADC Analog Input 0

ADC Analog

Input 1

11/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Pin n°

Level Port

Pin Name

Type

TQFP80

TQFP64

SDIP56

TQFP44

SDIP32

TQFP32

21 17 21 11 13 9 PB0/MCVREF I/O C 22 18 22 12 14 10 PB1/MCIA I/O C 23 19 23 13 15 11 PB2/MCIB I/O C 24 20 24 14 16 12 PB3/MCIC I/O C

25 21 25 15 - - PB4/MISO I/O C

26 22 26 16 - -

PB5/MOSI/ AIN3

27 23 27 17 - - PB6/SCK I/O C

28 24 28 18 - - PB7/SS

/AIN4 I/O CTHS X ei2 X X Port B7

29-----PG4 I/OT 30-----PG5 I/OT 31-----PG6 I/OT 32-----PG7 I/OT 33 25 29 - - - PC0 I/O C

34 26 30 - - -

PC1/MCCFI0 /AIN5

35 27 31 19 17 13 PC2/OAP I/O C 36 28 32 20 18 14 PC3/OAN I/O C

37 29 33 21 19 15

OAZ/ MCCFI1

Input

T T T T

I/O C

T T T T T

I/O C

T T

I/O X

AIN6

38 30 34 22 20 16 PC4/MCCREF I/O C

39 31 35 - - -

40 32 36 - - -

PC5/MCPWMU

PC6/ MCPWMV

I/O C

PC7/

41 33 37 23 - -

MCPWMW7)/

I/O C

AIN7 42 34 38 24 21 17 V 43 35 39 25 - - V 44 36 40 26 22 18 V 45 37 41 27 23 19 V

AREF SSA SS_0 DD_0

46 38 42 28 24 20 RESET

I Analog Reference Voltage for ADC S Analog Ground Voltage S Digital Ground Voltage S Digital Main Supply Voltage

I/O C

Outp

function

(after

reset)

Alternate function

Output

float

Input

wpu

int

ana

X X X X X Port B0 MTC Voltage Reference X X X X X Port B1 MTC Input A X X X X X Port B2 MTC Input B X X X X X Port B3 MTC Input C

Main

X XXXPort B4

X XXXPort B5

SPI Master In / Slave Out Data

SPI Master Out / Slave In Data

ADC Analog Input 3

HS X ei2 X X Port B6 SPI Serial Clock

SPI Slave Select (active low)

ADC Analog Input 4

X XXXPort G4 X XXXPort G5 X XXXPort G6 X XXXPort G7

HS X ei2 X X Port C0

MTC Cur-

X ei2 XXXPort C1

rent Feedback Input

ADC Analog Input 5

X ei2 X X X Port C2 OPAMP Positive Input X ei2 X X X Port C3 OPAMP Negative Input

MTC CurOpamp Output

X X XXXPort C4

rent Feed-

back Input

MTC Current Feedback

Reference

ADC analog Input 6

X X X X Port C5 MTC PWM Output U

X X X X Port C6 MTC PWM Output V

X X XXXPort C7

MTC PWM

Output W

ADC Analog

Input 7

Top priority non maskable interrupt

12/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Pin n°

Level Port

Pin Name

Type

TQFP80

TQFP64

SDIP56

TQFP44

SDIP32

TQFP32

Input

PF0/

47 39 43 - - -

MCDEM6)/

I/O C

AIN8

48 40 44 - - -

4941----

PF1/MCZEM AIN9

PF2/MCO/

AIN10 50 42 45 - - - PF3/BEEP I/O C 5143----PF4 I/OC 5244----PF5 I/OC 53-----PH0 I/OT 54-----PH1 I/OT 55-----PH2 I/OT 56-----PH3 I/OT

I/O C

T T T T T T T

PD0/ 57 45 46 29 25 21

OCMP2_A/

MCPWMW

I/O C

AIN11

PD1 (HS)/ 58 46 47 30 26 22

OCMP1_A/

MCPWMV

MCDEM

I/O CTHS X ei0 X X Port D1

PD2/ICAP2_A/ 59 47 48 31 27 23

MCZEM5) /

I/O C

AIN12

60 48 49 32 28 24

PD3/ICAP1_A/

AIN13

I/O C

PD4/ 61 49 50 33 29 25

EXTCLK_A/IC-

I/O C

CCLK/AIN14

62 50 51 34 30 26 63 51 52 35 31 27 PD6/RDI I/O C

64 52 53 36 32 28 PD7/TDO I/O C 65 53 54 - - - V 66 54 55 - - - V 67-----PH4 I/OT 68-----PH5 I/OT 69-----PH6 I/OT 70-----PH7 I/OT

PD5/ICCDA-

TA/AIN15

SS_2 DD_2

I/O C

T T

S Digital Ground Voltage S Digital Main Supply Voltage

T T T T

Outp

Output

float

Input

wpu

int

ana

X X X X X Port F0

X X X X X Port F1

X X X X X Port F2

function

(after

reset)

Alternate function

MTC Demagnetization Output

MTC BEMF Output

Main Clock Out (f

osc

/2)

ADC Analog Input 8

ADC Analog Input 9

ADC Analog Input 10

HS X X X X Port F3 Beep Signal Output HS X XXXPort F4 HS X XXXPort F5

X XXXPort H0 X XXXPort H1 X XXXPort H2 X XXXPort H3

Timer A Output Compare 2

Main

X XXXPort D0

MTC PWM Output W

ADC Analog Input 11 Timer A Output Compare 1

MTC PWM Output V

MTC Demagnetization6) Timer A Input Capture 2

X ei0 XXXPort D2

MTC BEMF

ADC Analog Input 12

X ei0XXXPort D3

Timer A Input Capture 1

ADC Analog Input 13

Timer A External Clock source

X ei0 XXXPort D4

ICC Clock Output ADC Analog Input 14

X ei0 XXXPort D5

ICC Data Input

ADC Analog Input 15 HS X ei0 X X Port D6 SCI Receive Data In HS X X X X Port D7 SCI Transmit Data Output

X XXXPort H0 X XXXPort H10 X XXXPort H2 X XXXPort H3

13/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Pin n°

Pin Name

TQFP64

SDIP56

TQFP80

71 55 56 37 - -

7256138- 73 57 2 39 - - PE2/ICAP2_B I/O C

74 58 3 40 - - PE3/ICAP1_B/ I/O C 7559---7660----PE5 I/OC

77 61 4 41 1 29

78 62 5 42 2 30 MCO0 (HS) O HS X MTC Output Channel 0 79 63 6 43 3 31 MCO1 (HS) O HS X MTC Output Channel 1 80 64 7 44 4 32 MCO2 (HS) O HS X MTC Output Channel 2

TQFP44

SDIP32

TQFP32

PE0/ OCMP2_B

PE1/ OCMP1_B

PE4/ EXTCLK_B

/ICCSEL

Level Port

Input

Type

Input

Output

I/O CTHS X X X X Port E0 Timer B Ou t p ut C om p a r e 2

I/O C

T T

I/O C

wpu

float

X X X X X Port E1 Timer B Output Compare 1 X X X X Port E2 Timer B Input Capture 2

X X X X X Port E3 Timer B Input Capture 1 X XXXPort E4 X X X X X Port E5

Outp

int

ana

Main

function

(after

reset)

Must be tied low. In the programming mode when available, this pin acts as the programming voltage input V ICC mode pin. See section 11.9.2 on

page 264

Alternate function

Timer B External Clock

source

Notes:

1. In the interrupt input column, “eiX ” defines the associated ex ternal in terrupt vecto r. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. If two alternate func tion output s are enabled at the sa me time on a given pin (for instance, MCP WMV and MCDEM on PD1 on TQFP32), the two signals will be ORed on the output pin.

4. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator; se e Section 1 INTRODUCTION and Section 11.5 CLOCK AND TIMING CHARACTERISTICS for more details.

5. MCCFI can be mapped on 2 different pins on 80 ,64 and 56-pin packages. This allows:

- either to use PC1 as a standard I/O and m ap M CCF I o n A OZ w ith or without us ing the operational amplifier (selected case after reset),

- or to map MCCFI on PC1 and use the amplifier for another function. The mapping can be selected in MREF register of motor control cell. See section MOTOR CONTROL for

more details.

6. MCZEM is mapped on PF1 on 80, 64 and 56-pin packages and on PD2 on 44 and 32-pins. MCDEM is mapped on PF0 on 80, 64 and 56-pin packages and on PD1 on 44 and 32-pin packages.

7. MCPWMV is mappe d on PC 6 on 8 0 and 64 -pin pac kages an d on P D1 on 44 ,and 32-p ins packag es. MCPWMW is mapped on PC7 on 80, 64 and 44-pin packages and on PD0 on 32-pins package .

8. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added c urrent consumption.

9. Once the MTC peripheral is ON (bits CKE=1 or DAC=1 in the regist er MCRA), the pin PC4 i s configured to an alternate function. PC4 is no longer usable as a digital I/O.

14/294

3 REGISTER & MEMORY MAP

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

As sho wn in Figure 8, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 2Kbytes of RAM and up to 60Kbytes of user program memory. The RAM space includes up to 256 byt es fo r the stac k from 0100h to 01FFh.

Figure 8. Me m ory M a p

0000h

007Fh 0080h

067Fh 0680h

0FFFh

1000h

FFDFh FFE0h

FFFFh

HW Registers

(see Table 2)

RAM

(1536/1024

768/384 Bytes)

Reserved

Program Memory

(60K, 48K, 32K, 24K, 8K)

Interrupt & Reset Vectors

(see Table 8)

0080h

00FFh

0100h

01FFh

0200h

01FFh or 037Fh or 047Fh or 067Fh

The highest address by tes contain the user re set and interrupt vectors.

IMPORTANT: Memory locations marked as “Re- served” must never be ac ces sed. A ccessi ng a reseved area can have unpredictable e ffects on the device.

Short Addressing RAM (zero page)

256 Bytes Stack

16-bit Addressing

RAM

1000h

4000h

8000h

A000h

E000h

FFFFh

60 KBytes

48 KBytes

32 KBytes 24 KBytes

8 KBytes

As sho wn in Figure 9, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 1536 bytes of RAM and up to 60 Kbytes of user program memo-

ry. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

The highest address by tes contain the user re set and interrupt vectors.

15/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Table 2. Hardware Register Map

Address Block

0000h 0001h

Port A

0002h 0003h

0004h

Port B

0005h

0006h 0007h

Port C

0008h 0009h

000Ah

Port D

000Bh

000Ch 000Dh

Port E

000Eh 000Fh

0010h

Port F

0011h

0012h 0013h

Port G

0014h

Label

PADR PADDR PAOR

PBDR PBDDR PBOR

PCDR PCDDR PCOR

PDDR PDDDR PDOR

PEDR PEDDR PEOR

PFDR PFDDR PFOR

PGDR PGDDR PGOR

Port A Data Register Port A Data Direction Register Port A Option Register

Port B Data Register Port B Data Direction Register Port B Option Register

Port C Data Register Port C Data Direction Register Port C Option Register

Port D Data Register Port D Data Direction Register Port D Option Register

Port E Data Register Port E Data Direction Register Port E Option Register

Port F Data Register Port F Data Direction Register Port F Option Register

Port G Data Register Port G Data Direction Register Port G Option Register

Reset

Status

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

Remarks

R/W R/W

R/W R/W R/W

R/W

R/W R/W

R/W R/W R/W

0015h 0016h 0017h

0018h

0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh

Port H

LIN

SCI

PHDR PHDDR PHOR

SCISR SCIDR SCIBRR SCICR1 SCICR2 SCICR3 SCIERPR SCIETPR

Port H Data Register Port H Data Direction Register Port H Option Register

SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Control Register 3 SCI Extended Receive Prescaler Register SCI Extended Transmit Prescaler Register

0020h Reserved Area (1 Byte)

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

SPI

ITC

SPIDR SPICR SPICSR

ITSPR0 ITSPR1 ITSPR2 ITSPR3 EICR

SPI Data I/O Register SPI Control Register SPI Control/Status Register

Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register

00h

00h 00h

C0h

xxh 00h xxh 00h 00h 00h 00h

xxh 0xh 00h

FFh FFh FFh FFh

00h

R/W R/W R/W

Read Only R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W

R/W R/W R/W R/W R/W

16/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Address Block

0029h FLASH FSCR Flash Control/Status Register 00h R/W

002Ah 002Bh

002Ch 002Dh

002Eh 002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

WATCHDOG

MCC

ADC

TIMER A

Label

WWDGCR Window Watchdog Control Register 7Fh R/W WWDGWR Window Watchdog Window Register 7Fh R/W

MCCSR MCCBCR

ADCCSR ADCDRMSB ADCDRLSB

TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR

Main Clock Control / Status Register Main Clock Controller: Beep Control Register

Control/Status Register Data Register MSB Data Register LSB

Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register

Reset

Status

00h 00h

00h 00h 00h

00h 00h xxh xxh xxh 80h

00h FFh FCh FFh FCh

xxh

80h

00h

Remarks

R/W R/W

R/W Read Only Read Only

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

0040h SIM SICSR System Integrity Control/Status Register 000x000x b R/W

0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h

0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

TIMER B

TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

00h 00h xxh xxh xxh 80h

00h FFh FCh FFh FCh

xxh

80h

00h

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

17/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Address Block

0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h

0059h 005Ah 005Bh 005Ch 005Dh 005Eh

MTC

(page 0)

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h 006Ah

Label

MTIM MTIML MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MCRC MPHST MDFR MCFR MREF MPCR MREP MCPWH MCPWL MCPVH MCPVL MCPUH MCPUL MCP0H MCP0L

Timer Counter High Register Timer Counter Low Register Capture Z Capture Z Compare C

n-1

n+1

Demagnetization Register A

Weight Register

Prescaler & Sampling Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Control Register C Phase State Register D event Filter Register Current feedback Filter Register Reference Register PWM Control Register Repetition Counter Register Compare Phase W Preload Register High Compare Phase W Preload Register Low Compare Phase V Preload Register High Compare Phase V Preload Register Low Compare Phase U Preload Register High Compare Phase U Preload Register Low Compare Phase 0 Preload Register High Compare Phase 0 Preload Register Low

Reset

Status

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

0Fh

00h 00h 00h 00h 00h 00h 00h 00h 00h

00h 0Fh FFh

Remarks

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

0050h 0051h 0052h 0053h 0054h 0055h 0056h

0057h to

006Ah

006Bh 006Ch 006Dh 006Eh 006Fh

0070h

MTC

(page 1)

MDTG MPOL MPWME MCONF MPAR MZRF MSCR

DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L

Dead Time Generator Enable Polarity Register PWM Register Configuration Register Parity Register Z event Filter Register Sampling Clock Register

Reserved Area (4 Bytes)

Debug Control Register Debug Status Register Debug Breakpoint 1 MSB Register Debug Breakpoint 1 LSB Register Debug Breakpoint 2 MSB Register Debug Breakpoint 2 LSB Register

FFh 3Fh

00h

02h

00h 0Fh

00h

10h FFh FFh FFh FFh

see MTC description

R/W Read Only R/W R/W R/W R/W

18/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Address Block

0074h 0075h 0076h 0077h 0078h

0079h 007Ah 007Bh

007Ch 007Dh 007Eh

007Fh OPAMP OACSR OPAMP Control/Sta tus Registe r 00h R/W

PWM ART

Label

PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR

ARTCSR ARTCAR ARTARR

ARTICCSR ARTICR1 ARTICR2

PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register

Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register

AR Timer Input Capture Control/Status Reg. AR Timer Input Capture Register 1 AR Timer Input Capture Register 2

Reset

Status

00h 00h 00h 00h 00h

00h 00h 00h

Remarks

R/W R/W R/W R/W R/W

R/W R/W R/W

R/W Read Only Read Only

Legend: x=unde fined, R/W=read/write Notes:

1. The contents of the I/O p ort D R regist ers are read able only i n out put c onf iguration. In i nput conf iguration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

19/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

4 FLASH PROG RAM MEMORY

4.1 Introduc tion

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V

supply.

The HDFlash devices can be programmed and erased off-board (plugge d in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organ isation allows each sector to be erased and reprogrammed wi thout affecting other sectors.

4.2 Main Features

■

Three Flash programming modes: – Insertion in a programming tool. In this mode,

all sectors including option bytes can be programmed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be programmed or erased without removing the device from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be programmed or erased without removing the device from the appli cation board a nd wh ile the application is running.

■

ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■

Read-out protection against piracy

■

prevent accidental programming or erasing

4.3 S tructure

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flas h memory when only a partial erasing is required.

The first two sectors have a fixed siz e of 4 K bytes (see Figure 9). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 3. Sectors available in Flash devices

Flash Size (bytes) Available Sectors

4K Sector 0 8K Sectors 0,1

> 8K Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory.

In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.

Read-out protection selection depends on the device type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

The Flash memory is organised in sectors and can be used for both code and data storage.

Figure 9. Me m ory Map and Sec t or Address

4K 10K 24K 48K

1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh

20/294

8K 16K 32K 60K

2Kbytes

8Kbytes 40 Kbytes

16 Kbytes 4 Kbytes 4 Kbytes

24 Kbytes

FLASH MEMORY SIZE

SECTOR 2

52 Kbytes

SECTOR 1 SECTOR 0

FLASH PROGRAM MEMORY (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure

10). These pins are:

– RESET – V

: device reset

: device power supply ground

Figure 10. Ty pi c al IC C Interface

PROGRAMMING TOOL

APPLICATION POWER SUPPLY

(See Note 3)

OSC2

OPTIONAL (See Note 4)

OSC1

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the ap plication, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICC session, the programming tool must control the RESET flicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the appl ication RESET circuit in this case. When using a classical RC network with R>1K or a reset man-

pin. This can lead to con-

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/V

: programming voltage

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

– V

: application board power supply (option-

al, see Figure 10, Note 3)

ICC CONNECTOR

975 3

10kΩ

ICCSEL/VPP

ICC Cabl e

1 246810

RESET

ICCCLK

HE10 CONNECTOR TYPE

ICCDATA

APPLICATION BOARD

ICC C ONNECTOR

APPLICATION RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

agement IC with open drain outpu t and pull-up resistor>1K, no additional com ponents are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC con nector de pends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4. Pin 9 has to be connecte d to the OSC1 or OS CIN pin of the ST7 when the clock is not available in the application or if t he selected clock option is not programmed in the opt ion byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

21/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code downloade d in RAM, Flash memory programming can be fully customized (number of bytes to prog ram, program locations, or selection serial communication interface for downloading).

When using an STMicroelect ronics or third-party programming tool that supp orts ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 10). For more details on the pin locations, refer to the device pinout description.

4.6 IAP (In-Application Pr ogramming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash program ming and I CC protocol, refer to the ST7 Flash Programming Reference Manual and to th e ST7 ICC Protocol Reference Manual

4.8 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 0000 0000 (00h)

00000000

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

22/294

5 SUPPLY, RESET AND CLOCK M ANAGEMENT

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11.

For more details, refer to dedicated parametric section.

Main features Figure 11. Clock, Reset and Supply Block Diagram

CLOCK SECURITY SYSTEM

OSC2

OSCILLATOR

OSC1

1/2

OSC

■

Reset Sequence Manager (RSM)

■

1 Crystal/ C e ra m ic res o nator osc illator

■

System Integrity Management (SI)

– Main supply Low voltage detection (LVD) – Auxiliary Voltage detector (AVD) with interrupt

capability for mon ito ring the m ain supply

– Clock Security System (CSS) w ith the VCO of

the PLL, providing a backup safe oscillator

– Clock Detector – PLL which can be used to multiply the fre-

quency by 2 if the clock frequency input is 8MHz

8Mhz

SYSTEM

PLL

Safeosc

INTEGRITY MANAGEMENT

OSC

MAIN CLOCK

CLK

CONTROLLER

16Mhz

lock

WITH REALTIME

CLOCK (MCC/RTC)

CKSELDIV2 OPT

CPU

MTC

RESET

RESETSEQUENCE

MANAGER

(RSM)

Clock Dete ctor

SICSR, page 0

AVD AVD

SICSR, page 1

AVD Interrupt Request

LVD

AUXILIARY VOLTAGE

LOW VOLTAG E

DETECTOR

(LVD)

DETECTOR

(AVD)

VCO

LOCKPLL

CSS

CSSDWDG

CSS Interrupt Request

SEL

WATCHDOG

TIMER (WDG)

23/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

5.1 OSCILLATOR

The main clock of the ST7 can be generated by a crystal or ce ramic reso nato r oscilla tor o r an exter nal source.

The associated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin wh ile the O SC2 pin is not c onnected.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. In this mode, the reson ator and the load capacitors have to be placed as clo se as poss ibl e to the oscillator pins in order to minimize output distortion and start-up stabilization time.

This oscillator is not stopped during the RESET phase to avoid losing time in its start-up phase.

See Electrical Characteristics for more details.

Table 4. ST7 Clock Sources

Hardware Configuration

ST7

OSC1 OSC2

External ClockCrystal/Ceramic Resonators

EXTERNAL

SOURCE

OSC1 OSC2

CAPACITORS

ST7

LOAD

24/294

5.2 RESET SEQUENCE MANAGER (RSM)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

5.2.1 Introd uct i on

The reset sequence manager in cludes three RESET sources as shown in Figure 13:

■

External RESET source pulse

■

Internal LVD RESET (Low Voltage Detection)

■

Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists o f 3 p has es

as shown in F igure 12:

■

Active Phase depending on the RESET source

■

256 or 4096 CPU clock cycle delay (selected by opti on by t e)

■

RESET vector fe tch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset st ate. T he short er or longer clock cycle delay should be selected by option byte to correspond to the stabilizat ion time of the external oscillator used in the application.

Figure 13. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock cycles.

Figure 12. RESET Sequence Phases

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

5.2.2 Async hronous External R ESET

The RESET output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

FETCH

VECTOR

This pull-up has no fixed v alue but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the dev ice. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 14). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

RESET

Filter

PULSE

GENERATOR

INTERNAL RESET

WATCHDOG RESET LVD RESET

25/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

RESET SEQUENCE MANAGER (Cont’d) The RESET

plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical charact eristics section.

5.2.3 External Power-On RESET

If the LVD is disabled by option byte, to s tart up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V level specified for the selected f

A proper reset signal for a slow rising V can generally be provide d by an ext ernal RC net work connected to the RESET

Figure 14. RESET Sequences

pin is an asynchronous signal which

is over the m inimum

frequency.

OSC

supply

pin.

5.2.4 Internal Low Voltage Detector (LVD) RESET

Two differen t RESET sequences caused by the internal LVD circuitry can be distinguished:

■

Power-On RESET

■

Voltage Drop RESET

The device RESET pulled low when V V

DD<VIT-

(falling edge) as shown in Figure 14.

The LVD filters spikes on V

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

g(VDD)

avoid parasitic resets.

5.2.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 14.

Starting from the Watchdog counter underflow, the device RESET low during at least t

pin acts as an output that is pulled

w(RSTL)out

IT+(LVD)

IT-(LVD)

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

RUN

LVD

RESET

ACTIVE PHASE

RUN

h(RSTL)in

EXTERNAL

RESET

ACTIVE PHASE

WATCHDOG UNDERFLOW

RUN RUN

INTERNAL RESET (256 or 4096 T VECTOR FETCH

WATCHDOG

RESET

ACTIVE

PHASE

w(RSTL)out

CPU

)

26/294

5.3 SYSTEM INTEGRITY MANAGEMENT (SI)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

The System Integrity Managem ent block contains the Low Voltage Detector (LVD), Auxiliary Voltage Detector (AVD) and Clock Security System (CSS) functions. It is managed by the SICSR register.

5.3.1 Low Voltage Detector (LVD)

The Low Voltage Detector funct ion (LVD) generates a static reset when the V below a V

reference value. This m eans that it

IT-

supply voltage is

secures the power-up as well as the power-dow n keeping the ST7 in reset.

The V than the V to avoid a parasitic reset when the MCU starts run-

reference value for a voltage drop is lower

IT-

reference value for power-on in order

IT+

ning and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a res et when

is below:

– V

when VDD is rising

IT+

when VDD is falling

– V

IT-

Figure 15. Low Voltage Detector vs Reset

The LVD function is illustrated in Figure 15. Provided the minimum V

the oscillator frequency) is above V

value (guaranteed for

, the MCU

IT-

can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus p ermitting the MCU to reset other devices.

Notes: The LVD allows the device to be used without any

external RESET circuitry. The LVD is an optional func tion which can be se-

lected by option byte.

V V

RESET

IT+ IT-

hys

27/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

5.3.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) i s based on an analog comparison between a V V

IT+(AVD)

ply. The V lower than the V

reference value and the VDD main sup-

reference value for f alling voltage is

IT-

reference value for rising volt-

IT+

IT-(AVD)

age in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in t he SI CSR regi ster. Th is bit is read only.

Caution: The AVD function is active only if the LVD is enabled through the option byte (see sec-

tion 13.1 on page 284).

5.3.2.1 Monitoring the V

Main Su pply

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V V

IT-(AVD)

threshold (AVDF bit toggles).

and

IT+(AVD)

In the case of a drop i n v oltage, t he AV D interrupt acts as an early warning, allowing software to shut down safely before the LVD re sets the microcontroller. See Fi gure 16.

The interrupt on the rising edge is used to inform the application that the V

If the voltage rise time t

warning state is over.

is less than 256 or 4096

CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when V

is greater than 256 or 4096 cycles then:

If t

IT+(AVD)

is reached.

– If the AVD interrupt is enabled before the

IT+(AVD)

threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached.

– If the AVD interrupt is enabled after the V

IT+(AVD)

threshold is reached then only one AVD interrupt will occur.

Figure 16. Using the AVD to Monitor V

Early Warning Interr upt

(Power has dropped, MCU not not yet in reset)

IT+(AVD)

IT-(AVD)

IT+(LVD)

IT-(LVD)

AVDF bit 0 01

AVD INTERRUPT REQUEST

IF AVDIE bit = 1

LVD RESET

hyst

INTERRUPT PROCESS

VOLTAGE RISE TIME

INTERRUPT PROCESS

28/294

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

5.3.3 Clock Security System (CSS)

The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a PLL which can provide a backup clock. The PLL can be enabled or disabled by option byte or by software. It requires an 8-MHz input clock and provides a 16-MHz output clock.

5.3.3.1 Safe Oscillator Control

The safe oscillator of the CSS block is made of a PLL.

If the clock signal disappears (due to a broken or disconnected resonator...) the PLL continues to provide a lower frequency, which allows the ST7 to perform some rescue operations.

Automatically, the ST7 clock source switches back from the safe os cilla tor if the orig ina l cloc k so urce recovers.

5.3.3.2 Limitation detection

The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the SICSR register. An interrupt can be gen erated if the CSSIE bit has been previously set. These two bits are described in the SICSR register description.

ST7MC1/ST7MC2

5.3.4 Low Power Modes

Mode Description

WAIT

HALT

5.3.4.1 Interrupts

The CSS or AVD i nterrupt events generat e an interrupt if the corresponding Enable Control Bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

Interrupt Event

CSS event detection (safe oscillator activated as main clock)

AVD event AVDF AVDIE Yes Yes

No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode.

The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET. The AVD remains active, and an AVD interrupt can be used to exit from Halt mode.

Flag

Enable

Control

Bit

Event

CSSD CSSIE Yes No

Exit from Wait

Exit

from

Halt

Note 1: This int errupt allows to exit from activehalt mode.

29/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

5.3.5 Register Description SYSTEM INTEGRITY (SI) CONTROL/ STAT U S RE GI STER (SICSR, page 0)

Read/Write Reset Value: 000x 000x (00h)

AVD

PAG

AVDFLVD

CSSIECSSDWDG

Bit 7 = PAGE SICSR Register Page Selection This bit selects the SICSR regi ster page. It is set and cleared by software 0: Access to SICSR register mapped in page 0. 1: Access to SICSR register mapped in page 1.

Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the VDIE bit is set, an interrupt request is generated when the AVDF bit changes value. 0: V 1: V

DD DD

over V

under V

IT+ (AVD)

IT-(AVD)

threshold

Bit 4 = L VDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

Bit 3 = Reserved, must be kept cleared.

is detected by the Clock Security System (CSSD bit set). It is set and cleared by software. 0: Clock security system interrupt disabled 1: Clock security system interrupt enabled When the PLL is disabled (PLLE N=0), the CSS IE bit has no effect.

Bit 1 = CSSD Clock security system detection This bit indicates a disturbance on t he main clock signal (f

): the clock stops (at least for a few c y-

OSC

cles). It is set by hardware and cleared by reading the SICSR register when the original oscillator recovers. 0: Safe oscillator is not active 1: Safe oscillator has been activated When the PLL is d isabled (PLLEN=0), t he CSSD bit value is forced to 0.

Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog p eripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.

RESET Sources LVDRF WDGRF

External RESET pin 0 0

Watchdog 0 1

LVD 1 X

Application notes

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep tra ce of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.

Bit 2 = CSSIE Clock security syst This bit enables the interrupt when a disturbance

30/294

interrupt enable

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

SYSTEM INTEGRITY (SI) CONTROL/ STAT U S RE GI STER (SICSR, page 1)

Reset Value: 00000000 (00h)

Bit 3 = PLLEN PLL Enable This bit enables the P LL an d t he clo ck dete ctor. It

PA GE

VCOENLOCKPLL

CK-

SEL

is set and cleared by software. 0: PLL and Clock Detector (CKD) disabled 1: PLL and Clock Detector (CKD) enabled

Notes:

Bit 7 = PAGE SICSR Register Page Selection This bit selects the SICSR regi ster page. It is set and cleared by software

1. During ICC session, this bit is set to 1.

2. PLL cannot be disabled if PLL clock source is

selected (CKSEL= 1). 0: Access to SICSR register mapped in page 0. 1: Access to SICSR register mapped in page 1.

Bit 2 = Reserved, must be kept cleared.

ST7MC1/ST7MC2

Bit 6 = Reserved, must be kept cleared.

Bit 5 = VCOEN VCO Enable This bit is set and cleared by software. 0: VCO (Voltage Controlled Oscillator) connected

to the output of the PLL charge pump (default mode), to obtain a 16-MHz output frequency (with an 8-MHz input frequency).

1: VCO tied to ground in order to obtain a 10-MHz

frequency (f

vco

)

Notes:

1. During ICC session, this bit is set to 1 in order to have an internal frequency which does not depend on the input clock. Then, it can be reset in order to run faster with an external oscillator.

Bit 4 = LOCK PLL Locked This bit is read only. It is set by hardware. It is set automatically when the PLL reache s its ope rating frequency. 0: PLL not locked 1: PLL locked

Bit 1 = CKSELClock Source Selection

This bit selects t he clock so urce: oscill ator clo ck or

clock from the PLL. It is set and cleared by soft-

ware. It can also be set by option byte (PLL opt)

0: Oscillator cloc k selecte d

1: PLL clock selected

Notes:

1. During ICC session, this bit is set to 1. Then,

CKSEL can be reset in order to run with f

OSC

2. Clock from the PLL cannot be selected if the

PLL is disabled (PLLEN =0)

3. If the clock source is selected by PLL option bit,

CKSEL bit selection has no effect.

Bit 0 = Reserved, must be kept cleared.

31/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

5.4

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)

The Main Clock Controller consists of three di fferent functions:

■

a programmable CPU clock prescaler

■

a clock-out signal to supply external devices

■

a real time clock timer with interrupt capability

Each function can be used independently and simultaneously.

5.4.1

Programmable CPU Clock Prescaler

The programmable CP U clock prescaler supplies the clock for the ST7 CPU and its inte rnal peripherals. It manages SLOW power saving mode (See

Section 7.2 SLOW MODE for more details).

The prescaler s elect s th e f

main clock frequen-

CPU

cy and is controlled by three bits in the MCCSR register : CP[1 :0 ] a n d SMS.

5.4.2

Clock-out Capability

The clock-out capability is an alternat e function of an I/O port pin that outputs a f

Figure 17.

Main Clock Controller (MCC/RTC) Block Diagram

clock to drive

OSC2

MCCBCR

external devices. It is controlled by the M C O bit in

the MCCSR register.

CAUTION: When selected, the clock out pin sus-

pends the clock during ACTIVE-HALT mode.

5.4.3

Real Time Clock Timer (RTC)

The counter of the real time clock t imer allows an

interrupt to be generated based on an accurate

real time clock. Four different t ime bas es depend-

ing directly on f

functionality is controlled by four bits of the MCC-

are available. The whole

OSC2

SR register: TB[ 1 :0 ], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set),

the ST7 enters ACTIVE-HALT mode when the

HALT instruction is executed. See Section 7.4 AC-

TIVE-HALT AND HALT MODES for more details.

5.4.4

Beeper

The beep function is controlled by the MCCBCR

on the BEEP pin (I/O po r t alternate function).

BC1 BC0

BEEP SIG NAL

GENERATO R

BEEP

MCO

32/294

CLK

DIV 2

MCCSR

OSC2

DIV128

MCO

DIV 2, 4, 8, 16

RTC

COUNTER

SMS

CP0 TB1 TB0 OIE OIF

DIV 2

ADC

MCC/RTC INTERRUPT (AND TO MTC

PERIPHERAL)

CPU

MTC

CPU CLOCK

TO CPU AND

PERIPHERALS

TO MOTOR

CONTROL

PERIPHERAL

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

5.4.5

Low Power Modes

Mode Description

No effect on MCC/RTC peripheral.

WAIT

ACTIVEHALT

HALT

MCC/RTC interrupt cause the device to exit from WAIT mode.

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode.

MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit from HALT” capability.

Bit 6:5 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is

applied in the different slow modes. Their action is

conditioned by the setting of the SMS bit . These

two bits are set and cleared by software

in SLOW mode CP1 CP0

CPU

f f f

OSC2

ST7MC1/ST7MC2

/ 2 0 0

OSC2

/ 4 0 1

OSC2

/ 8 1 0

OSC2

/ 16 1 1

5.4.6

Interrupts

The MCC/RTC interrupt even t generat es an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).

Interrupt Event

Time base overflow event

Event

Enable

Control

Flag

OIF OIE Yes No

Bit

Exit from Wait

Exit

from

Halt

Note: The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

5.4.7

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write Reset Value: 0000 0000 (00h

)

Bit 4 = SMS Slow mode select This bit is set and cleared by software.

0: Normal mode. f 1: Slow mode. f See Section 7.2 SLOW MODE and Section 5.4

CPU

OSC2

is given by CP1, CP0

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) for more de-

tails.

Bit 3:2 = TB[1:0] Time base control These bits select the programmabl e divider time

base. They are set and cleared by software.

Counter

Prescaler

16000 4ms 2ms 0 0 32000 8ms 4ms 0 1 80000 20ms 10ms 1 0

200000 50ms 25ms 1 1

OSC2

Time Base

=4MHz f

OSC2

A mod ificatio n of th e time bas e is taken into a ccount at the end of the current period (previously

set) to avoid an unwanted time shift. This allows to use this time base as a real time clock.

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

Bit 7 = MCO Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

OSC2

on I/O

port)

Note: To reduce power consumption, the MCO

Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to e xit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving

mode

function is not active in ACTIVE-HALT mode.

=8MHz

TB1 TB0

33/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscilla t o r in t e rrupt flag

This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main osc illator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached

CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.

MCC BEEP CONTROL REGISTER (MCCBCR)

Read/Write Reset Value: 0000 0000 (00h)

0000

Bit 7:4 = Reserved, must be kept cleared. Bit 3 = ADSTS A/D Converter Sample Time

Stretch

This bit is set and cleared by software to enable or disable the A/D Converter sample time stretch feature. 0: AD sample time stretch disabled (for standard

impedance analog inputs)

1 AD sample time stretch enabled (for high imped-

ance analog inputs)

Bit 2 = ADCIE A/D Converter Interrupt Enable This bit is set and cleared by software to enable or disable the A/D Converter interrupt. 0: AD Interrupt disabled

AD-

STS

ADC

BC1 BC0

1 AD Interrupt enabled

Bit 1:0 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability.

BC1 BC0 B eep mode with f

00 Off 01 ~2-KHz 10 ~1-KHz 1 1 ~500-Hz

The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the consumption.

Table 5. Main Clock Controller Register Map and Reset Values

Address

(Hex.)

0040h

002Ch

002Dh

Label

SICSR, page0

Reset Value

SICSR, page1

Reset Value

MCCSR

Reset Value

MCCBCR

Reset Value0000

76543210

PAGE

MCO

VDIE

CP1

VDF0LVDRF

VCOEN0LOCKxPLLEN

CP0

SMS

CFIE

TB1

ADSTS0ADCIE

TB0

=8MHz

OSC2

Output

Beep signal

~50% duty cycle

CSSD0WDGRF

CKSEL

OIE

BC1

OIF

BC0

34/294

6 INTERRUPTS

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

6.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■

Hardware interrupts

■

Software interrupt (TRAP)

■

Nested or concurrent interrupt management with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels – Up to 16 interrupt vectors fixed by hardware – 2 non maskable events: RESET, TRAP – 1 maskable top level event: MCES

This interrupt management is based on:

– Bit 5 and bit 3 of the CPU CC register (I1:0), – Interrupt software priority registers (ISPRx), – Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.

6.2 MASKI NG AN D PROC ESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of

each interrupt vector (see Table 6). The processing flow is shown in Figure 18

When an interrupt request has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Inter rupt M a pping ” table for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be rest ored from the stack and the program in the previous level will resume.

Table 6. Interrupt Software Priority Levels

Interrupt software priority Level I1 I0

Level 0 (main) Low Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

High

Figure 18. Int errupt Proces s in g Fl ow c hart

RESET

RESTORE PC, X, A, CC

FROM STACK

PENDING

INTERRUPT

FETCH NEX T

INSTRUCTION

“IRET”

EXECUTE

INSTRUCTION

THE INTERRUPT STAYS PENDING

MCES

Interrupt has th e sam e or a

lower software priority

than current one

STACK PC, X, A, CC

LOA D I1:0 FROM IN TERR UPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

I1:0

software priority

than current one

Interrupt has a higher

35/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

INTERRUPTS (Cont’d) Servicing Pe nding Interrup t s

As several interrupts can b e pending at the sam e time, the interrupt to be taken into account is determined by the following two-step process:

– the highest software priority interrupt is serviced, – if several interrupts have the same software pri-

ority then the interrupt with the highest hardware priority i s serv ice d first.

Figure 19 describes this decision process.

Figure 19. Priority Decision Process

PENDING

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Different

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one is not. This allows the previ ous process to succeed with only one interrupt. Note 2: RESET, TRAP and MCES can be considered as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (ex ternal or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I 0 bits of the CC register (see

Figure 18). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding vector is loaded in the PC re gister and the I1 an d I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit HALT mode.

■

TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the fl owchart in Figure 18 as a MCES t op level interrupt.

■

RESET

The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vect or sourc es can be servi ced if the corresponding interrupt is e nabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.

■

MCES (MTC Emergency Stop)

This hardware interrupt occurs when a specific edge is detected on the dedicated MCES pin or when an error is detected by the micro in the motor speed measurement.

■

External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensit iv ity is software selectab le through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a grou p connected to the same interrupt line are selected simultaneously, these w ill be log i cally ORed.

■

Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT m ode except those mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

36/294

INTERRUPTS (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

6.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present whi le exiting HALT mode, the first one serviced can only be an interrupt with e xit from HALT mo de capability and it is selected through the same decision process shown in Figure 19.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

Figure 20. Con c u rre n t Int errupt Manag e m ent

IT1

IT3

MCES

IT0

IT1

RIM

IT2

IT1

IT4

HARDWARE PRIORITY

MAIN

11 / 10

6.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 20 and Figure 21 show two different interrupt management modes. The first is called concurrent mode and do es not allow an interrupt to be interrupted, unlike the nested mode in

Figure 21. The interrupt hardware priority is given

in this order from the l owest to th e hi ghest: M A IN, IT4, IT3, IT2, IT1, IT0, MCES. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

SOFTWARE PRIORITY LEVEL

IT0

IT3

IT4

MAIN

3 3 3 3 3 3 3/0

11 11 11 11 11 11

USED STACK = 10 BYTES

Figure 21. Nested Interrupt Management

IT2

IT1

IT4

IT1

IT2

RIM

HARDWARE PRIORITY

MAIN

11 / 10

IT4

IT3

MCES

IT0

IT4

IT0

IT3

IT1

SOFTWARE PRIORITY LEVEL

IT2

MAIN

I1 I0

3 3 2 1 3 3 3/0

11 11 00 01 11 11

USED STACK = 20 BYTES

37/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

INTERRUPTS (Cont’d)

6.5 INTERRUPT REGISTER DESCRIPTION

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)

CPU CC REGISTER INTERRUPT BITS

Read/Write Reset Value: 111x 1010 (xAh)

11I1 H I0 NZC

Bit 5, 3 = I1, I0 Softwar e Interr u p t Prio rity These two bits indicate the current interrupt soft-

ware priority.

Interrupt Software Priority Level I1 I0

Level 0 (main) Low Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable*) 1 1

High

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also set/cleared by sof tw are wi th th e RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction Set” table).

*Note: M CES, TRAP and RESET events can interrupt a level 3 program.

Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software priority of each interrupt vector.

– Each interrupt vecto r (except RESET and TRAP)

has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)

The RESET, TRAP and MCES vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

*Note: Bits in the ISPRx registers which correspond to the MCES can be read and written but they are not significant in the interrupt process management.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

38/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

INTERRUPTS (Cont’d)

Table 7. Dedicated Interrupt Instruction Set

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C JRM Jump if I1:0=11 (level 3) I1:0=11 ? JRNM Jump if I1:0<>11 I1:0<>11 ? POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0 SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

39/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

INTERRUPTS (Cont’d) Table 8. Interrupt Mapping

N°

0MCES

1 2 ei0 External interrupt port

3 ei1 External interrupt port yes FFF4h-FFF5h 4 ei2 External interrupt port yes FFF2h-FFF3h 5 6 Event R or Event Z no FFEEh-FFEFh 7 Event C or Event D no FFECh-FFEDh 8 SPI SPI peripheral interru pts SPICS R yes FFEA h-FFE Bh

9 TIMER A TIMER A peripheral interrupts TASR no FFE8h-FFE9h 10 TIMER B TIMER B peripheral interrupts TBSR no FFE6h-FFE7h 11 LIN

12 13 PWM ART PWM ART overflow interrupt ARTCSR no FFE0h-FFE1h

Source

Block

RESET Reset

TRAP Software interrupt no FFFCh-FFFDh

Motor Control Emergency Stop or Speed error interrupt

MCC/RTC

CSS

MTC

SCI

AVD/

ADC

Main clock controller time base interrupt Safe oscillator activation interrupt

Event U or Current Loop or Sampling Out

LIN

SCI

Auxiliary Voltage detector interrupt ADC End of conversion interrupt

Description

Peripheral interrupts SCISR no FFE4h-FFE5h

Label

N/A

MISR

MCRC

MCCSR

SICSR

N/A

MISR

SICSR

ADCSR

Priority

Order

Highest

Priority

Lowest

Priority

Exit from

HALT

yes FFFEh-FFFFh

no FFFAh-FFFBh

yes FFF8h-FFF 9h yes FFF6h-FFF 7h

no FFF0h-FFF1h

yes FFE2h-FFE3h

Address

Vector

Note 1. Va lid for HALT and ACTIVE-HA LT modes except for the MCC/ RTC or CSS interrupt source which exits from

ACTIVE-HALT mode only.

40/294

INTERRUPTS (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

6.6 EXTERNAL INTERRUPTS

ST7MC1/ST7MC2

The pending interrupts are cleared writing a different value in the ISx[1:0], IPA or IPB bits of the EICR.

Note: External interrupts are masked when an I/O (configured as input interrupt) of the same interrupt vector is forced to V

6.6.1 I/O PORT INTERRUPT SENSITIVITY

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 22). This control allows to have up to 4 fully independent external interrupt source sensitivities.

Each external interrupt sou rce can be generated on four (or five) different events on the pin:

■

Falling edge

■

Rising edge

■

Falling and rising edge

■

Falling edge and low level

■

Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3).

41/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

INTERRUPTS (Cont’d) Figure 22. External Interrupt Con tr ol bits

PORT D [6:4] INTERRUPTS

PDOR.6

PDDDR.6

PD6

IPA BIT

PORT D [3:1] INTERRUPTS

PDOR.3

PDDDR.3

PD3

PORT A [7:3] INTERRUPTS

PAOR.7

PADDR.7

PA7

EICR

IS30 IS31

SENSITIVITY

CONTROL

EICR

IS30 IS31

SENSITIVITY

CONTROL

EICR

IS20 IS21

SENSITIVITY

CONTROL

PD6 PD5

PD4

PD3 PD2 PD1

PA7 PA6 PA5

PA3

ei0 INTERRUPT SOURCE

ei1 INTER RUPT SOURCE

PORT C [3:1] INTERRUPTS

PCOR.3

PCDDR.3

PC3

IPB BIT

PORT C0, PB[7:6] INTERRUPTS

PCOR.0

PCDDR.0

PC0

42/294

EICR

IS10 IS11

SENSITIVITY

CONTROL

EICR

IS10 IS11

SENSITIVITY

CONTROL

PC0 PB7 PB6

PC3 PC2

PC1

ei2 INTER RUPT SOURCE

ei2 INTERRUPT S O URCE

INTERRUPTS (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

6.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

ST7MC1/ST7MC2

Read/Write Reset Value: 0000 0000 (00h)

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 5 = IPB Interrupt polarity for port C This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be set and cleared

IS11 IS10 IPB IS21 IS20 IS31 IS30 IPA

by software only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 7:6 = IS1[1:0] ei2 sensitivity The interrupt sensitivity, defined using the IS1[1:0]

0: No sensitivity inversion 1: Sensitivity inversion

bits, is applied to the following external interrupts:

- ei2 (port C3..1)

IS11 IS10

00 0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only 1 1 Rising and falling edge

External Interrupt Sensit ivity

IPB bit =0 IPB bit =1

Falling edge &

low level

Rising edge

& high level

- ei2 (port C0, B7..6)

IS11 IS1 0 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

Bit 4:3= IS2[1:0] ei1sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:

- ei1 (port A 3 , A5... A7 )

IS21 IS20 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

Bit 2:1= IS3[1:0] ei0sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:

43/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

EXTERNAL INTERRUPT CONTROL REGISTER (EICR) (Cont’d)

- ei0 (port D5..3)

IS31 IS30

00 0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only 1 1 Rising and falling edge

External Interrupt Sensit ivity

IPA bit =0 IPA bit =1

Falling edge &

low level

Rising edge

& high level

- ei0 (port D2..0)

IS31 IS3 0 External Interrupt Sensitivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 0= IPA Interrupt polarity for port A This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion

44/294

INTERRUPTS (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Table 9. Nested Interrupts Register Map and Reset Values

ST7MC1/ST7MC2

Address

(Hex.)

0024h

0025h

0026h

0027h

0028h

Label

ISPR0

Reset Value

ISPR1

Reset Value

ISPR2

Reset Value

ISPR3

Reset Value

EICR

Reset Value

76543210

ei1 ei0 MCC + SI MCES

I1_3

MTC C/D MTC R/Z MTC U/CL ei2

I1_7

I1_11

I1_15

IS11

I0_3

I0_7

SCI TIMER B TIMER A SPI

I0_11

I0_15

IS10

I1_2

I1_6

I1_10

I1_14

IPB

I0_2

I0_6

I0_10

I0_14

IS21

I1_1

I1_5

I1_9

PWMART AVD

I1_13

IS20

I0_1

111

I0_5

I0_9

I0_13

IPA

I1_4

I1_8

I1_12

1 00

I0_4

I0_8

I0_12

45/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

7 POWER SAVIN G MODES

7.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 23): SLOW, WAIT (SL OW WAIT), ACTIVE HALT and HALT.

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2

OSC2

From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 23. Power Savin g Mo de Tr a nsi t io ns

High

RUN

SLOW

WAIT

7.2 SLOW MODE

This mode has two targets: – To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f

In this mode, the master clock frequency (f

CPU

OSC2

can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency

CPU

Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is al ready in SLOW mode.

Figure 24. SLOW Mode Clock Transitions

MCCSR

CPU

OSC2

CP1:0

SMS

/2 f

OSC2

00 01

OSC2

/4 f

OSC2

)

SLOW WAIT

ACTIVE HALT

HALT

Low

POWER CONSUMPTION

46/294

NEW SLOW

FREQUENCY

REQUEST

NORMALRUN MODE

REQUEST

POWER SAVING MODES (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

7.3 WAIT MODE

WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This pow e r s a v ing mode is s e lected b y ca llin g the ‘WFI’ instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC regist er are fo rced t o ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to th e starting address of the interrupt or Reset service routine. The MCU will r ema in in W AIT mod e unt il a R ese t or an Interrupt occurs, causing it to wake up.

Refer to Figure 25.

Figure 25. WAIT Mode Flow-chart

OSCILLATOR

WFI INSTRUCTION

INTERRUPT

PERIPHERALS CPU

I[1:0] BITS

RESET

OSCILLATOR PERIPHERALS CPU

I[1:0] BITS

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR PERIPHERALS CPU

I[1:0] BITS

ON ON

OFF

ON ON ON

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

47/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

POWER SAVING MODES (Cont’d)

7.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MC U. They are both entered by executing the ‘HA LT’ instruc tion. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

0 HALT mode 1 ACTIVE-HALT mode

7.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a rea l time clock available. It is entered by execut ing the ‘HALT’ instruction when the OIE bit of the M ain Clock Controller Status register (MCCSR) is set (see section

5.4 on page 32 for more details on the MCCSR

tion of either an MCC/RTC interrupt, a specific interrupt (see Table 8, “Interrupt Mapping,” on page 40) or a RESET. When exiting ACTIVEHALT mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the inte rrupt or by fetching the reset vector which woke it up (see Figure 27).

When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except t hose which get their clock supply from anoth er clock generator (suc h as externa l or a ux iliary oscilla t o r) .

The safeguard against staying l ocked in ACT IVEHALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

Figure 26. ACTIVE-HALT Timing Overview

ACTIVE

HALTRUN RUN

HALT

INSTRUCTION

[MCCSR.OIE=1]

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

FETCH

VECTOR

Figure 27. ACT IV E - H ALT Mode Flow-char t

HALT INSTRUCTION

(MCCSR.OIE=1)

INTERRUPT

OSCILLATOR PERIPHERALS CPU

I[1:0] BITS

RESET

OSCILLATOR PERIPHERALS CPU

I[1:0] BITS

256 OR 4096 CPU CLOCK

OSCILLATOR PERIPHERALS CPU

I[1:0] BITS

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CYCLE DELAY

ON OFF OFF

ON OFF

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripheral clocked with an external clock source can still be active.

3. Only the MCC/RTC i nterrupt and s om e specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 8, “Interrupt Mappi ng,” on page 40 for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.

48/294

POWER SAVING MODES (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

7.4.2 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see section 5.4 on page 32 for more details on the MCCSR register).

The MCU can exit HALT m ode on reception of either a specific interrupt (see Table 8, “Interrupt Mapping,” on page 40) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing t he i nterrupt o r by fetching the reset vector which woke it up (see Fig-

ure 29).

When entering HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with HALT mode is configured by t he “WDGHALT” option bit of the option byte. The HALT instruction when executed while the W atchdo g system is enabled, can generate a Watchdog RESET (see sec-

tion 13.1 on page 284 for more details).

Figure 28. HALT Timing Ove r v iew

HALTRUN RUN

HALT

INSTRUCTION

[MCCSR.OIE=0]

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

FETCH

VECTOR

ST7MC1/ST7MC2

Figure 29. HALT Mode Flow-chart

HALT INSTRUCTION

(MCCSR.OIE=0)

ENABLE

WDGHALT

WATCHDOG

RESET

INTERRUPT

OSCILLATOR PERIPHERALS CPU

I[1:0] BITS

OSCILLATOR PERIPHERALS CPU

I[1:0] BITS

256 OR 4096 CPU CLOCK

OSCILLATOR PERIPHERALS CPU

I[1:0] BITS

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from HALT mode (such as ext ernal inte rrupt). Refer to Table 8, “Interrupt Mapping,” on page 40 for more details.

WATCHDOG

RESET

CYCLE

DISABLE

DELAY

OFF OFF OFF

ON OFF

49/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

8 I/O PORTS

8.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs

and for specific pins:

– external interrupt generation – alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

8.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:

– Data Register (DR) – Data Direction Register (DDR)

and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implem entation section). The generic I/O block diagram is shown in Figure 30

8.2.1 Input Modes

The input configuration is sele cted by c learing th e corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1. Writing the DR register modifies the latc h valu e but does not affect the pin status.

2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.

3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register

External interrupt function

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.

Each pin can independen tly generate an i nterrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register.

Each external interrupt vector is linked to a d edicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as i nterrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed.

The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified.

8.2.2 Output Modes

The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

DR register value and output pin status:

DR Push-pull Open-drain

0V 1V

Vss

Floating

8.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is automat ically selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is automatica lly configured in ou tput mode (push-pull or open drain according to the peripheral).

When the signal is going t o an on-c hip pe ripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin h as to be configured in input floating mode.

50/294

I/O PORTS (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Figure 30. I/O Por t Ge neral B lo ck Diag ra m

ST7MC1/ST7MC2

DATA BUS

DDR SEL

DDR

OR SEL

DR SEL

ALTERNATE OUTPUT

ALTERNATE ENABLE

If implemented

PULL-UP CONDITION

N-BUFFER

CMOS SCHMITT TRIGGER

P-BUFFER (see table below)

PULL-UP (see table below)

PAD

DIODES (see table below)

ANALOG

INPUT

EXTERNAL INTERRUPT

SOURCE (eix)

Table 10. I/O Port Mode Options

Configuration Mode Pull-Up P-Buffer

Input

Output

Floating with/without Interrupt Off Pull-up with/withou t Interrupt On Push-pull Open Drain (logic level) Off True Open Drain NI NI NI (see note)

Legend: NI - not impleme nted

Off - implemented not activated On - implemented and activated

ALTERNATE

INPUT

Diodes

to V

Off

Note: The diode to V true open drain pads. A local protection between the pad and V vice against positive stress.

is implemented to protect the de-

is not implemented in the

to V

51/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

I/O PORTS (Cont’d) Table 11. I/O Port Configurations

Hardware Configuration

NOT IMPLEMENTED IN TRUEOPEN D RAIN I/O PORTS

INPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN

I/O PORTS

OPEN-DRAIN OUTPUT

PAD

PULL-UP CONDITIO N

INTERRUPT CONDITION

DR REGISTER ACCESS

EXTERNAL INTERRUPT SOURCE (ei

ENABLE OUTPUT

)

DR REGISTER ACCESS

ALTERNATEALTERNATE

ALTERNATE INPUT

ANALOG INPUT

R/W

DAT A BUS

NOT IMPLEMENTED IN TRUE OPEN DRAIN

I/O PORTS

PAD

PUSH-PULL OUTPUT

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function outp ut status.

2. When the I/O port is in output configuration and t he associated alternate function is enabled as an i nput, the alternate function reads the pin status given by the DR register content.

52/294

DR REGISTER ACCESS

ENABLE OUTPUT

R/W

ALTERNATEALTERNATE

DAT A BUS

I/O PORTS (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The analo g multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it i s recommended not to have clocking pins located clos e t o a sele cted analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum r a tings .

8.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port depends on the settings in the DDR and OR regi sters and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 31 Other transitions are potentially risky and shou ld be avoide d, since they are likely to present unwanted side-effects such as spurious interrupt generation.

ST7MC1/ST7MC2

Figure 31. Interrupt I/O Port State Transitions

INPUT

floating/pull-up

interrupt

8.4 LOW POWER MODES

Mode Description

WAIT

HALT

8.5 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).

Interrupt Event

External interrupt on selected external event

INPUT floating

(reset state)

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

Event

Flag

OUTPUT

open-drain

Enable

Control

Bit

DDRx

ORx

OUTPUT push-pull

= DDR, OR

Exit from Wait

Yes Yes

Exit

from

Halt

53/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

I/O PO R T S (Cont’d)

8.5.1 I/O Port Implementation

The I/O port register configurations are summarised as follows.

Stand ard Po rt s PA4, PA2:0, PB5:0, PC7:4,

PD7:6, PE5:0, PF5:0, PG7:0, PH7:0

MODE DDR OR

floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1

Interrupt P orts PA6, PA3, PB 6, PC 3, P C1, PD5, PD4, P D2 (with

pull-up)

MODE DDR OR

floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1

PA7, PA5, PB 7 , PC 2 , PC0, PD6, PD 3, PD 1 (wi thout pull-up)

MODE DDR OR

floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1

Table 12. Port Configuration

Port Pin name

PA7, PA5 floating fl oating interrupt open drain push-pull

Port A

Port B

Port C

Port D

Port E PE5:0 floating pull-up open drain push-pull Port F PF5:0 floating pull-up open drain push-pull Port G PG7:0 floating pull-up open drain push-pull Port H PH7:0 floating pull-up open drain push-pull

PA6, PA3 floating pull-up interrupt open drain push-pull PA2:0 floating pull-up open drain push-pull PB7 floating fl oating interrupt open drain push-pull PB6 floating pull-up interrupt open drain push-pull PB5:0 floating pull-up open drain push-pull PC7:4 floating pull-up open drain push-pull PC3, PC1 floating pull-up interrupt open drain push-pull PC2, PC0 floating floating interrupt open drain push-pu ll PD7, PD0 floating pull-up open drain push-pull PD6, PD3, PD1 floating floating interrupt open drain push-pull PD5, PD4, PD2 floating pull-up interrupt open drain push-pull

OR = 0 OR = 1 OR = 0 OR = 1

Input Output

54/294

I/O PORTS (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Table 13. I/O Port Register Map and Reset Values

ST7MC1/ST7MC2

Address

(Hex.)

Reset Value

of all I/O port registers

0000h PADR

0002h PAOR 0003h PBDR

0005h PBOR 0006h PCDR

0008h PCOR 0009h PDDR

000Bh PDOR

000Ch PEDR

000Eh PEOR 000Fh PFDR

0011h PFOR 0012h PGDR

0014h PGOR 0015h PHDR

0017h PHOR

Label

76543210

00000000

MSB LSB0001h PADDR

MSB LSB0004h PBDDR

MSB LSB0007h PCDDR

MSB LSB000Ah PDDDR

MSB LSB000Dh PEDDR

MSB LSB0010h PFDDR

MSB LSB0013h PGDDR

MSB LSB0016h PHDDR

55/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9 ON-CHIP PERIPHERALS

9.1 WINDOW WATCHDOG (WWDG)

9.1.1 Introd uct i on

The Window Watchdog is used t o detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal seque nce. The Watchdo g circuit generates an MCU reset o n expiry of a programmed time period, unless the program refreshes the contents of the downcounter before t he T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downco unter has reached the window register value. This implies that the counter must be refreshed in a limited window.

9.1.2 Main Features

– Programm able free-running down co unter – Conditional reset

– Reset (if watchdog activated) when the down-

counter value becomes less than 40h

– Reset (if watchdog activated) if the down-

Figure 32. Watchdog Block Diagram

RESET

counter is reloaded outside the window (see

Figure 35)

– Hardware/S oftware Watchdog ac tivation (se-

lectable by option byte)

– Optional reset on HALT instruction (configurable

by option byte)

9.1.3 Functional Description

The counter value stored in the WDGC R register (bits T[6:0]), is decremented every 16384 f

OSC2

cycles (approx.), and the length of the timeout period can be programmed by the u ser in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit downcounter (T[6:0] bits) rolls over from 40h to 3Fh (T6 b ecome s cl eared), it initiates a reset cycle pulling low the reset pin for typically 30µs. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated.

WATCHDOG WINDOW REGISTER (WDGWR)

56/294

OSC2

Write WDGCR

MCC/RTC

RTC COUNTER

MSB

comparator

=1 when

T6:0 > W6:0

DIV 64

12-BIT MCC

LSB

CMP

WDGA

WATCHDOG CONTROL REGISTER (WDGCR)

TB[1:0] bits (MCCSR Register)

6-BIT DOWNCOUNTER (CNT)

WDG PRESCALE R

DIV 4

WINDOW WATCHDOG (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register v alue. The value to b e stored in the WDGCR register must be between FFh and C0h (see Figure 33):

– Enabling the watchdog:

When Software Watchdog is selected (by option byte), the watchdog is disabled after a reset. It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be disabled again except by a reset.

When Hardware Watchdog is selected (by option byte), the watchdog is always active and the WDGA bit is not used.

– Controlling the downcounter :

This downcounter is free-running: it counts down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see Figure 33. Ap-

proximate Timeout Duration). The timing varies

ST7MC1/ST7MC2

between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see F igure 34).

The window register (WDGWR) contains the high limit of the window: to prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 3Fh. Figure 35 describes the window watchdog process.

Note: The T6 bit can be used to generate a sof tware reset (the WDGA bit is set and t he T6 bit is cleared).

– Watc hdog Reset on Halt option

If the watchdog is activated and the watchdog reset on halt option is selected, then the HALT instruction will generate a Reset.

9.1.4 Using Halt Mode with the WDG

If Halt mode with Watchdog is en abled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

57/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

WINDOW WATCHDOG (Cont’d)

9.1.5 How to Program the Watchdog Timeout

Figure 3 3 shows the linear relationship between

the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If

Figure 33. Approximate Timeout Duration

more precision is needed, use the formulae in Fig-

ure 34.

Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.

CNT Value (hex.)

1.5 65

503418 82 98 114

Watchdog timeout (ms) @ 8 MHz. f

128

OSC2

58/294

WATCHD OG TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

Figure 34. Exact Timeout Duration (t

min

and t

max

)

WHERE:

= (LSB + 128) x 64 x t

min0

max0

OSC2

= 16384 x t

= 125ns if f

OSC2

=8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values f rom th e table b elow d epending on the timebase s elected by t he T B[1:0] bits

in the MCCSR register

TB1 Bit

(MCCSR Reg.)

0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54

To calculate the m i ni m um W at chdog Tim eout (t

IF THEN

CNT

MSB

------------4

To calculate the maximum Watchdog Timeout (t

TB0 Bit

(MCCSR Reg.)

ELSE

mintmin0

Selected MCCSR

Timebase

mintmin0

16384 CNT t

16384 CNT



× 192 LS B+()64



MSB LSB

min

××+

osc2

4CNT

---------------- -

–

MSB

max

4CNT

××

---------------- MSB

osc2

IF THEN

CNT

MSB

-------------

≤

ELSE

maxtmax0

16384 CNT t

16384 CNT



× 192 LS B+()64



××+

–

osc2

4CNT

---------------- MSB

4CNT

××

---------------- MSB

Note: In the above formulae, division results must be rounded down to the next integer value. Example:

With 2ms timeout selected in MCCSR register

Value of T[5:0] Bits in

WDGCR Register (Hex.)

00 1.496 2.048

3F 128 128.552

Min. Watchdog

Timeout (ms)

min

Max. Watchdog

Timeout (ms)

max

osc2

59/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

WINDOW WATCHDOG (Cont’d) Figure 35. Window Watchdog Timing Diagram

T[5:0] CNT downcounter

WDGWR

3Fh

Refresh WindowRefresh not allowed

T6 bit

Reset

9.1.6 Low Power Modes

time

(step = 16384/f

OSC2

)

Mode Description

SLOW No effect on Watchdog : the downcounter continues to decrement at normal speed .

WAIT No effect on Watchdog : the downcounter continues to decrement.

OIE bit in

MCCSR register

HALT

0 1 A reset is generated instead of entering halt mode.

ACTIVE HALT

9.1.7 Hardware Watchdog Op t io n

If Hardware Watchdog is selected by option b yte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Opt ion Byt e description.

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset.

If an interrupt is received (refer to interrupt table mapping to see interrupts which can occur in halt mode), the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 9.1.8 below.

No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.

9.1.8 Using Halt Mode with the WDG (WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled.

– Before execut ing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

60/294

WINDOW WATCHDOG (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.1.9 Interrupts

None.

ST7MC1/ST7MC2

Note: This bit is not used if the hardware watch-

dog option is enabled by option byte.

9.1.10 Register Description CONTROL REGISTER (WDGCR)

Read/Write Reset Value: 0111 1111 (7Fh)

WDGA T6 T5 T4 T3 T2 T1 T0

Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB). These bits contain the value of the watchdog counter. It is decremented every 16384 f cles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

WINDOW REGISTER (WDGWR)

Read/Write Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

- W6W5W4W3W2W1W0

watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Bit 7 = Reserved Bits 6:0 = W[6:0] 7-bit window value

These bits contain the window value to be compared to the downcounter.

OSC2

cy-

61/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Table 14. Watchdog Timer Register Map and Rese t Values

Address

(Hex.)

002Ah

002Bh

Label

WDGCR

Reset Value

WDGWR

Reset Value

76543210

WDGA

0 0

62/294

9.2 PWM AUTO-RELOAD TIMER (ART)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.2.1 Introd uct i on

The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source.

These resources allow five possible operating modes:

– Generation of up to 4 independent PWM signals – Output compare and Time bas e interrupt

Figure 36. PWM Auto-Reload Timer Block Diagram

ST7MC1/ST7MC2

– Up to two input capture functions – External event dete ctor – Up to two external interrupt sources

The three first modes can be used together with a single counter frequency.

The timer can be used to wake up the MCU from WAIT and HALT modes.

PWMx

ARTICx

ARTCLK

PWMCR

PORT

ALTERNATE

FUNCTION

EXT

CPU

OEx

INPUT CAPTURE

MUX

ARR

CONTROL

ICIEx

OPx

POLARITY CONTROL

ICFxICSx

COUNTER

LOAD

ICCSR

OCRx

COMPARE

8-BIT COUNTER

(CAR REGISTER)

ICRx

ICx INTERRUPT

DCRx

LOAD

INPUT

PROGRAMMABLE

PRESCALER

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

ARTCSR

OVFINTERRUPT

63/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

PWM AUTO-RELOAD TIMER (Cont’d)

9.2.2 Functional Description Counter

The free running 8-bit cou nter is f ed by the output of the prescaler, and is incremented on every rising edge of the clock signal.

It is possible to read or write the content s of the counter on the fly by reading or writing the Counter Access register (ARTCAR).

When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected).

Counter clock and prescaler

The counter clock frequency is given by:

COUNTER

= f

INPUT

The timer counter’s input clock (f

/ 2

CC[2:0]

INPUT

) feeds the 7-bit programmable prescaler, which sel ects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2

This f

INPUT

(where n = 0, 1,..7).

frequency source is selected through the EXCL bit of the ARTCSR register and can be either the f

or an external input frequency f

CPU

EXT

The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When T CE is set, the coun ter runs at the rate of the selected clock sou rce .

Counter and Prescaler Initialization

After RESET, the counter and the prescaler are cleared and f

INPUT

= f

CPU

. The counter can be initialized by: – Writing to the ARTARR register and then setting

the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the ARTCSR reg-

ister. – Writing to the ARTCAR counter access register, In both cases the 7-bit pres caler is also cleared,

whereupon counting will start from a known value. Direct access to the prescaler is not possible.

Output compare contro l

The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made between the counter value and an outpu t compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the counter.

This double buffering method avoids glitch generation when changing the duty cycle on the fly.

Figure 37. Output compare control

COUNTER

OCRx

PWMDCRx

PWMx

64/294

FDh FEh FFh FDh FEh FFh FDh FEh

FDh

ARTARR=FDh

FDh

FFh

FEh

PWM AUTO-RELOAD TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

Independent PWM signal generation

This mode allows up to four Pulse Width Mo dulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode.

Each PWMx ou tput signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function.

The PWM signals all have the same frequency which is controlled by the counter period and the ARTARR register value.

PWM

= f

COUNTER

/ (256 - ARTARR)

When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx (output polarity) bit in the P WMCR register.

Figure 38. PW M Au t o-re l oad Timer Fun ct io n

255

DUTY CYCLE

(PWMDCRx)

When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored.

It should be noted that the reload values will also affect the value and the resolution of the duty cycl e of the PWM output sign al. T o obtain a signal on a PWMx pin, the contents of the OCRx register must be greater than the con tents of the AR TARR register.

The maximum avai lable resolution for the PW Mx duty cycle is:

Resolution = 1 / (256 - ARTARR)

Note: To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.

AUTO-RELOAD

COUNTER

(ARTARR)

000

WITH OEx=1 AND OPx=0

WITH OEx=1 AND OPx=1

PWMx OUTPUT

Figure 39. PWM Signal from 0% to 100% Duty Cycle

COUNTER

ARTARR=FDh

COUNTER

OCRx=FCh

OCRx=FDh

OCRx=FEh

AND OPx=0

WITH OEx=1

PWMx OUTPUT

OCRx=FFh

FDh FEh FFh FDh FEh FFh FDh FEh

65/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

PWM AUTO-RELOAD TIMER (Cont’d) Output compare and Time base interru pt

On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be

External clock and event detector mode

Using the f auto-reload timer can be used as an external clock event detector. In this mode, the ARTARR register is used to select the n be counted before setting the OVF flag.

used as a time base in the application.

Caution: The external clock function is not available in HALT mode. If HALT mode is used in the application, prior to executing the HALT instruction, the counter must b e di sa bled by c lea ring the TCE bit in the ARTCSR register to avoid spurious counter increments.

Figure 40. External Event Detector Example (3 counts)

EXT=fCOUNTER

ARTARR=FDh

COUNTER

OVF

FDh FEh FFh FDh

external prescaler input clock, the

EXT

EVENT

FEh FFh FDh

= 256 - ARTARR

EVENT

number of even ts to

INTERRUPT

IF OIE=1

ARTCSR READ

INTERRUPT

IF OIE=1

66/294

PWM AUTO-RELOAD TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Input capture function

This mode allows the measurement of external signal pulse widths through ARTICRx registers.

Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status register (ARTICCSR).

These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register.

The active transition (falling or rising edge) is software programmable through the CSx bits of the ARTICCSR register.

The read only input capture registers (ARTICRx) are used to latch the auto-reload counter value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register). After fetching the interrupt vector, the CFx flags can be read t o identify the interrupt source.

Note: After a capture detection, data transfer in the ARTICRx register is inhibited until it is read (clearing the CFx bit). The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled (CIEx bit set). This means, the ARTICRx register has to be read at each capture event to clear the CFx flag.

ST7MC1/ST7MC2

External interru pt capability

This mode allows the Input capture capabilities to be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx signal.

The edge sensitivity of the external interrupts is programmable (CSx bit of ARTICCSR register) and they are independently enable d throu gh CIEx bits of the ARTICCSR register. After fetching t he interrupt vector, the CFx flags can be read to identify the interrupt source.

During HALT mode, the external interrupts can be used to wake up the micro (if the CIEx bit is set).

The timing resolution is given by auto-reload counter cycle time (1/f

COUNTER

Note: During HALT mode, if both input capture and external clock are enabled, the ARTICRx register value is not guaranteed if the input capture pin and the external clock change simultaneously.

Figure 41. Input Capture Timing Diagram

COUNTER

ARTICx PIN

CFx FLAG

ICRx REGISTER

01h

02h 03h 05h 06h 07h

xxh

04h

INTERRUPT

04h

67/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

PWM AUTO-RELOAD TIMER (Cont’d)

9.2.3 Register Description CONTROL / STATUS REGISTER (ARTCSR)

Read/Write Reset Value: 0000 0000 (00h)

0: New transition not yet reached 1: Transition reached

COUNTER ACCESS REGISTER (ARTCAR)

Read/Write Reset Value: 0000 0000 (00h)

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

Bit 7 = EXCL

External Clock

CA7CA6CA5CA4CA3CA2CA1CA0

This bit is set and cleared by software. I t selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock.

Bit 6:4 = CC[2:0] Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from f

COUNTER

INPUT

/ 2 / 4

/ 8 / 16 / 32 / 64

/ 128

With f

=8 MHz CC2 CC1 CC0

INPUT

8 MHz 4 MHz 2 MHz

1 MHz 500 KHz 250 KHz 125 KHz

62.5 KHz

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

INPUT

0 1 0 1 0 1 0 1

Bit 7:0 = CA[7:0] Counter Access Data These bits can be set and cleared either by hard-

ware or by software. The ARTCAR register is used to read or write the auto-reload counter “on the fly” (while it is counting).

AUTO-RELOAD REGISTER (ARTARR)

Read/Write Reset Value: 0000 0000 (00h)

AR7AR6AR5AR4AR3AR2AR1AR0

Bit 3 = TCE Timer Counter Enable This bit is set and cleared by s oftware. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen). 1: Counter running.

Bit 2 = F CRL

Force Counter Re-Load

This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARTARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count.

Bit 1 = OIE

Overflow Interrupt Enable

This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable. 1: Overflow Interrupt enable.

Bit 0 = OVF

Overflow Flag

This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value

Bit 7:0 = AR[7:0]

Counter Auto-Reload Data

These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. At the same tim e, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register.

This register has two PWM management functions:

– Adjusting the PWM frequency – Setting the PWM duty cycle resolution

PWM Frequency vs. Resolution:

ARTARR

value

0 8-bit ~0.244-KHz 31.25-KHz

[ 0..127 ] > 7-bit ~0.244-KHz 62.5-KHz [ 128..191 ] > 6-bit ~0.488-KHz 125-KHz [ 192..223 ] > 5-bit ~0.977-KHz 250-KHz [ 224..239 ] > 4-bit ~1.953-KHz 500-KHz

Resolution

PWM

Min Max

68/294

PWM AUTO-RELOAD TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

PWM CONTROL REGISTER (PWMCR)

Read/Write Reset Value: 0000 0000 (00h)

OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0

Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output ch annels independently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled.

Bit 3:0 = OP[3:0] PWM Output Pol a r ity These bits are set and cleared by software. They independently select the po larity of the four P WM

DUTY CYCLE REGISTERS (PWMDCRx)

Read/Write Reset Value: 0000 0000 (00h)

DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

Bit 7:0 = DC[7:0] Duty Cycle Data These bits are set and cleared by software. A PWMDCRx register is associated with the OCRx

register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARTARR register). These PWMDCR registers allow the duty cycle to be set independently for each PWM channel.

output signals.

PWMx output level

Counter <= OCRx Counter > OCRx

100 011

OPx

Note: When an OPx bit is modified, the PWMx out-

put signal polarity is immediately reversed.

69/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

PWM AUTO-RELOAD TIMER (Cont’d) INPUT CAPTURE

CONTROL / STATUS REGISTER (ARTICCSR)

Read/Write

INPUT CAPTURE REGISTERS (ARTICRx)

Read only Reset Value: 0000 0000 (00h)

Reset Value: 0000 0000 (00h)

IC7IC6IC5IC4IC3IC2IC1IC0

0 0 CS2 CS1 CIE2 CIE1 CF2 CF1

Bit 7:0 = IC[7:0] Input Capture Data

Bit 7:6 = Reserved, always read as 0.

These read only bits are set and cleared by hard-

ware. An ARTICRx register contains the 8-bit Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They

auto-reload counter v alue t rans ferre d b y the input

capture channel x event. determine the trigger event polarity on the corresponding input capture channel. 0: Falling edge triggers capture on channel x. 1: Rising edge triggers capture on channel x.

Bit 3:2 = CIE[2:1] Capture Interrupt Enable These bits are set and cleared by software. They enable or disable the Input capture channel interrupts independently. 0: Input capture channel x interrupt disabled. 1: Input capture channel x interrupt enabled.

Bit 1:0 = CF[2:1] Capture Flag These bits are set by hardware and cleared by software reading the corresponding ARTICRx register. Each CFx bit indicates that an input capture x has occurred. 0: No input capture on channel x. 1: An input capture has occured on channel x.

70/294

PWM AUTO-RELOAD TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Table 15. PWM Auto-Reload Timer Register Map and Reset Values

ST7MC1/ST7MC2

Address

(Hex.)

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

Label

PWMDCR3

Reset Value

PWMDCR2

Reset Value

PWMDCR1

Reset Value

PWMDCR0

Reset Value

PWMCR

Reset Value

ARTCSR

Reset Value

ARTCAR

Reset Value

ARTARR

Reset Value

ARTICCSR

Reset Value

ARTICR1

Reset Value

76543210

DC7

OE3

EXCL

CA7

AR7

IC7

DC6

OE2

CC2

CA6

AR6

IC6

DC5

OE1

CC1

CA5

AR5

CS2

IC5

DC4

OE0

CC0

CA4

AR4

CS1

IC4

DC3

OP3

TCE

CA3

AR3

CIE2

IC3

DC2

OP2

FCRL

CA2

AR2

CIE1

IC2

DC1

OP1

OIE

CA1

AR1

CF2

IC1

DC0

OP0

OVF

CA0

AR0

CF1

IC0

007Dh

ARTICR2

Reset Value

IC7

IC6

IC5

IC4

IC3

IC2

IC1

IC0

71/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.3 16-BIT TIMER

9.3.1 Introd uct i on

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two out- put waveforms (output compare and PWM).

Pulse lengths and waveform perio ds c an be m odulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.

Some devices of the ST7 family have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a Device reset as long as the timer clock frequencies are not modified.

This description covers one or two 16-bit timers. In the devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).

9.3.2 Main Features

■

Programmable prescaler: f

■

Overflow status flag and maskable interrupt

■

External clock input (must be at least 4 times slower than the CPU

clock speed) with the choice

divided by 2, 4 or 8.

CPU

of active edge

■

Output compare functions with

– 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■

Input capture functions with

– 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■

Pulse width modulation mode (PWM)

■

One pulse mode

■

Reduced Power Mode

■

5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)*

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

9.3.3 Functional Description

9.3.3.1 Counter

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nific a nt byte ( MS By te ) .

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Count er High Re gist er (ACH R) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register, (SR),

(see note at the end of paragraph titled 16-bit read

sequence).

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock con trol bits

of the CR2 register, as illustrated in Table 16 Clock

Control Bits. The value in the c ounter register re-

peats every 131.072, 262.144 or 524.288 CPU

clock cycles depending on the CC[1:0] bits.

The timer frequency can be f

CPU

/2, f

CPU

/4, f

CPU

or an external frequency.

The Block Diagram is shown in Figure 42. *Note: Some timer pins may not available (not

bonded) in some devices. Refer to the device pin out description.

72/294

16-BIT TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Figure 42. Tim er B l ock D i a gra m

CPU

ST7MC1/ST7MC2

INTERNAL BUS

16-BIT TIMER PERIPHERAL INTERFACE

EXTCLK

EXEDG

1/2 1/4 1/8

CC[1:0]

8 high

COUNTER

ALTERNATE

COUNTER

OVERFLOW

DETECT CIRCUIT

8 low

8-bit

buffer

high

OUTPUT COMPARE REGISTER

TIMER INTERNAL BUS

OUTPUT COMPARE

CIRCUIT

low

16 16

high

low

OUTPUT COMPARE REGISTER

88 8

high

INPUT

CAPTURE

EDGE DETECT

CIRCUIT1

EDGE DETECT

CIRCUIT2

8 8 8

low

high

low

INPUT

CAPTURE

ICAP1

ICAP2

ICF2ICF1

OCF2OCF1 TOF

(Control/Status Register)

(Control Register 1) CR1

(See note)

TIMER INTERRUPT

TIMD

LATCH1

CSR

OC2E

PWMOC1E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE

LATCH2

(Control Register 2) CR2

Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See Device Interrupt Vector Table)

OCMP1

OCMP2

EXEDG

IEDG2CC0CC1

73/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d) 16-bit read seque nce: (from either the Counter

Beginning of the sequence

Read

At t0

At t0 +∆t

Sequence completed

The user must read the MS Byte f irst, then the LS Byte value is buffered automatically.

This buffered value rem ains unchanged until th e 16-bit read sequence is completed, even if the user reads the MS Byte several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count v alue at the time of the read.

Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

– The TOF bit of the SR register is set. – A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bit of the CC register is cleared.

If one of these cond itions is fal se, the interrupt remains pending to be issued as soon as they are both true.

MS Byte

Other

instructions

Read

LS Byte

LS Byte is buffered

Returns the buffered

LS Byte value at t0

Clearing the overflow interrupt request is done in two steps:

1.Reading the SR register while the TOF bit is set.

2.An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the previous count (Device awakened by an i nte rrupt) or from the reset count (Device awakened by a Reset).

9.3.3.2 External Clock

The external clock (where av ailable) is select ed if CC0=1 and CC1=1 in CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronise d with the falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus t he external clock frequency must be less than a quarter of the CPU clock frequency.

74/294

16-BIT TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Figure 43. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

ST7MC1/ST7MC2

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFD FFFE FFFF 0000 0001 0002 0003

Figure 44. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGI STER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0001

Figure 45. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is running.

FFFC FFFD

0000

75/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d)

9.3.3.3 Input Capture

In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer.

The two input capture 16-bit registers (IC1R and IC2R) are used to latch the valu e of the free running counter after a transition detected by the ICAPi pin (see figure 5).

MS Byte LS Byte

ICiR ICiHR ICiLR

ICiR register is a read-only register. The active transition is software programmable

through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running

counter: (

Procedure:

To use the input capture function select the following in the CR2 register:

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

– Select the edge of the active transition o n the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as floating input). And select the following in the CR1 register: – Set the IC IE b it to generat e an in terrupt after a n

input capture coming from e ither the ICAP1 pin

or the ICAP2 pin – Select the edge of the active transition o n the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input).

CPU

CC[1:0]).

When an input capture occurs:

– IC Fi bit is set. – Th e ICiR register contains the value of the free

running counter on the active transition on the ICAPi pin (see Figure 47).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture in terrupt request (i.e. clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set .

2. An access (read or write) to the ICiLR register.

Notes:

1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read.

2. The ICiR register contains the free running counter value which corresponds to the most recent input capture.

3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions.

4. In One pulse Mode and PWM mode only the input capture 2 can be used.

5. The alternate inputs (ICAP1 & ICAP2) are always directly connec ted to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the I CAPi pin is configured as an input and the s econd one as an output, an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set. This can be avoided if the in put capture function i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt in order to measure event that go beyond the timer range (FFFFh).

76/294

16-BIT TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Figure 46. Input Capture Block Diagram

ST7MC1/ST7MC2

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

IC2R Register

16-BIT

FREE RUNNING

COUNTER

EDGE DETECT

CIRCUIT1

IC1R Register

Figure 47. Input Capture Timing Diagram

TIMER CLOCK

ICIE

(Control Register 1) CR1

IEDG1

(Status Register) SR

ICF2ICF1 000

(Control Register 2) CR2

IEDG2

CC0

CC1

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER

Note: The active edge is the rising edge.

FF01 FF02 FF03

Note: The time between an event on the ICAPi pin and the appearance of the corresponding flag is from 2 to 3 CPU clock cycles. This depends on the moment when the ICAP event hap pens relative t o the timer clock.

FF03

77/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d)

9.3.3.4 Output Compare

In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer.

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found bet ween the Out put Com pare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCIE bit is set

– Sets a flag in the status register – Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be com pared to the counter register each timer clock cycle.

MS Byte LS Byte

OCiROCiHR OCiLR

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC

Timing resolution is one count of the free running counter: (

Procedure:

To use the output compare function, select the following in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMPi pin i s dedicated to the output com pare i signal.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

And select the following in the CR1 register: – Select the OLVLi bit to applied to the OCMPi pins

after the match occurs. – Set the OCIE bit to generate an interrupt if it is

needed. When a match is found between OCRi register

and CR register: – OCFi bit is set.

R value to 8000h.

CC[1:0]

CPU/

– The OCMP i pin take s OLVL i bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in the CC register (CC).

The OC ing application can be c alcul ated us ing the fol lowing f ormula:

Where:

∆

CPU

PRESC

If the timer clock is an external clock, the formula is:

Where:

∆

EXT

Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is

2. An access (read or write) to the OCiLR register. The following procedure is recommended to pre-

vent the OCFi bit from be ing set betwee n the time it is read and the write to the OC

– Write to the OCiHR register (further compares

– Read the SR register (first step of the clearance

– Write to the OCiLR register (enables the output

R register value required for a specific tim-

∆t * f

∆

OCiR =

t = Output compare period (in seconds)

= CPU clock frequency (in hertz)

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 16

Clock Control Bits)

∆

OCiR =

t = Output compare period (in seconds)

= External timer clock frequency (in hertz)

set.

are inhibited).

of the OCFi bit, which may be already set).

compare function and clears the OCFi bit).

∆t * f

CPU

PRESC

EXT

R register:

78/294

16-BIT TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Notes:

1. After a processor write cycle to t he O C iHR reg-

ister, the output compare function is inhibited until the OCiLR register is also written.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not appear when a match is f ound but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f

/2, OCFi and

CPU

OCMPi are set while the counter value equals the OCiR register value (see Figure 49 on page

80). This behaviour is the same in OPM or

PWM mode. When the timer clock is f external clock mode, OC Fi and OCMPi are set

CPU

/4, f

CPU

/8 or in

while the counter value equals the OCiR register value plus 1 (see Figure 50 on page 80).

4. The output compare functions can be used both

for generating external events on the OCMPi pins even if the input capture mode is also used.

5. The value in the 16-bit OC

R register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout.

ST7MC1/ST7MC2

Forced Compare Output capabilit y

When the FOLVi bit is set by software, the OLV Li bit is copied to the OCMPi pin. The OLVi bit has to be toggled in ord er to t oggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

FOLVLi bits have no effect in both one pulse mode and PWM mode.

Figure 48. Output Compare Block Diagram

16 BIT FREE RUNNING

COUNTER

16-bit

OUTPUT COMPARE

CIRCUIT

16-bit

OC1R Register

16-bit

OC2R Register

OC1E CC0CC1

OC2E

(Control Register 2) CR2

(Control Register 1) CR1

FOLV2 FOLV1

(Status Register) SR

OLVL1OLVL2OCIE

000OCF2OCF1

Latch

OCMP1

OCMP2

79/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d) Figure 49. Output Compare Timing Diagram, f

INTERNAL CPU CLOC K

TIMER CLOCK

TIMER

CPU

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 50. Output Compare Timing Diagram, f

INTERNAL CPU CLOC K

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

2ED0 2ED1 2ED2

TIMER

CPU

2ED0 2ED1 2ED2

2ED3

2ED42ECF

80/294

16-BIT TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the op p o s ite column).

2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the a ctive trans ition o n the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input).

3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

– Set the OPM bit. – Select the timer clock CC[1:0] (see Table 16

Clock Control Bits).

ST7MC1/ST7MC2

Clearing the Input Capture in terrupt request (i.e. clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set .

2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific

timing application can be calculated usi ng the following formula:

OCiR Value =

CPU

PRESC

Where: t = P ulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 16

Clock Control Bits)

If the timer clock is an external clock the formula is:

OCiR =

t * f

EXT

-5

Where: t = Pulse period (in seconds) f

= External timer clock frequency (in hertz)

EXT

When the value of the counter is equal to the value of the contents of t he OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 51).

- 5

One pulse mode cycle

When

event occurs

on ICAP1

ICR1 = Counter

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 b it is set

When

Counter = OC1R

OCMP1 = OLVL1

When a valid event occu rs on the ICAP1 pin, the counter value is loaded in the ICR1 register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin and the ICF1 bit is set.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

Notes:

1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt.

2. When the Pulse Width Mo dulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perfo rm input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge o ccurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indica te a period of time has been elapsed but canno t generate an output waveform because the level OL VL 2 is dedicated to the one pulse mode.

81/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d) Figure 51. One Pu lse Mode Timing Example

IC1R

COUNTER

ICAP1

OCMP1

FFFC FFFD FFFE 2ED0 2ED1 2ED2

01F8

OLVL2

01F8

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 52. Pulse Width M odulation Mode Timin g E xa m p le

COUNTER

OCMP1

FFFC FFFD FFFE

34E2

OLVL2

2ED0 2ED1 2ED2

compare2 compare1 compare2

2ED3

FFFC FFFD

2ED3

OLVL2OLVL1

34E2 FFFC

OLVL2OLVL1

Note: OC1R=2ED0h, OC2R=34E2, OLV L1=0, OLVL2= 1

82/294

16-BIT TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency a nd puls e length determined by the value of the OC1R and OC2R registers.

Pulse Width Modulation m ode uses the c omplete Output Compare 1 func tion plus the OC2R re gister, and so this functionality can not be used when PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are l oaded in their respective shadow registers (double buffer) only at the end of the P W M p eriod (OC2) t o avoi d spikes on the PWM output pin (OCMP1). The shadow registers contain the reference values for comp arison in PWM “double buffering” mode.

Note: There is a locking mechanism for transferring the OCiR value to the buffer. After a write to the OCiHR register, transfer of the new compare value to the buffer is inhibited until OCi LR is also written.

Unlike in Output Compare mode, the compare function is always enabled in PWM mode.

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in t he opposite column.

3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with OC2R register.

4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 16

ST7MC1/ST7MC2

Clock Control Bits).

Pulse Width Modulation cycle

When

Counter = OC1R

When Counter = OC2R

If OLVL1=1 and OLVL2=0 th e length of the positive pulse is the difference between the OC2R and OC1R registers.

If OLVL1=OLV L2 a c ontinuous signal will be seen on the OCMP1 pin.

The OC

R register value required for a specific timing application can be c alcul ated us ing the fol lowing f ormula:

OCiR Value =

Where: t = S ignal or pulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 16 Clock

Control Bits)

If the timer clock is an external clock the formula is:

OCiR =

Where: t = Signal or pulse period (in seconds) f

= External timer clock frequency (in hertz)

EXT

The Output Compare 2 event ca uses the counter to be initialized to FFFCh (See Figure 52)

Notes:

1. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output Compare interrupt is inhibited.

2. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit i s cleared.

OCMP1 = OLVL1

OCMP1 = OLVL 2

Counter is reset

to FFFCh

ICF1 bit is set

CPU

PRESC

t * f

EXT

-5

- 5

83/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d)

3. In PWM m ode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capt ure (ICF2 can be s et and IC2R can be loaded) but the user must take care that the counter is reset eac h period and

9.3.4 Low Power Modes

Mode Description

WAIT

HALT

No effect on 16-bit Timer. Timer interrupts cause the Device to exit from WAIT mode.

16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the Device is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the Device is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the Device is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.

9.3.5 Interrupts

Interrupt Event

Input Capture 1 event/Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No

ICF1 can also generates interrupt if ICIE is set.

4. When the Pulse Width Mo dulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.

Event

Flag

Enable

Control

Bit

ICIE

OCIE

Exit

from

Wait

Yes No

Exit

from

Halt

Note: The 16-bit Timer interrupt events are connecte d to the same i nterru pt vector (see In terrupts chap-

ter). These events generate an interrupt if the corresponding E nable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

9.3.6 Summary of Time r modes

MODES

Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse Mode No Not Recommended PWM Mode No Not Recommended

See note 4 in Section 9.3.3.5 One Pulse Mode

See note 5 in Section 9.3.3.5 One Pulse Mode

See note 4 in Section 9.3.3.6 Pulse Width Modulation Mode

Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2

AVAILABLE RESO URC ES

No Partially No No

84/294

16-BIT TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.3.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compa res, the count er and the alternate counter.

ST7MC1/ST7MC2

Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC 2E bit is set and even if there is no successful compari so n.

CONTROL REGISTER 1 (CR1)

Read/Write Reset Value: 0000 0000 (00h)

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no successful comparison.

Bit 2 = OLVL2 Output Level 2.

Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

This bit is copied to the OCMP2 pin wh enever a successful compa rison occurs with t h e OC2R re gister and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode.

Bit 1 = IEDG1 Input Edge 1. This bit determines wh ich type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied t o t he O C MP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in th e CR2 register.

85/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2)

Read/Write Reset Value: 0000 0000 (00h)

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outpu ts a

programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.

Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the si gnal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate f unction disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the si gnal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate f unction disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM One Pulse Mode. 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the active transition is g iven by the IE DG1 bit. The length of the generated pulse depends on the contents of the OC1R register.

Bit 3, 2 = CC[1:0] Clock Control. The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Timer Clock CC1 CC 0

/ 4 0 0

CPU

/ 2 0 1

CPU

/ 8 1 0

CPU

External Clock (where

available)

Note: If the external clock pin is not available, programming the external clock configuration stops the counter.

Bit 1 = IEDG2 Input Edge 2. This bit determines wh ich type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = EXEDG External Clock Edge. This bit determines wh ich type of level transition on the external clock pin EXTCLK wi ll trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

86/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR)

Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.

ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0

Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin

or the counter has reached th e OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low by te of the IC1R (IC1LR) register.

Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC1R register. To clear this bit, first read the SR register, t hen read or write the low byte of the OC1R (OC1LR) register.

Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1:The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register.

Bit 3 = OCF2 O utput Compare Fl ag 2. 0: No match (reset value). 1: The content of the free running counter has

matched the c ontent of the OC2R register. T o clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.

Bit 2 = TIMD Timer disable. This bit is set and cleared by software. When set, it freezes the timer prescaler an d counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

87/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).

OUTPUT COMPARE 1 HIGH REGISTER (OC1HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).

MSB LSB

OUTPUT COMPARE 1 LOW REGISTER (OC1LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

MSB LSB

88/294

16-BIT TIMER (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

OUTPUT COMPARE 2 HIGH REGISTER (OC2HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit register that c ontains the high part of the value to be compared to the CHR register.

ST7MC1/ST7MC2

ALTERNATE COUNTER HIGH REGISTER (ACHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

MSB LSB

OUTPUT COMPARE 2 LOW REGISTER (OC2LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

MSB LSB

ALTERNATE COUNTER LOW REGISTER (ACLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does no t clear the TOF bit in t he CSR register.

MSB LSB

COUNTER HIGH REGISTER (CHR)

MSB LSB

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit register that c ontains the high part of the counter value.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only

Reset Value: Undefined This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

MSB LSB

Input Capture 2 event).

COUNTER LOW REGISTER (CLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.

MSB LSB

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).

MSB LSB

89/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

16-BIT TIMER (Cont’d) Table 17. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Timer A: 32 Timer B: 42

Timer A: 31 Timer B: 41

Timer A: 33 Timer B: 43

Timer A: 34 Timer B: 44

Timer A: 35 Timer B: 45

Timer A: 36 Timer B: 46

Timer A: 37 Timer B: 47

Timer A: 3E Timer B: 4E

Timer A: 3F Timer B: 4F

Timer A: 38 Timer B: 48

Timer A: 39 Timer B: 49

Timer A: 3A Timer B: 4A

Timer A: 3B Timer B: 4B

Timer A: 3C Timer B: 4C

Timer A: 3D Timer B: 4D

Label

CR1

Reset Value

CR2

Reset Value

CSR

Reset Value

ICHR1

Reset Value

ICLR1

Reset Value

OCHR1

Reset Value

OCLR1

Reset Value

OCHR2

Reset Value

OCLR2

Reset Value

CHR

Reset Value

CLR

Reset Value

ACHR

Reset Value

ACLR

Reset Value

ICHR2

Reset Value

ICLR2

Reset Value

76543210

ICIE

OC1E

ICF1

MSB

1111111

MSB

1111110

MSB

1111111

MSB

1111110

MSB

OCIE

OC2E

OCF1

------

TOIE0FOLV20FOLV10OLVL20IEDG10OLVL1

OPM

TOF

PWM

ICF2

CC1

OCF2

CC0

TIMD

IEDG20EXEDG

LSB

90/294

9.4 SERIAL PERIPHERAL INTERFACE (SPI)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

ST7MC1/ST7MC2

9.4.1 Introd uct i on

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves.

9.4.2 Main Features

■

Full duplex synchronous transfers (on 3 lines)

■

Simplex synchronous transfers (on 2 lines)

■

Master or slave operation

■

Six master mode frequencies (f

■

/2 max. slave mode frequency (see note)

CPU

■

SS Management by software or hardware

■

Programmable clock polarity and phase

■

End of transfer interrupt flag

■

Write co llision, Master Mode Fault and Overrun

CPU

/4 max.)

flags

Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence.

9.4.3 General Description

Figure 53 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR)

The SPI is connect ed to external d evices through 4 pins:

– MISO: Master In / Slave Out data – MOSI: Master Out / Slave In data – SCK: Serial Clock out by SPI m asters and in-

put by SPI slaves

– SS

: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS ard I/O ports on the master

inputs can be driven by stand-

Device

91/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

Figure 53. Serial Peripheral Interface Block Diagram

Data/Address Bus

MOSI

MISO

SCK

SOD

bit

SPIDR

Read Buffer

8-Bit Shift Register

Read

Write

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

Interrupt

request

SPIF WCOL MODF

OVR SSISSMSOD

SPI

STATE

CONTROL

MSTR

SPIE SPE

SPR2

CPOL

CPHA

SPICSR

SPICR

SPR1

SPR0

92/294

SERIAL PERIPHERAL INTERFACE (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.4.3.1 Functional Description

A basic example of interconnections between a single master and a single slave is illustrated in

Figure 54.

The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device re-

Figure 54. Single Master/ Single Slave Application

ST7MC1/ST7MC2

sponds by sending da ta to the master device via the MISO pin. This implies full duplex communication with both data out an d data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible).

Four possible data/clock timing relationship s may be chosen (see Figure 57) b ut master and slave must be programmed with the same timing mode.

MASTER

MSBit LSBit MSBit LSBit 8-BIT SHIFT REGISTE R

SPI

CLOCK

GENERATOR

MISO

MOSI

SCK

+5V

MISO

MOSI

SCK

8-BIT SHIFT REGISTE R

SLAVE

Not used if SS is mana ged by software

93/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.3.2 Slave Select Management

As an alternative to using the SS Slave Select signal, the appli cation c an choose to manage the Slave Select signal by softwa re. This is configured by the SSM bit in the SPI CSR register (see Figure 56)

In software management, the external SS free for other application uses and t he i nternal S S signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode:

– SS

internal must be held high continuously

pin to control the

pin is

In Slave Mode:

There are two cases depending on th e data/clock timing relationship (see Figure 55 ):

If CPHA=1 (data latched on 2nd clock edge):

– SS

internal must be held low during the entire transmission. This implies that in single slave applications the SS V

, or made free for standard I/O by manag-

ing the SS

function by software (SSM= 1 and

pin either can be tied to

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

– SS

internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS

is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Sec tion 9.4.5.3).

Figure 55. Generic SS

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Timing Dia gram

Byte 1 Byte 2

Figure 56. Hardware/Software Slave Select Management

SSM bit

external pin

SSI bit

SS internal

Byte 3

94/294

SERIAL PERIPHERAL INTERFACE (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The c lock f requency, polarity and phase are configured by software (refer to the description of the SPICSR register).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit ) may be not taken into account):

1. Write to the SPICR register: – Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity a nd clock phase by

configuring the CPOL and CPHA bits. Figure

57 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

2. Write to the SPICSR register: – Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS the complete byte transmit sequence.

3. Write to the SPICR register: – Set the MSTR and SPE bits

Note: MST R and SPE bits remain set onl y if SS

is high).

The transmit sequence begins when software writes a byte in the SPIDR register.

9.4.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware – An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set

2. A read to the SPIDR register.

pin high for

ST7MC1/ST7MC2

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR register is read.

9.4.3.5 Slave Mode Operation

In slave mode, the serial c lock is received on the SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPIC SR register to perform t he following actions:

– Select the clock po larity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 57).

Note: The slav e must have the sam e CPOL and CPHA settings as the master.

– Manage the SS

9.4.3.2 and Figure 55. If CPHA=1 SS

held low continuously. If CPHA=0 SS held low during byte transmission and pulled up between each by te t o l et the slave wri te in the shift register.

2. Write to the SPICR reg ister to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.

9.4.3.6 Slave Mode Transmit Sequen ce

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first.

The transmit sequence begins when the slave device receives the clo ck si g n al and the most significant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware – An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

The SPIF bit can be cleared during a second transmission; however, it mus t be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 9.4.5.2).

pin as described in Section

must be must be

95/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chosen by software, using the CPOL an d CPHA bits (Se e

Figure 57).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge

Figure 57. Dat a C loc k Ti m in g D i agram

SCK (CPOL = 1)

SCK (CPOL = 0)

Figure 57, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly c onnected between the master and the slave device.

Note: If CPOL is changed at the communication byte boundaries, the SPI must be di sabled by resetting the SPE bit.

CPHA =1

MISO

(from master)

MOSI

(from slav e)

(to slave)

CAPTURE STROBE

SCK (CPOL = 1)

SCK (CPOL = 0)

MISO

(from master)

MOSI

(from slav e)

(to slave)

CAPTURE STR OB E

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

CPHA =0

Bit 4 Bit3 Bit 2 Bit 1 LSBit

Note:

This figure should not be used as a replacement for parametric informa tion .

Refer to the E lectrical Characteristics chapter.

96/294

SERIAL PERIPHERAL INTERFACE (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.4.5 Error Flags

9.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master device has its SS

pin pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the Device and disables the S PI peripheral.

– The MSTR bit is reset, thus forcing the Device

into slave mode.

Clearing the MODF bit is done through a software sequence:

1. A read access to the SPICSR register while the MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application with multiple slaves, the SS

pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

In a slave device, the MODF bit can not be set, but in a multi master configuration the

Device

can be in

slave mode with the MODF bit set. The MODF bit indicates that there might have

been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset o r return to an application default state.

ST7MC1/ST7MC2

9.4.5.2 Overrun Condition (OVR )

An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte.

When an Overrun o ccurs: – The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the receiver buffer contains t he byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

9.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also Section 9.4.3.2 Slave Select Man-

agement.

Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the CPU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 58).

Figure 58. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

2nd Step

Read SPICSR

Read SPIDR

RESULT

SPIF =0 WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

Read SPICSR

Read SPIDR

RESULT

WCOL=0

Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit

97/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.5.4 Single Master and Multimaster Configurations

There are two types of SPI systems:

– Single Master System – Multimaster System

Single Master System

A typical single master system may be configured, using a

device

as the master and four

device

s as

slaves (see Figure 59). The master device selects the individual slave de-

vices by using four pins of a parallel port to control the four SS

The SS

pins of the slave devices.

pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.

Note: T o prevent a b us conflict on the MISO line the master allows only one active slave device during a transmission.

Figure 59. Single Master / Multiple Slave Configuration

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has n ot written to its S PIDR register.

Other transmission security methods can use ports for handshake lines or data by tes with command fields.

Multi-Master System

A multi-master system may also be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system.

The multi-master system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register.

SCK

Device

MOSI

SCK

Master Device

SS SS

SCK

Slave

MOSI MOSI MOSIMISO MISO MISOMISO

MISO

Ports

Slave

Device

SCK SCK

Slave

Device

Slave

98/294

SERIAL PERIPHERAL INTERFACE (Cont’d)

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

9.4.6 Low Power Modes

Mode Description

No effect on SPI.

WAIT

HALT

SPI interrupt events cause the Device to exit from WAIT mode.

SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operati o n r e s um e s wh en t h e D e vi c e is w ok e n up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device.

9.4.6.1 Using the SPI to wake-up the Device from Halt mode

In slave configuration, the SPI is able to wake-up

Device

the

from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from Halt mo de, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution: The SPI can wake-up the

Device

from

Halt mode only if the Slave Select signal (external

ST7MC1/ST7MC2

pin or the SSI bit in the SPICSR register) is low

Device

when the lection is configured as external (see Section

9.4.3.2), make sure the master drive s a low level

on the SS

9.4.7 Interrupts

Interrupt Event

SPI End of Transfer Event

Master Mode Fault Event

Overrun Error OVR Yes No

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the in terrupt mas k in the CC register is reset (RIM instruction).

enters Halt mode. So if Slave se-

pin when the slave enters Halt mode.

Event

Flag

SPIF

MODF Yes No

Enable

Control

Bit

SPIE

Exit

from

Wait

Yes Yes

Exit

from

Halt

99/294

ST7MC1/ST7MC2

http://www.xinpian.net

提供单片机解密、IC解密、芯片解密业务

010-62245566 13810019655

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.8 Register Description CONTROL REGISTER (SPICR)

Read/Write Reset Value: 0000 xxxx (0xh)

SPIE SPE SPR2 MSTR CPOL C PHA SPR1 SPR0

Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever an End

of Transfer event, Master Mode Fault or Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register)

Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by s oftware. It is also cleared by hardware when, in master mode, SS

=0 (see Section 9.4.5.1 Master Mode F ault (MO DF)). The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider Enable. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer t o Table 18 SPI Master

mode SCK Frequency.

0: Divider by 2 enabled 1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR Master Mode. This bit is set and cleared by s oftware. It is also cleared by hardware when, in master mode, SS

=0 (see Section 9.4.5.1 Master Mode Fault (MODF)). 0: Slave mode 1: Master mode. The function of the SCK pin

changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI must be di sabled by resetting the SPE bit.

Bit 2 = CPHA Clock Phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Note: The slave must have the same CPOL and CPHA settings as the master.

Bits 1:0 = SPR[1:0] Serial Clock Frequency. These bits are set and c leared by software. Used with the SPR2 bit, they select the baud ra te of the SPI serial clock SCK output by the SPI in master mode.

Note: These 2 bits have no effect in slave mode. Table 18. SPI Master mode SCK Frequency

Serial Clock SPR2 SPR1 SPR0

/4 1 0 0

CPU

/8 0 0 0

CPU

/16 0 0 1

CPU

/32 1 1 0

CPU

/64 0 1 0

CPU

/128 0 1 1

CPU

100/294

ST ST7MC1, ST7MC2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual