ST ST7LITEU05, ST7LITEU09 User Manual

8-bit MCU with single voltage Flash memory,

DIP8

SO8 150”

DFN8

Features

■ Memories

– 2K Bytes single voltage Flash program

memory with readout protection, in-circuit and in-application programming (ICP and IAP). 10K write/erase cycles guaranteed,

data retention: 20 years at 55 °C – 128 bytes RAM – 128 bytes data EEPROM. 300K write/erase

cycles guaranteed, data retention: 20 years

at 55 °C

■ Clock, reset and supply management

– 3-level low voltage supervisor (LVD) and

auxiliary voltage detector (AVD) for safe

power- on/off procedures – Clock sources: internal trimmable 8-MHz

RC oscillator, internal low power, low

frequency RC oscillator or external clock – Five Power Saving Modes: Halt, Auto-

Wakeup from Halt, Active-halt, Wait and

Slow

■ Interrupt management

– 11 interrupt vectors plus TRAP and RESET – 5 external interrupt lines (on 5 vectors)

■ I/O Ports

– 5 multifunctional bidirectional I/O lines – 1 additional output line – 6 alternate function lines

Table 1. Device summary

Features

ST7LITEU05 ST7LITEU09

Program memory - bytes 2K

RAM (stack) - bytes 128 (64)

EEPROM -bytes - 128

Peripherals LT timer w/ Wdg, AT timer w/ 1 PWM, 10-bit ADC

Operating supply 2.4 V to 3.3 V @f

CPU frequency up to 8 MHz RC

Operating temperature -40 °C to +125 °C

Packages SO8 150”, DIP8, DFN8, DIP16

1. For development or tool prototyping purposes only. Not orderable in production quantities.

– 5 high sink outputs

■ 2 timers

– One 8-bit lite timer (LT) with prescaler

including: watchdog, 1 realtime base and 1 input capture

– One 12-bit auto-reload timer (AT) with

output compare function and PWM

■ A/D converter

– 10-bit resolution for 0 to V – 5 input channels

■ Instruction set

– 8-bit data manipulation – 63 basic instructions with illegal opcode

detection – 17 main addressing modes – 8 x 8 unsigned multiply instruction

■ Development tools

– Full hardware/software development

package – Debug module

ST7ULTRALITE

= 4 MHz, 3.3 V to 5.5 V @f

CPU

ST7LITEU05 ST7LITEU09

ADC, timers

= 8 MHz

CPU

(1)

October 2008 Rev 2 1/139

www.st.com

Contents ST7LITEU05 ST7LITEU09

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3.1 In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3.2 In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5.2 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7.1 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.1 Read operation (E2LAT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.2 Write operation (E2LAT=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.4.1 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.4.2 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.4.3 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.6 Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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5.7.1 EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . 26

6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.5 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.2 Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.3.1 Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 35

7.3.2 RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.3.3 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 36

7.3.4 AVD threshold selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . . 36

7.3.5 Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 37

7.4 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.4.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.4.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.4.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 39

7.4.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.5.1 Multiplexed IO reset control register 1 (MUXCR1) . . . . . . . . . . . . . . . . . 41

7.5.2 Multiplexed IO reset control register 0 (MUXCR0) . . . . . . . . . . . . . . . . . 41

8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Priority management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Interrupts and low power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.1 Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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8.3 Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.3.1 External interrupt control register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . . 45

8.3.2 External interrupt control register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . . 45

8.4 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.4.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.4.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.4.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.4.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.4 Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.4.1 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.5 Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.5.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.2.4 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.3 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.6 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

11.1 Lite timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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11.1.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

11.1.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.1.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

11.2 12-bit autoreload timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.3 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.1.1 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.1.4 Indexed mode (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.1.5 Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.1.6 Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

13.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

13.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . 98

13.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . 98

13.3.4 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.4.2 Internal RC oscillator supply characteristics . . . . . . . . . . . . . . . . . . . . 102

13.4.3 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

13.7.1 Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . 107

13.7.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

13.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108

13.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

13.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

13.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

13.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

13.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

13.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

14 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

15 Device configuration and ordering information . . . . . . . . . . . . . . . . . 127

15.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

15.1.1 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

15.1.2 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

15.2 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

15.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

15.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

15.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

15.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

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15.3.4 Order codes for development and programming tools . . . . . . . . . . . . . 132

15.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

7/139

List of tables ST7LITEU05 ST7LITEU09

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Data EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 5. Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 6. Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 7. Clock register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 8. CPU clock cycle delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 9. Multiplexed IO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 10. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 11. Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 12. Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 13. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 14. AVD threshold selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 15. System integrity register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 16. Enabling/disabling Active-halt and Halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 17. Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 18. AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 19. DR value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 20. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 21. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 22. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 23. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 24. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 25. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 26. Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 27. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 28. Lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 29. Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 30. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 31. Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 32. Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 33. Effect of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 34. Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 35. Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 36. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 37. Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 38. ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 39. Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 40. Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 89

Table 41. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 90

Table 42. Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 43. ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 44. Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 45. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 46. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 47. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 48. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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Table 49. Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 50. Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 51. Voltage drop between AVD flag set and LVD reset generation . . . . . . . . . . . . . . . . . . . . . 99

Table 52. Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 53. Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 54. Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 56. On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 57. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 58. Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 59. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 60. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 61. EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 62. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 63. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 64. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 65. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 66. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 67. Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 68. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 69. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 70. ADC accuracy with VDD = 3.3 V to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 71. ADC accuracy with VDD = 2.7 V to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 72. ADC accuracy with VDD = 2.4 V to 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 73. 8-lead very thin fine pitch dual flat no-lead package, mechanical data . . . . . . . . . . . . . . 122

Table 74. 8-pin plastic small outline package - 150-mil width, mechanical data. . . . . . . . . . . . . . . . 123

Table 75. 8-pin plastic dual in-line outline package, 300-mil width, mechanical data. . . . . . . . . . . . 124

Table 76. 16-pin plastic dual in-line package, 300-mil width, mechanical data . . . . . . . . . . . . . . . . 125

Table 77. Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 78. Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 79. LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 80. Sector 0 size selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 81. Development tool order codes for the ST7LITEU0x family. . . . . . . . . . . . . . . . . . . . . . . . 133

Table 82. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 83. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

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List of figures ST7LITEU05 ST7LITEU09

List of figures

Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. 8-pin SO and DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. 8-pin DFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4. 16-pin package pinout 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. EEPROM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8. Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9. Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 10. Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 11. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 13. Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 14. Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 15. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 16. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 17. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 18. Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 20. Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 21. Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 22. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 23. Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 24. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 25. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 26. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 27. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 28. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 29. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 30. AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 31. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 32. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 33. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 34. Lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 35. Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 36. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 37. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 38. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 39. PWM signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 40. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 41. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 42. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 43. fCPU maximum operating frequency versus V

Figure 44. Typical accuracy with RCCR=RCCR0 vs VDD= 2.4-6.0 V and temperature . . . . . . . . . . 100

Figure 45. Typical accuracy with RCCR=RCCR1 vs VDD= 2.4-6.0V and temperature. . . . . . . . . . . 100

Figure 46. Typical IDD in run mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 103

Figure 47. Typical IDD in WFI mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 103

Figure 48. Typical IDD in Slow, Slow-wait and Active-halt mode vs VDD & int

supply voltage . . . . . . . . . . . . . . . . . . . 97

10/139

ST7LITEU05 ST7LITEU09 List of figures

RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 49. Idd vs temp @VDD 5 V & int RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 50. Idd vs temp @VDD 5 V & int RC = 4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 51. Idd vs temp @VDD 5V & int RC = 2 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 52. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 53. Typical IPU vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 54. Typical RPU vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 55. Typical VOL at vDD = 2.4 V (standard pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 56. Typical vOL at vDD = 3 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 57. Typical VOL at VDD = 5 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 58. Typical VOL at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 59. Typical VOL at VDD = 3 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 60. Typical VOL at VDD = 5 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 61. Typical VDD-VOH at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 62. Typical VDD-VOH at VDD = 3 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 63. Typical VDD-VOH at VDD = 5 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 64. Typical VOL vs. VDD (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 65. Typical VDD-VOH vs. VDD (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 66. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 67. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 68. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 69. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 70. 8-lead very thin fine pitch dual flat no-lead package, package outline . . . . . . . . . . . . . . . 121

Figure 71. 8-pin plastic small outline package - 150-mil width, package outline . . . . . . . . . . . . . . . . 122

Figure 72. 8-pin plastic dual in-line outline package - 300-mil width, package outline. . . . . . . . . . . . 123

Figure 73. 16-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 125

Figure 74. ST7LITEU0 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

11/139

Introduction ST7LITEU05 ST7LITEU09

8-bit core

ALU

ADDRESS AND DATA BUS

PA3 / RESET

Port A

10-bit ADC

with watchdog

Internal Clock

Control

RAM

(128 Bytes)

PA5:0

(6 bits)

Power

supply

8-MHz RC osc.

Lite timer

memory

12-bit auto-

reload timer

Flash

2 Kbyte

LVD

AWU RC osc.

External

clock

Data EEPROM

(128 Bytes)

1 Introduction

The ST7ULTRALITE is a member of the ST7 microcontroller family. All ST7 devices are

based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

The ST7ULTRALITE features Flash memory with byte-by-byte in-circuit programming (ICP)

and in-application programming (IAP) capability.

Under software control, the ST7ULTRALITE device can be placed in Wait, Slow, or Halt

mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and

flexibility to software developers, enabling the design of highly efficient and compact

application code. In addition to standard 8-bit data management, all ST7 microcontrollers

feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data are located in Section 13 on page 95.

The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD).

For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Figure 1. General block diagram

12/139

ST7LITEU05 ST7LITEU09 Pin description

PA5 (HS) / AIN4 / CLKIN

PA3 / R E S ET

PA0 (HS) / AIN0 / ATPWM / ICCDATA

PA 2 (HS) / LTIC / AIN2

PA1 (HS) / AIN1 / ICCCLK

PA4 (HS) / AIN3 / MCO

ei4

ei3

ei2

ei1

ei0

PA5 (HS) / AIN4 / CLKIN

PA3 / RESET

PA0 (HS) / AIN0 / ATPWM / ICCDATA

PA 2 (HS) / LTIC / AIN2

PA1 (HS) / AIN1 / ICCCLK

PA4 (HS) / AIN3 / MCO

ei4

ei3

ei2

ei1

ei0

2 Pin description

Figure 2. 8-pin SO and DIP package pinout

1. HS : High sink capability

2. eix : associated external interrupt vector

Figure 3. 8-pin DFN package pinout

1. HS : High sink capability

2. eix : associated external interrupt vector

13/139

Pin description ST7LITEU05 ST7LITEU09

Reserved

ICCCLK

PA1 (HS) / AIN1

PA0 (HS) / AIN0 / ATPWM

RESET

ei4

ei3

ei1

ei0

PA5 (HS) / AIN4 / CLKIN

PA4 (HS) / AIN3 / MCO

ICCDATA

PA 2 (HS) / LTIC / AIN2

PA 3

ei2

Figure 4. 16-pin package pinout

1. For development or tool prototyping purposes only. Package not orderable in production quantities.

2. Must be tied to ground

Note: The differences versus the 8-pin packages are listed below:

The ICC signals (ICCCLK and ICCDATA) are mapped on dedicated pins; The RESET signal is mapped on a dedicated pin. It is not multiplexed with PA3. PA3 pin is always configured as output. Any change on multiplexed IO reset control registers (MUXCR1 and MUXCR2) will have no effect on PA3 functionality. Refer to “Register description” on page 41.

14/139

ST7LITEU05 ST7LITEU09 Pin description

Legend / Abbreviations for Tab le 2 :

Type: I = input, O = output, S = supply

In/Output level: C

= CMOS 0.3 V

/0.7 VDD with input trigger

Output level: HS = High sink (on N-buffer only)

Port and control configuration:

● Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog

● Output: OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 2. Device pin description

Level Port / Control

Input Output

int

float

wpu

ana

Pin No.

Pin Name

(1)

Type

Input

Output

S Main power supply

2 PA5/AIN4/CLKIN I/O CTHS X ei4 X X X Port A5

3 PA4/AIN3/MCO I/O C

(2)

4 PA3/RESET

O X XXPort A3RESET

HS X ei3 X X X Port A4

5 PA2/AIN2/LTIC I/O CTHS X ei2 X X X Port A2

6 PA1/AIN1/ICCCLK I/O C

HS X ei1 XXXPort A1

function

(after

reset)

main

Alternate function

Analog input 4 or external clock input

Analog input 3 or main clock output

(2)

Analog input 2 or lite timer input capture

Analog input 1 or In Circuit Communication Clock

Caution: During normal operation this pin must be pulledup, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in pull-up

PA 0/ A IN 0 / ATP W M /

ICCDATA

1. It is mandatory to connect all available VDD and V

2. After a reset, the multiplexed PA3/RESET pin will act as RESET

(1)

MUXCR0 and AAh to MUXCR1. For further details, please refer to Section 7.5 on page 41.

I/O C

S Ground

HS X ei0 X X X Port A0

pins to the supply voltage and all VSS and V

DDA

. To configure this pin as output (Port A3), write 55h to

Analog input 0 or Auto-Reload Timer PWM or In Circuit Communication Data

pins to ground.

SSA

15/139

0000h

RAM

Flash memory

(2K)

Interrupt & reset vectors

HW registers

0080h

007Fh

(see Ta bl e )

FFE0h

FFFFh

(see Ta b le 10 )

0100h

00FFh

Short addressing RAM (zero page)

64-Byte Stack

00FFh

0080h

00C0h

(128 Bytes)

F800h

F7FFh

Reserved

FFDFh

1 Kbyte

SECTOR 1

SECTOR 0

2K FLASH

FFFFh

FC00h

FBFFh

F800h

PROGRAM MEMORY

DEE0h

RCCRH0

RCCRL0

DEE1h

RCCRH1

RCCRL1

DEE2h

DEE3h

Data

EEPROM

1080h

107Fh

1000h

0FFFh

Reserved

(128 Bytes)

3 Register & memory map

As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbyte of user program memory. The RAM space includes up to 64 bytes for the stack from 00C0h to 00FFh.

The highest address bytes contain the user reset and interrupt vectors.

The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (FC00-FFFFh).

The size of Flash Sector 0 and other device options are configurable by Option byte.

Important: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.

Figure 5. Memory map

Note: DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are

1. see Section 7.2 on page 32.

special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibration values

16/139

locations) has been erased (after the readout protection removal), then the RC calibration values can still be obtained through these addresses.

ST7LITEU05 ST7LITEU09 Register & memory map

Table 3. Hardware register map

Address Block Register label Register name

0000h 0001h 0002h

0003h to

000Ah

000Bh

000Ch

000Dh 000Eh 000Fh

0010h 0011h 0012h 0013h

0014h to

0016h

0017h 0018h

0019h to

002Eh

Por t A

Lite

timer

Auto-reload

timer

Auto-reload

timer

PA DR PADDR PA OR

LT CS R LT IC R

AT CS R CNTRH CNTRL AT RH AT RL PWMCR PWM0CSR

DCR0H DCR0L

Port A data register Port A data direction register Port A option register

Reserved area (8 bytes)

Lite timer control/status register Lite timer input capture register

Timer control/status register Counter register high Counter register low Auto-reload register high Auto-reload register low PWM output control register PWM 0 control/status register

Reserved area (3 bytes)

PWM 0 duty cycle register high PWM 0 duty cycle register low

Reserved area (22 bytes)

Reset

status

00h

08h

02h

0xh 00h

00h 00h 00h 00h 00h 00h 00h

00h 00h

(2)

(3)

(1)

Remarks

(1)

R/W R/W R/W

R/W

Read only

R/W Read only Read only

R/W

0002Fh Flash FCSR Flash control/status register 00h R/W

00030h EEPROM EECSR Data EEPROM control/status register 00h R/W

0031h to

0033h

0034h 0035h 0036h

ADC

ADCCSR ADCDRH ADCDRL

Reserved area (3 bytes)

A/D control status register A/D data register high A/D data register low

00h xxh 00h

R/W Read only

R/W

0037h ITC EICR1 External interrupt control register 1 00h R/W

0038h MCC MCCSR Main clock control/status register 00h R/W

0039h

003Ah

003Bh to

003Ch

Clock and

reset

RCCR SICSR

RC oscillator control register System integrity control/status register

Reserved area (2 bytes)

FFh

0000 0x00b

R/W

003Dh ITC EICR2 External interrupt control register 2 00h R/W

003Eh AVD AVDTHCR AVD threshold selection register 03h R/W

003Fh

0040h to

0046h

0047h 0048h

Clock

controller

MuxIO-

reset

CKCNTCSR Clock controller control/status register 09h R/W

Reserved area (7 bytes)

MUXCR0 MUXCR1

Mux IO-reset control register 0 Mux IO-reset control register 1

00h 00h

R/W

17/139

Table 3. Hardware register map (continued)

Address Block Register label Register name

0049h

004Ah

AWU

004Bh 004Ch 004Dh 004Eh

(4)

004Fh

0050h

0051h to

007Fh

1. Legend: x=undefined, R/W=read/write

2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

3. The bits associated with unavailable pins must always keep their reset value.

4. For a description of the DM registers, see the ST7 ICC Protocol Reference Manual.

AWUPR AWUCSR

DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L

AWU prescaler register AWU control/status register

DM control register DM status register DM breakpoint register 1 high DM breakpoint register 1 low DM breakpoint register 2 high DM breakpoint register 2 low

Reserved area (47 bytes)

Reset

status

FFh 00h

00h 00h 00h 00h 00h 00h

(1)

Remarks

(1)

R/W R/W

R/W R/W R/W R/W R/W R/W

18/139

ST7LITEU05 ST7LITEU09 Flash program memory

4 Flash program memory

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main features

● ICP (In-circuit programming)

● IAP (In-application programming)

● ICT (In-circuit testing) for downloading and executing user application test patterns in

RAM

● Sector 0 size configurable by option byte

● Readout and write protection

4.3 Programming modes

The ST7 can be programmed in three different ways:

● Insertion in a programming tool. In this mode, Flash sectors 0 and 1 and option byte

row can be programmed or erased.

● In-Circuit Programming. In this mode, Flash sectors 0 and 1 and option byte row can be

programmed or erased without removing the device from the application board.

● In-application programming. In this mode, sector 1 can be programmed or erased

without removing the device from the application board and while the application is running.

4.3.1 In-circuit programming (ICP)

ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

● Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a

specific signal sequence on the ICCCLK/DATA pins while the RESET When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 system memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

● Download ICP driver code in RAM from the ICCDATA pin

● Execute ICP driver code in RAM to program the Flash memory

pin is pulled low.

19/139

Flash program memory ST7LITEU05 ST7LITEU09

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

HE10 CONNECTOR TYPE

APPLICATION POWER SUPPLY

246810

97 5 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

ST7

CLKIN

OPTIONAL

See Note 1

See Note 1 and Caution

See Note 2

APPLICATION RESET SOURCE

APPLICATION

I/O

(See Note 4)

3.3kΩ

(See Note 5)

Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP driver program previously programmed in sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.4 ICC interface

ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:

● RESET: device reset

● V

● ICCCLK: ICC output serial clock pin (see note 1)

● ICCDATA: ICC input serial data pin

● CLKIN: main clock input for external source

● V

: device power supply ground

: application board power supply (see note 3)

Figure 6. Typical ICC interface

1. If the ICCCLK or ICCDATA pins are only usedas outputs in the application, no signal isolation is necessary. As soon as the programming tool isplugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins arenot available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the programmingtool documentation for recommended resistor values.

2. During the ICP session, the programming tool must control the RESET between the programming tool and the application reset circuit if it drives more than 5 mA at high level (push pull output or pull-up resistor < 1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor >1 K, no additional components are needed. In all cases the user must

20/139

pin. This can lead to conflicts

ST7LITEU05 ST7LITEU09 Flash program memory

ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual.

4. Pin 9 has to be connected to the CLKIN pin of the ST7 when ICC mode is selected with option bytes disabled (35-pulse ICC entry mode). When option bytes are enabled (38-pulse ICC entry mode), the internal RC clock is forced, regardless of the selection in the option byte.

5. A serial resistor must be connected to ICC connector pin 6 in order to prevent contention on PA3/RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin forces the opposite state in output mode. The resistor value is defined to limit the current below 2 mA at 5 V. If PA3 is used as output push-pull, then the application must be switched off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to drive the RESET pin below V when a pull-up is placed on PA3 for application reasons.

, special care must also be taken

Caution: During normal operation, ICCCLK pin must be pulled- up, internally or externally (external

pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.

4.5 Memory protection

There are two different types of memory protection: readout protection and write/erase protection which can be applied individually.

4.5.1 Readout protection

Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Program memory is protected.

In Flash devices, this protection is removed by reprogramming the option. In this case, program memory is automatically erased, and the device can be reprogrammed.

Readout protection selection depends on the device type:

● In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

● In ROM devices it is enabled by mask option specified in the option list.

4.5.2 Flash write/erase protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content.

Warning: Once set, Write/erase protection can never be removed. A

write-protected flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

21/139

Flash program memory ST7LITEU05 ST7LITEU09

4.6 Related documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

4.7 Register description

4.7.1 Flash control/status register (FCSR)

This register controls the XFlash erasing and programming using ICP, IAP or other programming methods.

1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

Reset value: 000 0000 (00h)

7 0

Address

(Hex.)

002Fh

00000OPTLATPGM

Read/write

label

FCSR

Reset Value

76543210

OPT

LAT

PGM

22/139

ST7LITEU05 ST7LITEU09 Data EEPROM

EECSR

HIGH VOLTAGE

PUMP

0 E2LAT00 0 0 0 E2PGM

EEPROM

MEMORY MATRIX

(1 ROW = 32 x 8 BITS)

ADDRESS DECODER

DATA

MULTIPLEXER

32 x 8 BITS

DATA LATCHES

ROW

DECODER

DATA BUS

128128

ADDRESS BUS

5 Data EEPROM

5.1 Introduction

The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter.

5.2 Main features

● Up to 32 bytes programmed in the same cycle

● EEPROM mono-voltage (charge pump)

● Chained erase and programming cycles

● Internal control of the global programming cycle duration

● Wait mode management

● Readout protection

Figure 7. EEPROM block diagram

5.3 Memory access

The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes.

5.3.1 Read operation (E2LAT=0)

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared.

23/139

Data EEPROM ST7LITEU05 ST7LITEU09

READ MODE

E2LAT=0

E2PGM=0

WRITE MODE

E2LAT=1

E2PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 32 BYTES

IN EEPROM AREA

(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

E2LAT=1

E2PGM=1 (set by software)

E2LAT

CLEARED BY HARDWARE

On this device, data EEPROM can also be used to execute machine code. Take care not to write to the data EEPROM while executing from it. This would result in an unexpected code being executed.

5.3.2 Write operation (E2LAT=1)

To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 32 data latches according to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to

32) are programmed in the EEPROM cells. The effective high address (row) is determined

by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.

Note: Care should be taken during the programming cycle. Writing to the same memory location

will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data. This note is ilustrated by the Figure 10.

Figure 8. Data EEPROM programming flowchart

24/139

ST7LITEU05 ST7LITEU09 Data EEPROM

Byte 1 Byte 2 Byte 32

PHASE 1

Programming cycle

Read operation impossible

PHASE 2

Read operation possible

E2LAT bit

E2PGM bit

Writing data latches Waiting E2PGM and E2LAT to fall

Set by USER application

Cleared by hardware

⇓ Row / byte ⇒ 0123 ... 30 31 Physical address

0 00h...1Fh

1 20h...3Fh

...

N Nx20h...Nx20h+1Fh

ROW

DEFINITION

Figure 9. Data EEPROM write operation

1. If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed.

5.4 Power saving modes

5.4.1 Wait mode

The data EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-Halt mode.The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the data EEPROM will finish the cycle and then enter Wait mode.

5.4.2 Active-halt mode

Refer to Wait mode.

5.4.3 Halt mode

The data EEPROM immediately enters Halt mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.

5.5 Access error handling

If a read access occurs while E2LAT=1, then the data bus will not be driven.

If a write access occurs while E2LAT=0, then the data on the bus will not be latched.

If a programming cycle is interrupted (by a Reset action), the integrity of the data in memory will not be guaranteed.

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Data EEPROM ST7LITEU05 ST7LITEU09

LAT

ERASE CYCLE WRITE CYCLE

PGM

PROG

Read operation not possible

WRITE OF

DATA LATCHES

Read operation possible

Internal programming voltage

5.6 Data EEPROM readout protection

The readout protection is enabled through an option bit (see option byte section).

When this option is selected, the programs and data stored in the EEPROM memory are protected against readout (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the option byte, the entire Program memory and EEPROM is first automatically erased.

Note: Both program memory and data EEPROM are protected using the same option bit.

Figure 10. Data EEPROM programming cycle

5.7 Register description

5.7.1 EEPROM control/status register (EECSR)

Address: 0030h

Reset value: 0000 0000 (00h)

7 0

000000E2LATE2PGM

Read/write

Bits 7:2 = Reserved, forced by hardware to 0

Bit 1 = E2LAT Latch access transfer bit:

This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared

0: Read mode 1: Write mode

Bit 0 = E2PGM Programming control and status bit

This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware.

0: Programming finished or not yet started 1: Programming cycle is in progress

Note: If the E2PGM bit is cleared during the programming cycle, the memory data is not

guaranteed.

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ST7LITEU05 ST7LITEU09 Data EEPROM

Table 4. Data EEPROM register map and reset values

Address

(Hex.)

0030h

Label

EECSR

Reset Value

76543210

E2LAT0E2PGM

000000

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Central processing unit ST7LITEU05 ST7LITEU09

6 Central processing unit

6.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.

6.2 Main features

● 63 basic instructions

● Fast 8-bit by 8-bit multiply

● 17 main addressing modes

● Two 8-bit index registers

● 16-bit stack pointer

● Low power modes

● Maskable hardware interrupts

● Non-maskable software interrupt

6.3 CPU registers

The six CPU registers shown in Figure 11 are not present in the memory mapping and are accessed by specific instructions.

6.3.1 Accumulator (A)

The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

6.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The cross-assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

6.3.3 Program counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is the LSB) and PCH (Program Counter High which is the MSB).

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ST7LITEU05 ST7LITEU09 Central processing unit

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C11HI NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X1 1 X1 XX

RESET VALUE = XXh

Figure 11. CPU registers

1. X = undefined value

6.3.4 Condition code register (CC)

The 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

Reset value: 111x 1xxx

7 0

111H INZC

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H Half carry bit

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 3 = I Interrupt mask

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM

and JRNM instructions.

bit

Read/write

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Central processing unit ST7LITEU05 ST7LITEU09

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By

default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative bit

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7

bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic

1). This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero bit

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC

instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

6.3.5 Stack pointer (SP)

Reset Value: 00 FFh

15 8

00000000

7 0

1 1 SP5 SP4 SP3 SP2 SP1 SP0

The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 12).

bit

Read/write

Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.

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