8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI
■Memories
–1K or 1.5 Kbytes single voltage Flash Program memory with read-out protection, In-Cir- cuit and In-Application Programming (ICP and IAP). 10 K write/erase cycles guaranteed, data retention: 20 years at 55 °C.
–128 bytes RAM.
–128 bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed, data retention: 20 years at 55 °C.
■Clock, Reset and Supply Management
–3-level low voltage supervisor (LVD) and auxiliary voltage detector (AVD) for safe poweron/off procedures
–Clock sources: internal 1MHz RC 1% oscillator or external clock
–PLL x4 or x8 for 4 or 8 MHz internal clock
–Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
■Interrupt Management
–10 interrupt vectors plus TRAP and RESET
–4 external interrupt lines (on 4 vectors)
■I/O Ports
–13 multifunctional bidirectional I/O lines
–9 alternate function lines
–6 high sink outputs
■2 Timers
–One 8-bit Lite Timer (LT) with prescaler including: watchdog, 1 realtime base and 1 input capture.
Device Summary
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SO16 |
DIP16 |
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150” |
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QFN20
–One 12-bit Auto-reload Timer (AT) with output compare function and PWM
■1 Communication Interface
–SPI synchronous serial interface
■A/D Converter
–8-bit resolution for 0 to VDD
–Fixed gain Op-amp for 11-bit resolution in 0 to 250 mV range (@ 5V VDD)
–5 input channels
■Instruction Set
–8-bit data manipulation
–63 basic instructions with illegal opcode detection
–17 main addressing modes
–8 x 8 unsigned multiply instruction
■Development Tools
–Full hardware/software development package
Features |
ST7LITESxY0 (ST7SUPERLITE) |
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ST7LITE0xY0 |
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ST7LITES2Y0 |
ST7LITES5Y0 |
ST7LITE02Y0 |
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ST7LITE05Y0 |
ST7LITE09Y0 |
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Program memory - bytes |
1K |
1K |
1.5K |
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1.5K |
1.5K |
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RAM (stack) - bytes |
128 (64) |
128 (64) |
128 (64) |
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128 (64) |
128 (64) |
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Data EEPROM - bytes |
- |
- |
- |
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128 |
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LT Timer w/ Wdg, |
LT Timer w/ Wdg, |
LT Timer w/ Wdg, |
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LT Timer |
w/ Wdg, |
Peripherals |
AT Timer w/ 1 PWM, |
AT Timer w/ 1 PWM, |
AT Timer w/ 1 PWM, |
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AT Timer w/ 1 PWM, SPI, |
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SPI |
SPI, 8-bit ADC |
SPI |
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8-bit ADC w/ Op-Amp |
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Operating Supply |
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2.4V to 5.5V |
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CPU Frequency |
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1MHz RC 1% + PLLx4/8MHz |
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Operating Temperature |
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-40°C to +85°C |
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Packages |
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SO16 150”, DIP16, QFN20 |
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Rev 6 |
November 2007 |
1/124 |
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1 |
Table of Contents
ST7LITE0xY0, ST7LITESxY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
6.2 |
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
6.3 |
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
37 |
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9.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
37 |
9.2 |
SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
37 |
9.3 |
WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
38 |
9.4 |
ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
39 |
2/124
2
Table of Contents
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.1 |
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
42 |
10.2 |
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
42 |
10.3 |
UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
46 |
10.4 |
LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
46 |
10.5 |
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
46 |
10.6 |
I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
46 |
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
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11.1 |
LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
11.2 |
12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
53 |
11.3 |
SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
59 |
11.4 |
8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
70 |
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
75 |
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS . . . . . . . . . . . . . 93 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 102 13.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 112
15.1 |
OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
112 |
15.2 |
DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . |
114 |
15.3 |
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
117 |
15.4 |
ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
118 |
16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.1 |
EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
16.2 |
IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARD- |
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WARE WATCHDOG OPTION 121 |
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16.3 |
IN-CIRCUIT DEBUGGING WITH HARDWARE WATCHDOG . . . . . . . . . . . . . . . . . . . |
121 |
16.4 |
RECOMMENDATIONS WHEN LVD IS ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
16.5 |
CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . |
121 |
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3/124
3
Table of Contents
To obtain the most recent version of this datasheet, please check at www.st.com
Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 121.
4/124
1
ST7LITE0xY0, ST7LITESxY0
The ST7LITE0x and ST7SUPERLITE (ST7LITESx) are members of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.
The ST7LITE0x and ST7SUPERLITE feature FLASH memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming (IAP) capability.
Under software control, the ST7LITE0x and ST7SUPERLITE devices can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state.
Figure 1. General Block Diagram
The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
For easy reference, all parametric data are located in section 13 on page 81.
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Internal |
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1 MHz. RC OSC |
CLOCK |
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+ |
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PLL x 4 or x 8 |
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LITE TIMER |
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LVD/AVD |
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w/ WATCHDOG |
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VDD |
POWER |
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PORT A |
PA7:0 |
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SUPPLY |
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(8 bits) |
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VSS |
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ADDRESS |
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12-BIT AUTO- |
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RESET |
CONTROL |
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RELOAD TIMER |
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8-BIT CORE |
AND |
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ALU |
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DATA |
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SPI |
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BUS |
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FLASH |
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MEMORY |
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PORT B |
PB4:0 |
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(1 or 1.5K Bytes) |
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(5 bits) |
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8-BIT ADC RAM
(128 Bytes)
DATA EEPROM
(128 Bytes)
5/124
1
ST7LITE0xY0, ST7LITESxY0
Figure 2. 20-Pin QFN Package Pinout
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PB0/SS/AIN0 |
V |
V |
PA0(HS)/LTIC |
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DD |
SS |
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20 |
19 |
18 |
17 |
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1 |
e3 |
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e0 |
16 |
PA1 (HS) |
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RESET |
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NC |
2 |
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15 |
PA2 (HS)/ATPWM0 |
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NC |
3 |
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14 |
PA3 (HS) |
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NC |
4 |
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13 |
NC |
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MISO/AIN2/PB2 |
5 |
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12 |
PA4 (HS) |
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SCK/AIN1/PB1 |
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ei2 |
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ei1 |
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11 |
PA5 (HS)/ICCDATA |
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8 |
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10 |
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MOSI/AIN3/PB3 |
CLKIN/AIN4/PB4 |
PA7 |
MCO/ICCCLK/PA6 |
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(HS) |
20mA High sink capability |
eix |
associated external interrupt vector |
Figure 3. 16-Pin SO and DIP Package Pinout
k
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VSS |
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PA0 (HS)/LTIC |
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ei0 |
16 |
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VDD |
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PA1 (HS) |
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RESET |
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3 |
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14 |
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PA2 (HS)/ATPWM0 |
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SS/AIN0/PB0 |
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ei3 |
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PA3 (HS) |
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SCK/AIN1/PB1 |
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MISO/AIN2/PB2 |
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PA5 (HS)/ICCDATA |
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MOSI/AIN3/PB3 |
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7 |
ei2 |
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10 |
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PA6/MCO/ICCCLK |
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CLKIN/AIN4/PB4 |
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ei1 |
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PA7 |
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(HS) |
20mA high sink capability |
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eix |
associated external interrupt vector |
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6/124
1
ST7LITE0xY0, ST7LITESxY0
PIN DESCRIPTION (Cont’d) |
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Legend / Abbreviations for Table 1: |
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Type: |
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I = input, O = output, S = supply |
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In/Output level: C= CMOS 0.15VDD/0.85VDD with input trigger |
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CT= CMOS 0.3VDD/0.7VDD with input trigger |
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Output level: |
HS = 20mA high sink (on N-buffer only) |
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Port and control configuration: |
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– |
Input: |
float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog |
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– |
Output: |
OD = open drain, PP = push-pull |
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Table 1. Device Pin Description |
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Pin n° |
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Level |
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Port / Control |
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Type |
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QFN20 |
SO16/DIP16 |
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Input |
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Output |
float |
wpu |
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int |
ana |
OD |
PP |
Main |
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Input |
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Output |
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Pin Name |
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Function |
Alternate Function |
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(after reset) |
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18 |
1 |
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VSS |
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S |
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Ground |
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19 |
2 |
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VDD |
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S |
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Main power supply |
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1 |
3 |
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I/O |
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CT |
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X |
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X |
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Top priority non maskable interrupt (active low) |
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RESET |
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I/O |
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CT |
X |
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ei3 |
X |
X |
X |
Port B0 |
ADC Analog Input 0 or SPI Slave |
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20 |
4 |
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PB0/AIN0/SS |
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Select (active low) |
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ADC Analog Input 1 or SPI Clock |
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Caution: No negative current in- |
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5 |
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PB1/AIN1/SCK |
I/O |
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CT |
X |
X |
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X |
Port B1 |
jection allowed on this pin. For |
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details, refer to section 13.2.2 on |
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page 82 |
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5 |
6 |
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PB2/AIN2/MISO |
I/O |
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CT |
X |
X |
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X |
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X |
Port B2 |
ADC Analog Input 2 or SPI Mas- |
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ter In/ Slave Out Data |
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7 |
7 |
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PB3/AIN3/MOSI |
I/O |
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CT |
X |
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ei2 |
X |
X |
X |
Port B3 |
ADC Analog Input 3 or SPI Mas- |
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ter Out / Slave In Data |
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8 |
8 |
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PB4/AIN4/CLKIN |
I/O |
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CT |
X |
X |
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X |
Port B4 |
ADC Analog Input 4 or External |
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clock input |
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9 |
9 |
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PA7 |
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I/O |
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CT |
X |
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ei1 |
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X |
X |
Port A7 |
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Main Clock Output/In Circuit |
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Communication Clock. |
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Caution: During normal opera- |
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tion this pin must be pulledup, |
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internally or externally (external |
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10 |
10 |
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PA6 /MCO/ |
I/O |
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CT |
X |
X |
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X |
X |
Port A6 |
pull-up of 10k mandatory in noisy |
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ICCCLK |
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environment). This is to avoid en- |
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tering ICC mode unexpectedly |
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during a reset. In the application, |
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even if the pin is configured as |
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output, any reset will put it back in |
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input pull-up |
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11 |
11 |
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PA5/ |
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I/O |
CT |
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HS |
X |
X |
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X |
X |
Port A5 |
In Circuit Communication Data |
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ICCDATA |
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12 |
12 |
PA4 |
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I/O |
CT |
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HS |
X |
X |
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X |
X |
Port A4 |
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14 |
13 |
PA3 |
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I/O |
CT |
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HS |
X |
X |
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X |
X |
Port A3 |
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7/124 |
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1
ST7LITE0xY0, ST7LITESxY0
Pin n° |
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Level |
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Port / Control |
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Type |
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QFN20 |
SO16/DIP16 |
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Input |
Output |
float |
wpu |
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int |
ana |
OD |
PP |
Main |
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Pin Name |
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Input |
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Output |
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Function |
Alternate Function |
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(after reset) |
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15 |
14 |
PA2/ATPWM0 |
I/O |
CT |
HS |
X |
X |
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X |
X |
Port A2 |
Auto-Reload Timer PWM0 |
16 |
15 |
PA1 |
I/O |
CT |
HS |
X |
X |
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X |
X |
Port A1 |
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17 |
16 |
PA0/LTIC |
I/O |
CT |
HS |
X |
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ei0 |
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X |
X |
Port A0 |
Lite Timer Input Capture |
Note:
In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.
8/124
1
ST7LITE0xY0, ST7LITESxY0
As shown in Figure 4 and Figure 5, the MCU is capable of addressing 64K bytes of memories and I/ O registers.
The available memory locations consist of up to 128 bytes of register locations, 128 bytes of RAM, 128 bytes of data EEPROM and up to 1.5 Kbytes of user program memory. The RAM space includes up to 64 bytes for the stack from 0C0h to 0FFh.
The highest address bytes contain the user reset and interrupt vectors.
The size of Flash Sector 0 is configurable by Option byte.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
Figure 4. Memory Map (ST7LITE0x)
0000h |
0080h |
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HW Registers |
Short Addressing |
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(see Table 2) |
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RAM (zero page) |
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007Fh |
00BFh |
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0080h |
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RAM |
00C0h |
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(128 Bytes) |
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64 Bytes Stack |
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00FFh |
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0100h |
00FFh |
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Reserved |
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0FFFh |
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1000h |
RCCR0 |
1000h |
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Data EEPROM |
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RCCR1 |
(128 Bytes) |
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1001h |
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107Fh |
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see section 7.1 on page 24 |
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1080h |
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Reserved |
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1.5K FLASH |
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PROGRAM MEMORY |
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F9FFh |
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FA00h |
FA00h |
0.5 Kbytes |
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Flash Memory |
FBFFh |
SECTOR 1 |
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FC00h |
1 Kbytes |
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(1.5K) |
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FFFFh |
SECTOR 0 |
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FFDFh |
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FFDEh |
RCCR0 |
FFE0h |
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Interrupt & Reset Vectors |
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(see Table 6) |
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FFDFh |
RCCR1 |
FFFFh |
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see section 7.1 on page 24 |
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9/124
1
ST7LITE0xY0, ST7LITESxY0
REGISTER AND MEMORY MAP (Cont’d)
Figure 5. Memory Map (ST7SUPERLITE)
0000h |
0080h |
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HW Registers |
Short Addressing |
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(see Table 2) |
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RAM (zero page) |
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007Fh |
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00BFh |
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0080h |
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RAM |
00C0h |
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(128 Bytes) |
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64 Bytes Stack |
00FFh |
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0100h |
00FFh |
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Reserved |
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1K FLASH |
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PROGRAM MEMORY |
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FBFFh |
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FC00h |
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FC00h |
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0.5 Kbytes |
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Flash Memory |
FDFFh |
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SECTOR 1 |
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FE00h |
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0.5 Kbytes |
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SECTOR 0 |
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FFFFh |
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FFDFh |
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FFE0h |
Interrupt & Reset Vectors |
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FFDEh |
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RCCR0 |
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(see Table 6) |
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FFFFh |
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FFDFh |
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RCCR1 |
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see section 7.1 on page 24
10/124
1
ST7LITE0xY0, ST7LITESxY0
REGISTER AND MEMORY MAP (Cont’d)
Legend: x=undefined, R/W=read/write
Table 2. Hardware Register Map
Address |
Block |
Register |
Register Name |
Reset |
Remarks |
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Label |
Status |
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0000h |
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PADR |
Port A Data Register |
00h1) |
R/W |
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0001h |
Port A |
PADDR |
Port A Data Direction Register |
00h |
R/W |
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0002h |
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PAOR |
Port A Option Register |
40h |
R/W |
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0003h |
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PBDR |
Port B Data Register |
E0h 1) |
R/W |
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0004h |
Port B |
PBDDR |
Port B Data Direction Register |
00h |
R/W |
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0005h |
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PBOR |
Port B Option Register |
00h |
R/W2) |
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0006h to |
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Reserved area (5 bytes) |
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000Ah |
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000Bh |
LITE |
LTCSR |
Lite Timer Control/Status Register |
xxh |
R/W |
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000Ch |
TIMER |
LTICR |
Lite Timer Input Capture Register |
xxh |
Read Only |
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000Dh |
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ATCSR |
Timer Control/Status Register |
00h |
R/W |
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000Eh |
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CNTRH |
Counter Register High |
00h |
Read Only |
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000Fh |
AUTO-RELOAD |
CNTRL |
Counter Register Low |
00h |
Read Only |
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0010h |
ATRH |
Auto-Reload Register High |
00h |
R/W |
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0011h |
TIMER |
ATRL |
Auto-Reload Register Low |
00h |
R/W |
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0012h |
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PWMCR |
PWM Output Control Register |
00h |
R/W |
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0013h |
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PWM0CSR |
PWM 0 Control/Status Register |
00h |
R/W |
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0014h to |
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Reserved area (3 bytes) |
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0016h |
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0017h |
AUTO-RELOAD |
DCR0H |
PWM 0 Duty Cycle Register High |
00h |
R/W |
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0018h |
TIMER |
DCR0L |
PWM 0 Duty Cycle Register Low |
00h |
R/W |
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0019h to |
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Reserved area (22 bytes) |
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002Eh |
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0002Fh |
FLASH |
FCSR |
Flash Control/Status Register |
00h |
R/W |
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00030h |
EEPROM |
EECSR |
Data EEPROM Control/Status Register |
00h |
R/W |
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0031h |
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SPIDR |
SPI Data I/O Register |
xxh |
R/W |
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0032h |
SPI |
SPICR |
SPI Control Register |
0xh |
R/W |
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0033h |
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SPICSR |
SPI Control/Status Register |
00h |
R/W |
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0034h |
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ADCCSR |
A/D Control Status Register |
00h |
R/W |
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0035h |
ADC |
ADCDR |
A/D Data Register |
00h |
Read Only |
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0036h |
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ADCAMP |
A/D Amplifier Control Register |
00h |
R/W |
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0037h |
ITC |
EICR |
External Interrupt Control Register |
00h |
R/W |
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0038h |
CLOCKS |
MCCSR |
Main Clock Control/Status Register |
00h |
R/W |
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0039h |
RCCR |
RC oscillator Control Register |
FFh |
R/W |
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11/124
1
ST7LITE0xY0, ST7LITESxY0
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Status |
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003Ah |
SI |
SICSR |
System Integrity Control/Status Register |
0xh |
R/W |
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003Bh to |
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Reserved area (69 bytes) |
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007Fh |
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Notes:
1.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2.The bits associated with unavailable pins must always keep their reset value.
12/124
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ST7LITE0xY0, ST7LITESxY0
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming.
The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.
■ICP (In-Circuit Programming)
■IAP (In-Application Programming)
■ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM
■Sector 0 size configurable by option byte
■Read-out and write protection
The ST7 can be programmed in three different ways:
–Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM can be programmed or erased.
–In-Circuit Programming. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM can be programmed or erased without removing the device from the application board.
–In-Application Programming. In this mode, sector 1 and data EEPROM can be programmed or erased without removing the device from the application board and while the application is running.
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.
–Download ICP Driver code in RAM from the ICCDATA pin
–Execute ICP Driver code in RAM to program the FLASH memory
Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
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ST7LITE0xY0, ST7LITESxY0
FLASH PROGRAM MEMORY (Cont’d)
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:
–RESET: device reset
–VSS: device power supply ground
–ICCCLK: ICC output serial clock pin
–ICCDATA: ICC input serial data pin
–CLKIN: main clock input for external source
–VDD: application board power supply (optional, see Note 3)
Notes:
1.If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.
2.During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at
Figure 6. Typical ICC Interface
high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.
3.The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.
4.Pin 9 has to be connected to the CLKIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte.
Caution: During normal operation, ICCCLK pin must be pulledup, internally or externally (external pull-up of 10K mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
(See Note 3)
OPTIONAL
(See Note 4)
APPLICATION
POWER SUPPLY
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CLKIN |
VDD |
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ST7
ICC CONNECTOR
HE10 CONNECTOR TYPE
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APPLICATION BOARD |
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APPLICATION |
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RESET SOURCE |
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See Note 2 |
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See Note 1 and Caution |
APPLICATION |
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I/O |
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See Note 1 |
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RESET |
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ICCCLK |
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ICCDATA |
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14/124
1
ST7LITE0xY0, ST7LITESxY0
FLASH PROGRAM MEMORY (Cont’d)
There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.
Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data E2 memory are protected.
In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E2 memory are automatically erased, and the device can be reprogrammed.
Read-out protection selection depends on the device type:
–In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
–In ROM devices it is enabled by mask option specified in the Option List.
Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E2 data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content.
Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable.
Table 3. FLASH Register Map and Reset Values
Write/erase protection is enabled through the FMP_W bit in the option byte.
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
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0 |
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0 |
0 |
0 |
0 |
0 |
OPT |
LAT |
PGM |
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Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations.
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.
Address |
Register |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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(Hex.) |
Label |
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002Fh |
FCSR |
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OPT |
LAT |
PGM |
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Reset Value |
0 |
0 |
0 |
0 |
0 |
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15/124
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ST7LITE0xY0, ST7LITESxY0
The Electrically Erasable Programmable Read Only Memory can be used as a non-volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter.
■Up to 32 bytes programmed in the same cycle
■EEPROM mono-voltage (charge pump)
■Chained erase and programming cycles
■Internal control of the global programming cycle duration
■WAIT mode management
■Read-out protection
Figure 7. EEPROM Block Diagram
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HIGH VOLTAGE |
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PUMP |
EECSR |
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E2LAT E2PGM |
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4 |
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EEPROM |
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ROW |
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DECODER |
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MEMORY MATRIX |
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DECODER |
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(1 ROW = 32 x 8 BITS) |
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128 |
128 |
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4 |
DATA |
32 x 8 BITS |
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MULTIPLEXER |
DATA LATCHES |
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4 |
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ADDRESS BUS |
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DATA BUS |
16/124
1
ST7LITE0xY0, ST7LITESxY0
DATA EEPROM (Cont’d)
The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes.
Read Operation (E2LAT = 0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared.
On this device, Data EEPROM can also be used to execute machine code. Take care not to write to the Data EEPROM while executing from it. This would result in an unexpected code being executed.
Write Operation (E2LAT = 1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs,
Figure 8. Data EEPROM Programming Flowchart
the value is latched inside the 32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: Only the five Least Significant Bits of the address can change.
At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.
Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit.
It is not possible to read the latched data. This note is illustrated by the Figure 10.
READ MODE |
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WRITE MODE |
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E2LAT = 0 |
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E2LAT = 1 |
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E2PGM = 0 |
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E2PGM = 0 |
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READ BYTES |
WRITE UP TO 32 BYTES |
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IN EEPROM AREA |
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IN EEPROM AREA |
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START PROGRAMMING CYCLE |
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E2LAT=1 |
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E2PGM=1 (set by software) |
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1 |
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E2LAT |
CLEARED BY HARDWARE
17/124
1
ST7LITE0xY0, ST7LITESxY0
DATA EEPROM (Cont’d)
Figure 9. Data E2PROM Write Operation
Row / Byte |
0 |
1 |
2 |
3 |
... |
30 31 |
Physical Address |
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00h...1Fh |
DEFINITION |
1 |
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20h...3Fh |
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... |
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N |
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Nx20h...Nx20h+1Fh |
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Read operation impossible |
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Byte 1 |
Byte 2 |
Byte 32 |
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Programming cycle |
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PHASE 2 |
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Writing data latches |
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Waiting E2PGM and E2LAT to fall |
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E2LAT bit |
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Set by USER application |
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E2PGM bit |
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Note: If a programming cycle is interrupted (by RESET action), the integrity of the data in memory will not be guaranteed.
18/124
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ST7LITE0xY0, ST7LITESxY0
DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES Wait mode
The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active Halt mode.The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode.
Active Halt mode
Refer to Wait mode.
Halt mode
The DATA EEPROM immediately enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.
If a read access occurs while E2LAT = 1, then the data bus will not be driven.
If a write access occurs while E2LAT = 0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by RESET action), the integrity of the data in memory will not be guaranteed.
The read-out protection is enabled through an option bit (see option byte section).
When this option is selected, the programs and data stored in the EEPROM memory are protected against read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire Program memory and EEPROM is first automatically erased.
Note: Both Program Memory and data EEPROM are protected using the same option bit.
Figure 10. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE |
READ OPERATION POSSIBLE |
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WRITE CYCLE |
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tPROG |
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19/124
1
ST7LITE0xY0, ST7LITESxY0
DATA EEPROM (Cont’d)
EEPROM CONTROL/STATUS REGISTER (EEC-
SR)
Read/Write
Reset Value: 0000 0000 (00h)
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E2LAT |
E2PGM |
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Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared.
0:Read mode
1:Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware.
0:Programming finished or not yet started
1:Programming cycle is in progress
Note: If the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed.
Table 4. DATA EEPROM Register Map and Reset Values
Address |
Register |
7 |
6 |
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4 |
3 |
2 |
1 |
0 |
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Label |
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0030h |
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E2PGM |
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Reset Value |
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20/124
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ST7LITE0xY0, ST7LITESxY0
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
■63 basic instructions
■Fast 8-bit by 8-bit multiply
■17 main addressing modes
■Two 8-bit index registers
■16-bit stack pointer
■Low power modes
■Maskable hardware interrupts
■Non-maskable software interrupt
The six CPU registers shown in Figure 11 are not present in the memory mapping and are accessed by specific instructions.
Figure 11. CPU Registers
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
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ACCUMULATOR |
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RESET VALUE = XXh |
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Y INDEX REGISTER |
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PCL |
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21/124
1
ST7LITE0xY0, ST7LITESxY0
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
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The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.
0:No half carry has occurred.
1:A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.
0:Interrupts are enabled.
1:Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible
22/124
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0:The result of the last operation is positive or null.
1:The result of the last operation is negative (that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0:The result of the last operation is different from zero.
1:The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0:No overflow or underflow has occurred.
1:An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
1
ST7LITE0xY0, ST7LITESxY0
CPU REGISTERS (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 00 FFh
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The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 12).
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 12.
–When an interrupt is received, the SP is decremented and the context is pushed on the stack.
–On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 12. Stack Manipulation Example
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Stack Higher Address = 00FFh
Stack Lower Address = 00C0h
23/124
1
ST7LITE0xY0, ST7LITESxY0
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components.
Main features
■Clock Management
–1 MHz internal RC oscillator (enabled by option byte)
–External Clock Input (enabled by option byte)
–PLL for multiplying the frequency by 4 or 8 (enabled by option byte)
■Reset Sequence Manager (RSM)
■System Integrity Management (SI)
–Main supply Low voltage detection (LVD) with reset generation (enabled by option byte)
–Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (enabled by option byte)
The ST7 contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage. It must be calibrated to obtain the frequency required in the application. This is done by software writing a calibration value in the RCCR (RC Control Register).
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3.0 and 5V VDD supply voltages at 25°C, as shown in the following table.
Notes:
–See “ELECTRICAL CHARACTERISTICS” on page 81. for more information on the frequency and accuracy of the RC oscillator.
–To improve clock stability and frequency accuracy, it is recommended to place a decoupling ca-
pacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.
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ST7FLITE09 |
ST7FLITE05/ |
RCCR |
Conditions |
ST7FLITES5 |
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VDD=5V |
1000h and |
FFDEh |
RCCR0 |
TA=25°C |
FFDEh |
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VDD=3.0V |
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TA=25°C |
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–These two bytes are systematically programmed by ST, including on FASTROM devices. Consequently, customers intending to us e FASTROM service must not use these two bytes.
–RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset after it has been set. See “Read out Protection” on page 15.
Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated.
Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal.
The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4
or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits.
–The x4 PLL is intended for operation with VDD in the 2.4V to 3.3V range
–The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range
Refer to Section 15.1 for the option byte description.
If the PLL is disabled and the RC oscillator is enabled, then fOSC = 1MHz.
If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock.
24/124
1
ST7LITE0xY0, ST7LITESxY0
Figure 13. PLL Output Frequency Timing
Diagram
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LOCKED bit set |
4/8 x |
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input |
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freq. |
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tSTAB |
freq. |
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tLOCK |
Output |
tSTARTUP |
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t |
When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of tSTARTUP.
When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after
a stabilization time of tSTAB (see Figure 13 and 13.3.4 Internal RC Oscillator and PLL)
Refer to section 8.4.4 on page 36 for a description of the LOCKED bit in the SICSR register.
MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
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MCO |
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Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock.
0:MCO clock disabled, I/O port free for general purpose I/O.
1:MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32.
0:Normal mode (fCPU = fOSC
1:Slow mode (fCPU = fOSC/32)
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
7 |
0 |
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
Bits 7:0 = CR[7:0] RC Oscillator Frequency Adjustment Bits
These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in EEPROM and write it to this register at start-up.
00h = maximum available frequency FFh = lowest available frequency
Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.
Bits 7:2 = Reserved, must be kept cleared.
Table 5. Clock Register Map and Reset Values
Address |
Register |
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Label |
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SMS |
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RCCR |
CR7 |
CR6 |
CR5 |
CR4 |
CR3 |
CR2 |
CR1 |
CR0 |
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1
ST7LITE0xY0, ST7LITESxY0
SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d)
Figure 14. Clock Management Block Diagram
CR7 |
CR6 CR5 CR4 |
CR3 |
CR2 |
CR1 |
CR0 |
RCCR |
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PLL 1MHz -> 8MHz |
fOSC |
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PLL 1MHz -> 4MHz |
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LITE TIMER COUNTER |
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1
ST7LITE0xY0, ST7LITESxY0
The reset sequence manager includes three RESET sources as shown in Figure 16:
The 256 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.
■External RESET source pulse
■Internal LVD RESET (Low Voltage Detection)
■Internal WATCHDOG RESET
Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 11.2.1 on page 53 for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases as shown in Figure 15:
■Active Phase depending on the RESET source
■256 CPU clock cycle delay
■RESET vector fetch
Figure 16.Reset Block Diagram
The RESET vector fetch phase duration is 2 clock cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of tSTARTUP (see Figure 13).
Figure 15. RESET Sequence Phases
RESET
Active Phase |
INTERNAL RESET |
FETCH |
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ILLEGAL OPCODE RESET 1) |
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Note 1: See “Illegal Opcode Reset” on page 78. for more details on illegal opcode reset conditions.
27/124
1
ST7LITE0xY0, ST7LITESxY0
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 17). This de-
tection is asynchronous and therefore the MCU can enter reset state even in HALT mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency.
Figure 17. RESET Sequences
A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin.
7.4.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■Power-On RESET
■Voltage Drop RESET
The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 17.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 17.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
VDD
VIT+(LVD)
VIT-(LVD)
LVD |
EXTERNAL |
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WATCHDOG |
RESET |
RESET |
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RESET |
RUN |
RUN |
RUN |
RUN |
ACTIVE PHASE |
ACTIVE |
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ACTIVE |
PHASE |
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PHASE |
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th(RSTL)in |
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tw(RSTL)out |
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 TCPU)
VECTOR FETCH
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ST7LITE0xY0, ST7LITESxY0
The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18.
The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
–Normal processing is suspended at the end of the current instruction execution.
–The PC, X, A and CC registers are saved onto the stack.
–The I bit of the CC register is set to prevent additional interrupts.
–The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses).
The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction, the I bit is cleared and the main program resumes.
Priority Management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT” column in the Interrupt Mapping Table).
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It is serviced according to the flowchart in Figure 18.
External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the HALT low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).
An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity.
Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:
–The I bit of the CC register is cleared.
–The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
–Writing “0” to the corresponding bit in the status register or
–Access to the status register while the flag is set followed by a read or write of an associated register.
Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear sequence is executed.
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ST7LITE0xY0, ST7LITESxY0
INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart
FROM RESET
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I BIT SET? |
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INTERRUPT |
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PENDING? |
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FETCH NEXT INSTRUCTION |
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IRET? |
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SET I BIT |
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LOAD PC FROM INTERRUPT VECTOR |
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EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 6. Interrupt Mapping
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Source |
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Register |
Priority |
Exit |
Address |
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N° |
Description |
from |
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Block |
Label |
Order |
Vector |
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HALT |
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RESET |
Reset |
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Highest |
yes |
FFFEh-FFFFh |
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TRAP |
Software Interrupt |
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Priority |
no |
FFFCh-FFFDh |
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0 |
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Not used |
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FFFAh-FFFBh |
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1 |
ei0 |
External Interrupt 0 |
N/A |
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FFF8h-FFF9h |
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2 |
ei1 |
External Interrupt 1 |
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yes |
FFF6h-FFF7h |
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3 |
ei2 |
External Interrupt 2 |
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FFF4h-FFF5h |
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4 |
ei3 |
External Interrupt 3 |
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FFF2h-FFF3h |
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5 |
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Not used |
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FFF0h-FFF1h |
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6 |
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Not used |
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FFEEh-FFEFh |
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7 |
SI |
AVD interrupt |
SICSR |
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no |
FFECh-FFEDh |
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8 |
AT TIMER |
AT TIMER Output Compare Interrupt |
PWM0CSR |
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no |
FFEAh-FFEBh |
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9 |
AT TIMER Overflow Interrupt |
ATCSR |
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yes |
FFE8h-FFE9h |
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10 |
LITE TIMER |
LITE TIMER Input Capture Interrupt |
LTCSR |
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no |
FFE6h-FFE7h |
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11 |
LITE TIMER RTC Interrupt |
LTCSR |
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yes |
FFE4h-FFE5h |
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12 |
SPI |
SPI Peripheral Interrupts |
SPICSR |
Lowest |
yes |
FFE2h-FFE3h |
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13 |
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Not used |
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Priority |
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FFE0h-FFE1h |
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