ST ST7LITE49M User Manual

8-bit MCU with single voltage Flash memory

LQFP32

(7x7mm)

SDIP32

data EEPROM, ADC, 8/12-bit timers, and I²C interface

Features

■ Memories

– 4 Kbytes single voltage extended Flash

(XFlash) Program memory with Read-Out Protection In-circuit programming and in-application programming (ICP and IAP) Endurance: 10k write/erase cycles guaranteed

Data retention: 20 years at 55 °C – 384 bytes RAM – 128 bytes data EEPROM with Read-Out

Protection.

300K write/erase cycles guaranteed,

data retention: 20 years at 55 °C.

■ Clock, reset and supply management

– 3-level low voltage supervisor (LVD) for

main supply and an auxiliary voltage

detector (AVD) for safe power-on/off – Clock sources: Internal trimmable 8 MHz

RC oscillator, auto-wakeup internal low

power - low frequency oscillator,

crystal/ceramic resonator or external clock – Five power saving modes: Halt, Active-halt,

Auto-wakeup from Halt, Wait and Slow

■ I/O Ports

– Up to 24 multifunctional bidirectional I/Os – 8 high sink outputs

Table 1. Device summary

Features ST7LITE49M

ST7LITE49M

■ 5 timers

– Configurable watchdog timer – Dual 8-bit Lite timers with prescaler,

1 real-time base and 1 input capture

– Dual 12-bit Auto-reload timers with 4 PWM

outputs, input capture, output compare, dead-time generation and enhanced onepulse mode functions

■ Communication interface:

– I²C multimaster interface

■ A/D converter: 10 input channels

■ Interrupt management

– 13 interrupt vectors plus TRAP and RESET

■ Instruction set

– 8-bit data manipulation – 63 basic instructions with illegal opcode

detection – 17 main addressing modes – 8 x 8 unsigned multiply instructions

■ Development tools

– Full HW/SW development package – DM (Debug Module)

Program memory 4 Kbytes

RAM (stack) - bytes 384 (128)

Data EEPROM - bytes 128

Operating supply 2.4 to 5.5 V

CPU frequency Up to 8 MHz

Operating temperature -40 to +125 °C

Packages LQFP32, SDIP32

November 2009 Doc ID 13562 Rev 3 1/188

www.st.com

Contents ST7LITE49M

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3.1 In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3.2 In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5.1 Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5.2 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7 Description of Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . 23

5 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3 Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3.1 Read operation (E2LAT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3.2 Write operation (E2LAT=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.4 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4.1 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4.2 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4.3 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.6 Data EEPROM read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.7 EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . . . 27

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6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3.5 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1.2 Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.2 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.3.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.3.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.3.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 39

7.3.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.4.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.5.1 Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 44

7.5.2 RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.5.3 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 45

7.5.4 AVD threshold selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . . 46

7.5.5 Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 47

8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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Contents ST7LITE49M

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.2.2 Interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.5 Description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.5.2 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 53

8.5.3 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 56

9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.4 Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.4.1 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.5 Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.5.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9.5.2 AWUFH control/status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . . 66

9.5.3 AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10.2.4 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.4 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.7 Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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10.7.1 Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.7.2 Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.1.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11.1.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11.1.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.2 Dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

11.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

11.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

11.3 Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

11.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

11.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

11.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

11.4 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

11.4.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

11.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

11.4.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

11.5 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

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11.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.5.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

11.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

11.5.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

12.1.1 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.1.2 Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

12.1.3 Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

12.1.4 Indexed modes (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . 132

12.1.5 Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.1.6 Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

12.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

13.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

13.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 142

13.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 143

13.3.4 Voltage drop between AVD flag setting and LVD reset generation . . . 143

13.3.5 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

13.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

13.4.2 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

13.5 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 150

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13.5.1 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

13.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

13.6.1 Auto-wakeup from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . 152

13.6.2 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 153

13.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

13.8 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 156

13.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 156

13.8.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

13.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 157

13.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

13.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

13.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

13.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 173

14.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

14.1.1 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

14.1.2 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

14.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

14.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

14.3.4 Order codes for development and programming tools . . . . . . . . . . . . . 177

14.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

15 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

15.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Doc ID 13562 Rev 3 7/188

List of tables ST7LITE49M

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4. Interrupt software priority truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 5. Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 6. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 7. CPU clock delay during reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 8. Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 9. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 10. Reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 11. Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 12. AVD threshold selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 13. Clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 14. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 15. Setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 16. Interrupt vector vs. ISPRx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 17. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 18. ST7LITE49M interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 19. Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 20. Enabling/disabling Active-halt and Halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 21. Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 22. AWU register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 23. DR value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 24. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 25. I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 26. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 27. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 28. PA5:0, PB7:0, PC7:4 and PC2:0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 29. PA7:6 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 30. PC3 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 31. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 32. I/O port register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 33. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 34. Watchdog timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 35. Effect of low power modes on autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 36. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 37. Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 38. Register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 39. Effect of low power modes on Lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 40. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 41. Lite timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 42. Effect of low power modes on the I

Table 43. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 44. Configuration of I Table 45. I

Table 46. Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 47. Channel selection using CH[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 48. Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

C register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

C delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

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Table 49. ADC register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 50. Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 51. ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 52. Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 53. Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . 132

Table 54. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 133

Table 55. Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 56. ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 57. Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 58. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 59. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 60. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 61. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 62. Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 63. Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 64. Voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 65. Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 66. Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 67. Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 68. On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 69. I Table 70. SCL frequency (multimaster I

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 71. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 72. External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 73. AWU from Halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 74. Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 75. Typical ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 76. RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 77. Flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 78. Data EEPROM memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 79. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 80. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 81. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 82. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 83. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 84. Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 85. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 86. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 87. ADC accuracy with VDD = 3.3 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 88. ADC accuracy with VDD = 2.7 to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 89. ADC accuracy with VDD = 2.4 to 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 90. Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 91. LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 92. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 93. Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 94. Development tool order codes for the ST7LITE49M family . . . . . . . . . . . . . . . . . . . . . . . 177

Table 95. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 96. 32-pin plastic dual in-line package, shrink 400-mil width,

(mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 97. 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . . . . . . . . 183

Table 98. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 99. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Doc ID 13562 Rev 3 9/188

List of figures ST7LITE49M

List of figures

Figure 1. ST7LITE49M general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. 32-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3. 32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4. ST7LITE49M memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6. EEPROM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7. Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8. Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 9. Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11. Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 13. Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 15. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 16. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 17. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18. Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 19. Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 20. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 21. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 22. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 23. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 24. Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 25. Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 26. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 27. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 28. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 29. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 30. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 31. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 32. AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 33. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 34. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 35. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 36. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 37. Single timer mode (ENCNTR2=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 38. Dual timer mode (ENCNTR2=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 39. PWM polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 40. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 41. PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 42. Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 43. ST7LITE49M block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 44. Block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 45. Block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 46. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 47. Long range input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 48. Long range input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10/188 Doc ID 13562 Rev 3

ST7LITE49M List of figures

Figure 49. Block diagram of One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 50. One-pulse mode and PWM timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 51. Dynamic DCR2/3 update in One-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 52. Force overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 53. Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 54. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 55. I Figure 56. I

C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 57. Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 58. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 59. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 60. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 61. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 62. fCPU maximum operating frequency versus VDD

supply voltage . . . . . . . . . . . . . . . . . . 142

Figure 63. Frequency vs voltage at four different ambient temperatures (RC at 5 V) . . . . . . . . . . . . 145

Figure 64. Frequency vs voltage at four different ambient temperatures (RC at 3.3 V). . . . . . . . . . . 145

Figure 65. Accuracy in % vs voltage at 4 different ambient temperatures (RC at 5 V) . . . . . . . . . . . 146

Figure 66. Accuracy in % vs voltage at 4 different ambient temperatures

(RC at 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 67. Typical IDD in Run mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 68. Typical IDD in WFI vs. fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 69. Typical IDD in slow mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 70. Typical IDD in Slow-wait mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 71. Typical IDD vs. temperature at VDD = 5 V and fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . 149

Figure 72. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 73. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 74. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 75. R Figure 76. I

resistance versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . 159

current versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 77. Typical VOL at VDD = 2.4 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 78. Typical VOL at VDD = 3 V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 79. Typical VOL at VDD = 5 V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 80. Typical VOL at VDD = 2.4 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 81. Typical VOL at VDD = 3 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 82. Typical VOL at VDD = 5 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 83. Typical VOL vs. VDD at I Figure 84. Typical VOL vs. VDD at I Figure 85. Typical VOL vs VDD at I Figure 86. Typical VOL vs VDD at Figure 87. Typical VOL vs VDD at I

= 2 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

= 4 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

= 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

= 8 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

= 12 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 88. Typical VDD-VOH vs. IIO at VDD = 2.4 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 89. Typical VDD-VOH vs. IIO at VDD = 3 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 90. Typical VDD-VOH vs. IIO at VDD = 5 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 91. Typical VDD-VOH vs. IIO at VDD = 2.4 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 92. Typical VDD-VOH vs. IIO at VDD = 3 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 93. Typical VDD-VOH vs. IIO at VDD = 5 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 94. Typical VDD-VOH vs. V

at IIO = 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 95. Typical VDD-VOH vs. VDD at IIO = 4 mA (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 96. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 97. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 98. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 99. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Doc ID 13562 Rev 3 11/188

List of figures ST7LITE49M

Figure 100. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 101. 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 182

Figure 102. 32-pin low profile quad flat package (7x7), package outline . . . . . . . . . . . . . . . . . . . . . . . 183

12/188 Doc ID 13562 Rev 3

ST7LITE49M Description

8-bit core

ALU

ADDRESS AND DATA BUS

OSC1

OSC2

RESET

Port A

Internal clock

Control

RAM

(384 bytes)

PA7:0

(8 bits)

Power

Supply

Flash

(4K bytes)

LVD, AVD

memory

Ext.

1MHz

Int.

RC OSC

8-bit

dual Lite timer

Port B

PB7:0

(8 bits)

I2C

8 MHz

OSC

16MHz

10-bit ADC

12-bit

Auto-reload

CLKIN

/ 2

Watchdog

Debug module

Port C

PC7:0

(8 bits)

Data EEPROM

(128 bytes)

program

/ 2

Int.

32 kHz

dual timer

RC OSC

1 Description

The ST7LITE49M is a member of the ST7 microcontroller family. All ST7 devices are based

on a common industry-standard 8-bit core, featuring an enhanced instruction set.

The ST7LITE49M features Flash memory with byte-by-byte in-circuit programming (ICP)

and in-application programming (IAP) capability.

Under software control, the ST7LITE49M device can be placed in Wait, Slow, or Halt mode,

reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and

flexibility to software developers, enabling the design of highly efficient and compact

application code. In addition to standard 8-bit data management, all ST7 microcontrollers

feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

The ST7LITE49M features an on-chip Debug Module (DM) to support in-circuit debugging

(ICD). For a description of the DM registers, refer to the ST7 ICC protocol reference manual.

Figure 1. ST7LITE49M general block diagram

Doc ID 13562 Rev 3 13/188

Pin description ST7LITE49M

ei1

eix associated external interrupt vector

(HS) 20 mA high sink capability

ATPWM0/PA2(HS)

BREAK/PC7

PA 0( HS )

ATIC/PA1(HS)

ATPWM1/PA3(HS)

I2CCLK/PA7(HS)

RESET

ATPWM3/PA5(HS)

ATPWM2/MCO/PA4(HS)

I 2 CD ATA /PA 6 ( HS )

DDA

PB0/AIN0

PB1/AIN1/CLKIN

OSC1/CLKIN

OSC2

SSA

PB2/AIN2

PB3/AIN3

PC1/AIN9 PC0/AIN8 PB7/AIN7

PB6/AIN6 PB5/AIN5 PB4/AIN4

PC6 PC5 PC4/LTIC PC3/ICCCLK PC2/ICCDATA

ei2

ei0

ei2

Note 1: Available on 8 Kbytes version only

SSA

DDA

AIN0/PB0

CLKIN/AIN1/PB1

AIN2/PB2

OSC1/CLKIN

OSC2

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10111213141516

1 2 3 4 5 6 7 8

PB6/AIN6 PB5/AIN5 PB4/AIN4 PB3/AIN3

PC2/ICCDATA PC1/AIN9 PC0/AIN8 PB7/AIN7

PC6

PC5

PC4/LTIC

PC3/ICCCLK

PA 2( HS )/ ATP W M 0

PA 1( HS )/ ATI C

PA 0( HS )

PC7/BREAK

eix associated external interrupt vector

(HS) 20 mA high sink capability

I2CCLK/PA7(HS)

RESET

ATPWM2/MCO/PA4(HS)

I2CDATA/PA6(HS)

ATPWM3/PA5(HS)

ATPWM1/PA3(HS)

ei0

ei2

ei1

2 Pin description

Figure 2. 32-pin SDIP package pinout

Figure 3. 32-pin LQFP 7x7 package pinout

14/188 Doc ID 13562 Rev 3

ST7LITE49M Pin description

Legend / Abbreviations for Tab le 2 :

Type: I = input, O = output, S = supply

In/Output level: C

= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20 mA high sink (on N-buffer only)

Port and control configuration:

● Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog

● Output: OD = open-drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is valid as long as the device is

in reset state.

Table 2. Device pin description

number

LQFP32

1 5 PA3 ( H S ) / AT P W M 1 I / O CTHS x

SDIP32

AT P WM 2 / MC O

Pin name

PA 4( HS )/

Level Port/control

Type

Input

I/O C

HS x xx

Main

Input Output

Output

float

int

wpu

ana

(1)

ei0

function

(after

reset)

Port A3

(HS)

Port A4

(HS)

Alternate

function

AT PW M1

AT PW M2 /

MCO

3 7 PA5 ( H S ) AT P W M 3 I / O C

PA 6( HS )/ I2CDATA

I/O C

HS x xx

HS x

Port A5

(HS)

Port A6

(HS)

AT PW M3

I2CDATA

ei0

5 9 PA7(HS)/I2CCLK I/O C

HS x T

Port A7

(HS)

I2CCLK

6 10 RESET x x Reset

812 V

913 V

(2)

S Digital supply voltage

S Digital ground voltage

Resonator oscillator

10 14 OSC1/CLKIN I

inverter input or external

clock input

11 15 OSC2 O Resonator oscillator output

12 16 V

13 17 V

SSA

DDA

(2)

S Analog ground voltage

S Analog supply voltage

Doc ID 13562 Rev 3 15/188

Pin description ST7LITE49M

Table 2. Device pin description

number

Pin name

SDIP32

LQFP32

14 18 PB0/AIN0 I/O C

15 19 PB1/AIN1/CLKIN I/O C

16 20 PB2/AIN2 I/O C

17 21 PB3/AIN3 I/O C

18 22 PB4/AIN4 I/O C

19 23 PB5/AIN5 I/O C

20 24 PB6/AIN6 I/O C

21 25 PB7/AIN7 I/O C

22 26 PC0/AIN8 I/O C

23 27 PC1/AIN9 I/O C

24 28 PC2/ICCDATA I/O C

25 29 PC3/ICCCLK I/O C

26 30 PC4/LTIC I/O C

27 31 PC5 I/O C

28 32 PC6 I/O C

29 1 PC7/BREAK I/O C

30 2 PA0 (HS) I/O C

31 3 PA1 (HS)/ATIC I/O C

32 4 PA2 (HS)/ATPWM0 I/O C

1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD are not

implemented).

2. It is mandatory to connect all available V

Level Port/control

Type

Input

Output

HS x

HS x xx

and V

pins to the supply voltage and all VSS and V

DDA

Input Output

wpu

float

x xxx Port B1

x xxx Port B2 AIN2

x xxx Port B3 AIN3

ei1

x xxx Port B4 AIN4

x xxx Port B5 AIN5

x xxx Port B6 AIN6

x xxx Port B7 AIN7

x xxx Port C1 AIN9

ei2

x xxPor t C2 ICCDATA

x x xx Port C3 ICCCLK

x xx Port C5

x xx Port C6

ei2

x xxPor t C7 BREAK

ei0

Main

function

(after

reset)

int

ana

(1)

xxx Port B0 AIN0

xxx Port C0 AIN8

xx Port C4 LTI C

xx Port A0 (HS)

Port A1

(HS)

Port A2

(HS)

pins to ground.

SSA

Alternate

function

AIN1/

External

clock source

AT I C

AT PW M0

16/188 Doc ID 13562 Rev 3

ST7LITE49M Register and memory mapping

0000h

Flash memory

(4K)

Interrupt & reset vectors

HW registers

0080h

007Fh

0FFFh

(seeTa bl e 3)

1000h

107Fh

FFE0h

FFFFh

(see Table 16)

Reserved

Short addressing RAM (zero page)

0080h

00FFh

Data EEPROM

(128 bytes)

F000h

1080h

EFFFh

Reserved

FFDFh

128 bytes Stack

0100h

017Fh

1 Kbytes

3 Kbytes

(SECTOR 1)

(SECTOR 0)

4K Flash

program memory

DEE0h

RCCRH1

RCCRL1

see Section 7.1.1

01FFh 0200h

RAM

(384 bytes)

0180h

01FFh

DEE1h

DEE2h

RCCRH0

RCCRL0

DEE3h

FFFFh

F000h

3 Register and memory mapping

As shown in Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O

registers.

The available memory locations consist of 128 bytes of register locations, 384 bytes of

RAM, 128 bytes of data EEPROM and 4 Kbytes of Flash program memory. The RAM space

includes up to 128 bytes for the stack from 180h to 1FFh.

The highest address bytes contain the user reset and interrupt vectors.

The Flash memory contains two sectors (see Figure 4) mapped in the upper part of the ST7

addressing space so the reset and interrupt vectors are located in Sector 0 (FFE0h-FFFFh).

The size of Flash Sector 0 and other device options are configurable by option bytes (refer

to Section 14.1 on page 173).

Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved

area can have unpredictable effects on the device.

Figure 4. ST7LITE49M memory map

Doc ID 13562 Rev 3 17/188

Table 3. Hardware register map

(1)

Address Block Register label Register name Reset status Remarks

0000h 0001h 0002h

0003h 0004h 0005h

0006h 0007h 0008h

0009h to

000Bh

000Ch 000Dh 000Eh 000Fh

0010h

0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h

0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h 002Ah

002Bh to

002Ch

Por t A

Por t B

Por t C

LITE

TIMER

AUTO-

RELOAD

TIMER

PA DR

PA DD R

PA OR

PBDR

PBDDR

PBOR

PCDR

PCDDR

PCOR

LTCSR2

LTA RR LTCNTR LTCSR1

LT IC R

AT CS R

CNTR1H

CNTR1L

AT R1 H

AT R1 L

PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR

DCR0H

DCR0L

DCR1H

DCR1L

DCR2H

DCR2L

DCR3H

DCR3L

ATICRH

AT IC RL

ATCSR2

BREAKCR

AT R2 H AT R2 L

DTGR

BREAKEN

Port A data register

Port A Data direction register

Port A option register

Port B data register

Port B data direction register

Port B option register

Port C data register

Port C data direction register

Port C option register

Reserved area (3 bytes)

Lite timer control/status register 2

Lite timer auto-reload register

Lite timer counter register

Lite timer control/status register 1

Lite timer input capture register

Timer control/status register

Counter register 1 High

Counter register 1 Low

Auto-reload register 1 High

Auto-reload register 1 Low

PWM output control register PWM 0 control/status register PWM 1 control/status register PWM 2 control/status register PWM 3 control/status register

PWM 0 duty cycle register High

PWM 0 duty cycle register Low

PWM 1 duty cycle register High

PWM 1 duty cycle register Low

PWM 2 duty cycle register High

PWM 2 duty cycle register Low

PWM 3 duty cycle register High

PWM 3 duty cycle register Low

Input capture register High Input capture register Low

Timer control/status register 2

Break control register

Auto-reload register 2 High

Auto-reload register 2 Low

Dead time generation register

Break enable register

Reserved area (2 bytes)

00h 00h 00h

00h 00h 08h

0Fh 00h 00h

0x00 0000b

xxh

0x00 0000b

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h 03h

R/W R/W R/W

R/W R/W

Read Only

R/W

Read Only

R/W Read Only Read Only

R/W

R/W Read Only Read Only

R/W

002Dh 002Eh 002Fh

0030h 0031h

ITC

ISPR0 ISPR1 ISPR2 ISPR3

EICR

Interrupt software priority register 0 Interrupt software priority register 1 Interrupt software priority register 2 Interrupt software priority register 3

External interrupt control register

18/188 Doc ID 13562 Rev 3

FFh FFh FFh FFh 00h

R/W

ST7LITE49M Register and memory mapping

Table 3. Hardware register map

(1)

(continued)

Address Block Register label Register name Reset status Remarks

0032h Reserved area (1 byte)

0033h WDG WDGCR Watchdog control register 7Fh R/W

0034h FLASH FCSR Flash control/status register 00h R/W

0035h EEPROM EECSR Data EEPROM control/status register 00h R/W

0036h 0037h 0038h

ADC

ADCCSR ADCDRH ADCDRL

A/D control status register

A/D data register high

00h xxh 0xh

R/W Read Only

R/W

0039h Reserved area (1 byte)

003Ah MCC MCCSR Main Clock Control/Status register 00h R/W

003Bh 003Ch

Clock and

reset

003Dh AVDTHCR

003Eh to

0047h

0048h 0049h

AWU

004Ah 004Bh 004Ch 004Dh

(2)

004Eh 004Fh

0050h

RCCR

SICSR

AWUCSR

AWUPR

DMCR DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

DMCR2

RC oscillator control register

System integrity control/status register

AVD threshold selection register / RC

prescaler

Reserved area (10 bytes)

AWU control/status register

AWU Preload register

DM control register

DM status register

DM breakpoint register 1 High

DM breakpoint register 1 Low

DM breakpoint register 2 High

DM breakpoint register 2 Low

DM control register 2

FFh

011x 0x00b

00h R/W

FFh 00h

00h 00h 00h 00h 00h 00h 00h

R/W

0051h

0052h to

0063h

0064h 0065h 0066h 0067h 0068h 0069h

006Ah

1. Legend: x=undefined, R/W=read/write.

2. For a description of the debug module registers, see ICC protocol reference manual.

Clock

Controller

I2C

CKCNTCSR Clock controller status register 09h R/W

Reserved area (18 bytes)

I2CCR I2CSR1 I2CSR2

I2CCCR I2COAR1 I2COAR2

I2CDR

C control register

C status register 1

C status register 2

C clock control register

C own address register 1

I I2C own address register 2

I2C data register

Doc ID 13562 Rev 3 19/188

00h 00h 00h 00h 00h 40h 00h

R/W Read only Read only

R/W

Flash programmable memory ST7LITE49M

4 Flash programmable memory

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using in-circuit programming or in-application programming.

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main features

● ICP (in-circuit programming)

● IAP (in-application programming)

● ICt (in-circuit testing) for downloading and executing user application test patterns in

RAM

● Sector 0 size configurable by option byte

● Read-out and write protection

4.3 Programming modes

The ST7 can be programmed in three different ways:

● Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row

and data EEPROM (if present) can be programmed or erased.

● In-circuit programming. In this mode, Flash sectors 0 and 1, option byte row and data

EEPROM (if present) can be programmed or erased without removing the device from the application board.

● In-application programming. In this mode, sector 1 and data EEPROM (if present) can

be programmed or erased without removing the device from the application board and while the application is running.

4.3.1 In-circuit programming (ICP)

ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET ST7 enters ICC mode, it fetches a specific reset vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

● Download ICP Driver code in RAM from the ICCDATA pin

● Execute ICP Driver code in RAM to program the Flash memory

pin is pulled low. When the

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ST7LITE49M Flash programmable memory

Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In-application programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is Write/Erase protected to allow recovery in case errors occur during the programming operation.

4.4 ICC interface

ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:

● RESET: device reset

● V

● ICCCLK: ICC output serial clock pin

● ICCDATA: ICC input serial data pin

● OSC1: main clock input for external source

● V

Note: 1 If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal

isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2 During the ICP session, the programming tool must control the RESET

conflicts between the programming tool and the application reset circuit if it drives more than 5 mA at high level (push pull output or pull-up resistor<1 k to isolate the application RESET circuit in this case. When using a classical RC network with R>1 k additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3 The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This

pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4 In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a

clock source, regardless of the selection in the option byte. In “disabled option byte” mode (35-pulse ICC mode), pin 9 has to be connected to the PB1/CLKIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte.

: device power supply ground

: application board power supply (optional, see Note 3)

pin. This can lead to

.). A schottky diode can be used

or a reset management IC with open-drain output and pull-up resistor>1 kΩ, no

Caution: During normal operation the ICCCLK pin must be internally or externally pulled- up (external

pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly

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Flash programmable memory ST7LITE49M

PROGRAMMING TOOL

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

VDD

HE10 CONNECTOR TYPE

APPLICATION POWER SUPPLY

246810

97 5 3

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

ST7

PB1/CLKIN

OPTIONAL

See Note 1

See Note 1 and Caution

See Note 2

APPLICATION RESET SOURCE

APPLICATION

I/O

(See Note 4)

during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.

Figure 5. Typical ICC interface

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ST7LITE49M Flash programmable memory

4.5 Memory protection

There are two different types of memory protection: Read-out protection and Write/Erase Protection which can be applied individually.

4.5.1 Read-out protection

Read-out protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data EEPROM memory are protected.

In Flash devices, this protection is removed by reprogramming the option. In this case, both program and data EEPROM memory are automatically erased and the device can be reprogrammed.

Read-Out Protection selection depends on the device type:

● In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

● In ROM devices it is enabled by mask option specified in the option list.

4.5.2 Flash write/erase protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to EEPROM data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Write/erase protection is enabled through the FMP_W bit in the option byte.

Caution: Once set, write/erase protection can never be removed. A write-protected Flash

device is no longer reprogrammable.

4.6 Related documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash programming reference manual and to the ST7 ICC protocol reference manual

4.7 Description of Flash control/status register (FCSR)

This register controls the XFlash erasing and programming using ICP, IAP or other programming methods.

1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

Reset value: 000 0000 (00h)

7 0

00000OPTLATPGM

Read/write

Doc ID 13562 Rev 3 23/188

Data EEPROM ST7LITE49M

DATA

MULTIPLEXER

EECSR

HIGH VOLTAGE

PUMP

0 E2LAT00 0 0 0 E2PGM

EEPROM

MEMORY MATRIX

(1 ROW = 32 x 8 BITS)

ADDRESS

DECODER

32 x 8 BITS

DATA LATCHES

ROW

DECODER

DATA BUS

128128

ADDRESS BUS

5 Data EEPROM

5.1 Introduction

The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter.

5.2 Main features

● Up to 32 bytes programmed in the same cycle

● EEPROM mono-voltage (charge pump)

● Chained erase and programming cycles

● Internal control of the global programming cycle duration

● Wait mode management

● Read-out protection

Figure 6. EEPROM block diagram

24/188 Doc ID 13562 Rev 3

ST7LITE49M Data EEPROM

READ MODE

E2LAT=0

E2PGM=0

WRITE MODE

E2LAT=1

E2PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 32 BYTES

IN EEPROM AREA

(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

E2LAT=1

E2PGM=1 (set by software)

E2LAT

CLEARED BY HARDWARE

5.3 Memory access

The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory access modes.

5.3.1 Read operation (E2LAT=0)

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared.

On this device, data EEPROM can also be used to execute machine code. Take care not to write to the data EEPROM while executing from it. This would result in an unexpected code being executed.

5.3.2 Write operation (E2LAT=1)

To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 32 data latches according to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to

32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.

Note: Care should be taken during the programming cycle. Writing to the same memory location

will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data (see Figure 9).

Figure 7. Data EEPROM programming flowchart

Doc ID 13562 Rev 3 25/188

Data EEPROM ST7LITE49M

Byte 1 Byte 2 Byte 32

PHASE 1

Programming cycle

Read operation impossible

PHASE 2

Read operation possible

E2LAT bit

E2PGM bit

Writing data latches Waiting E2PGM and E2LAT to fall

Set by USER application

Cleared by hardware

⇓ Row / byte ⇒ 0123 ... 30 31 Physical Address

0 00h...1Fh

1 20h...3Fh

...

N Nx20h...Nx20h+1Fh

ROW

DEFINITION

Figure 8. Data EEPROM write operation

1. If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed.

5.4 Power saving modes

5.4.1 Wait mode

The data EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-halt mode.The data EEPROM will immediately enter this mode if there is no programming in progress, otherwise the data EEPROM will finish the cycle and then enter Wait mode.

5.4.2 Active-halt mode

Refer to Wait mode.

5.4.3 Halt mode

The data EEPROM immediately enters Halt mode if the microcontroller executes the Halt instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.

5.5 Access error handling

If a read access occurs while E2LAT=1, then the data bus will not be driven.

If a write access occurs while E2LAT=0, then the data on the bus will not be latched.

If a programming cycle is interrupted (by a RESET action), the integrity of the data in memory will not be guaranteed.

26/188 Doc ID 13562 Rev 3

ST7LITE49M Data EEPROM

LAT

ERASE CYCLE

WRITE CYCLE

PGM

PROG

READ OPERATION NOT POSSIBLE

WRITE OF

DATA LATCHES

READ OPERATION POSSIBLE

Internal Programming

voltage

5.6 Data EEPROM read-out protection

The read-out protection is enabled through an option bit (see Section 14.1: Option bytes). When this option is selected, the programs and data stored in the EEPROM memory are protected against Read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the option byte, the entire Program memory and EEPROM is first automatically erased.

Note: Both program memory and data EEPROM are protected using the same option bit.

Figure 9. Data EEPROM programming cycle

5.7 EEPROM control/status register (EECSR)

Address: 0035h

Reset value: 0000 0000 (00h)

7 0

000000E2LATE2PGM

Read/write

Bits 7:2 = Reserved, forced by hardware to 0

0: Read mode 1: Write mode

Bit 1 = E2LAT Latch access transfer bit: this bit is set by software.

It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared

Bit 0 = E2PGM Programming control and status bit

This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware.

0: Programming finished or not yet started 1: Programming cycle is in progress

Note: If the E2PGM bit is cleared during the programming cycle, the memory data is not

guaranteed.

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Central processing unit ST7LITE49M

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C1 1 HI NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

X = Undefined Value

6 Central processing unit

6.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.

6.2 Main features

● 63 basic instructions

● Fast 8-bit by 8-bit multiply

● 17 main addressing modes

● Two 8-bit index registers

● 16-bit stack pointer

● Low power modes

● Maskable hardware interrupts

● Non-maskable software interrupt

6.3 CPU registers

The six CPU registers shown in Figure 10. They are not present in the memory mapping and are accessed by specific instructions.

Figure 10. CPU registers

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ST7LITE49M Central processing unit

6.3.1 Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

6.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

6.3.3 Program counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is the LSB) and PCH (program counter high which is the MSB).

6.3.4 Condition code register (CC)

The 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

Reset value: 111x 1xxx

7 0

11I1HI0NZC

Read/write

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic management bits

Bit 4 = H Half carry bit

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Doc ID 13562 Rev 3 29/188

Central processing unit ST7LITE49M

Bit 3 = I Interrupt mask

bit

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM

and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By

default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative bit

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7

bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic

1). This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero bit

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow

bit

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC

instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt management bits

Bits 5,3 = I1, I0 Interrupt bits

The combination of the I1 and I0 bits gives the current interrupt software priority. These two bits are set/cleared by hardware when entering in interrupt. The loaded

value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See Section 10.6: Interrupts for more details.

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