ST ST7LITE49K2 User Manual

8-bit MCU with single voltage Flash memory,

LQFP32

7 x 7

PDIP32S

data EEPROM, ADC, 8/12/16-bit timers, SPI and I²C interface

Features

■ Memories

– 8 Kbytes single voltage extended Flash

(XFlash) program memory with Read-out protection In-circuit programming and in-application programming (ICP and IAP) Endurance: 10K write/erase cycles guaranteed

Data retention: 20 years at 55 °C – 384 bytes RAM – 256 bytes data EEPROM with Read-Out

Protection.

300K write/erase cycles guaranteed,

data retention: 20 years at 55 °C.

■ Clock, Reset and Supply Management

– Low voltage supervisor (LVD) for safe

power-on/off – Clock sources: Internal trimmable 8 MHz

RC oscillator, auto-wakeup internal low

power - low frequency oscillator,

crystal/ceramic resonator or external clock – Five power saving modes: Halt, Active-halt,

Auto-wakeup from Halt, Wait and Slow – Internal 32-MHz input clock for Autoreload

timer

■ I/O Ports

– Up to 24 multifunctional bidirectional I/Os – 8 high sink outputs

■ 6 timers

– Configurable watchdog timer – Dual 8-bit Lite timers with prescaler,

1 real time base and 1 input capture – Dual 12-bit Autoreload timers with 4 PWM

outputs, input capture, output compare,

dead-time generation and enhanced one

pulse mode functions

ST7LITE49K2

■ Communication interfaces:

– I²C multimaster interface – SPI synchronous serial interface

■ 2 analog comparators

– Internal voltage reference module

■ A/D Converter

– 10 input channels – Fixed gain Op-amp

■ Interrupt management

– 13 interrupt vectors plus TRAP and RESET

■ Instruction set

– 8-bit data manipulation – 63 basic instructions with illegal opcode

detection – 17 main addressing modes – 8 x 8 unsigned multiply instructions

■ Development tools

– Full HW/SW development package – DM (Debug module)

February 2009 Rev 4 1/245

www.st.com

Contents ST7LITE49K2

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3.1 In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3.2 In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.5.1 Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.5.2 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.7 Description of Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . 28

5 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.1 Read operation (E2LAT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.2 Write operation (E2LAT=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.1 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.2 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.3 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.6 Data EEPROM read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.7 EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . . . 32

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6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3.5 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1 RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.1.2 Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.2 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.3 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.3.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.3.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 45

7.3.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.4 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.4.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.4.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.4.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.5.1 Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 50

7.5.2 RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.5.3 System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 51

7.5.4 AVD threshold selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . . 52

7.5.5 Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 53

8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.2.2 Interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.5 Description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.5.2 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 59

8.5.3 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 62

9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.4 Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.4.1 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.5 Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

9.5.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.5.2 AWUFH control/status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . . 72

9.5.3 AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.2.4 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.7 Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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10.7.1 Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.7.2 Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.1.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

11.2 Dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

11.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

11.3 Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

11.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

11.4.6 Summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

11.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

11.4.8 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . 137

11.5 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

11.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

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11.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

11.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

11.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

11.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

11.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

11.6 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

11.6.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.6.5 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

11.6.6 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

11.6.7 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

11.6.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

11.6.9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

11.7 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

11.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

11.7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

11.7.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

11.7.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

11.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

11.7.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

11.8 Analog comparator (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

11.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

11.8.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

11.8.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.8.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

12.1.1 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

12.1.2 Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

12.1.3 Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

12.1.4 Indexed modes (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . 185

12.1.5 Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

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12.1.6 Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 186

12.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

12.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

13.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

13.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 195

13.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 196

13.3.4 Voltage drop between AVD flag setting and LVD reset generation . . . 196

13.3.5 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

13.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

13.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

13.4.2 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

13.5 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 203

13.5.1 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

13.5.2 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

13.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

13.6.1 Auto-wakeup from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . 208

13.6.2 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 209

13.6.3 32-MHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

13.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

13.8 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 212

13.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 212

13.8.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

13.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 213

13.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

13.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

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13.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

13.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

13.11.1 Amplifier output offset variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

13.12 Analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 230

14.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

14.1.1 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

14.1.2 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

14.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

14.3 Transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

14.4 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

14.4.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

14.4.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

14.4.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

14.4.4 Order codes for development and programming tools . . . . . . . . . . . . . 236

14.5 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

15 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

15.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

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List of tables

Table 1. ST7LITE49K2 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. ST7LITE49K2 device pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 4. Interrupt software priority truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 5. Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 7. CPU clock delay during Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 8. Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 9. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 10. Reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 11. Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 12. AVD threshold selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 13. Clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 14. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 15. Setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 16. Interrupt vector vs ISPRx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 17. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 18. ST7LITE49K2 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 19. Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 20. Enabling/disabling Active-halt and Halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 21. Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 22. AWU register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 23. DR value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 24. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 25. I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 26. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 27. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 28. PA5:0, PB7:0, PC7:4 and PC2:0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 29. PA7:6 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 30. PC3 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 31. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 32. I/O port register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 33. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 34. Watchdog timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 35. Effect of low power modes on autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 36. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 37. Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 38. Register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 39. Effect of low power modes on Lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 40. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 41. Lite timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 42. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 43. 16-bit timer interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 44. Summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 45. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 46. Effect of low power modes on the I

Table 47. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 48. Configuration of I

C delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

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Table 49. I2C register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 50. Low power mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 51. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 52. SPI Master mode SCK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 53. SPI Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 54. Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 55. Channel selection using CH[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 56. Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 57. ADC register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 58. Comparison result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 59. Voltage reference programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 60. Analog comparator register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 61. Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 62. ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 63. Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 64. Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . 185

Table 65. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 186

Table 66. Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 67. ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 68. Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 69. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 70. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 71. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 72. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 73. Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 74. Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 75. Voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 76. Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 77. Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 78. Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 79. On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 80. I Table 81. SCL frequency (multimaster I

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 82. SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 83. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 84. External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 85. AWU from Halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 86. Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 87. Typical ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 88. 32-MHz PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 89. RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 90. Flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 91. Data EEPROM memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 92. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 93. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 94. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 95. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 96. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 97. Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 98. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 99. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 100. ADC accuracy with VDD = 3.3 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

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Table 101. ADC accuracy with VDD = 2.7 to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 102. ADC accuracy with VDD = 2.4 to 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 103. Amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 104. Offset variation at TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 105. Analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 106. Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 107. LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 108. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 109. Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 110. Development tool order codes for the ST7LITE49K2 family. . . . . . . . . . . . . . . . . . . . . . . 237

Table 111. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 112. 32-pin plastic dual in-line package, shrink 400-mil width, mechanical data . . . . . . . . . . . 241

Table 113. 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . . . . . . . . 242

Table 114. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 115. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

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List of figures ST7LITE49K2

List of figures

Figure 1. ST7LITE49K2 general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. 32-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. 32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4. ST7LITE49K2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 5. Typical ICC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 6. EEPROM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 7. Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 8. Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 9. Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 10. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 11. Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 13. Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 15. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 16. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 17. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 18. Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 19. Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 20. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 21. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 22. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 23. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 24. Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 25. Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 26. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 27. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 28. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 29. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 30. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 31. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 32. AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 33. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 34. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 35. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 36. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 37. Single timer mode (ENCNTR2=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 38. Dual timer mode (ENCNTR2=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 39. PWM polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 40. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 41. PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 42. Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 43. ST7LITE49K2 block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 44. Block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 45. Block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 46. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 47. Long range input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 48. Long range input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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Figure 49. Block diagram of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 50. One pulse mode and PWM timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 51. Dynamic DCR2/3 update in one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 52. Force overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 53. Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 54. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 55. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 56. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 57. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 58. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 59. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 60. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 61. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 62. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 63. Output compare timing diagram, f Figure 64. Output compare timing diagram, f

TIMER=fCPU TIMER=fCPU

/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 65. One pulse mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 66. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 67. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 68. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 69. I Figure 70. I

C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 71. Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 72. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 73. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 74. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 75. Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 76. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 77. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 78. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 164

Figure 79. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 80. ST7LITE49K2 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 81. Analog comparator and internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 82. Analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 83. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 84. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 85. fCPU maximum operating frequency versus VDD

supply voltage . . . . . . . . . . . . . . . . . . 195

Figure 86. Frequency vs voltage at four different ambient temperatures (RC at 5 V) . . . . . . . . . . . . 198

Figure 87. Frequency vs voltage at four different ambient temperatures (RC at 3.3 V). . . . . . . . . . . 199

Figure 88. Accuracy in % vs voltage at 4 different ambient temperatures (RC at 5 V) . . . . . . . . . . . 199

Figure 89. Accuracy in % vs voltage at 4 different ambient temperatures (RC at 3.3V) . . . . . . . . . . 199

Figure 90. Typical IDD in Run vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 91. Typical IDD in WFI vs. fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 92. Typical IDD in Slow mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 93. Typical IDD in Slow-wait mode vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 94. Typical IDD vs. temperature at VDD = 5 V and fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . 202

Figure 95. SPI slave timing diagram with CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 96. SPI slave timing diagram with CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 97. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 98. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 99. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 100. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

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List of figures ST7LITE49K2

Figure 101. Rpu resistance versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . 215

Figure 102. I

current versus voltage at four different temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 103. Typical VOL at VDD = 2.4 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 104. Typical VOL at VDD = 3 V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 105. Typical VOL at VDD = 5 V (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 106. Typical VOL at VDD = 2.4 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 107. Typical VOL at VDD = 3 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 108. Typical VOL at VDD = 5 V (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 109. Typical VOL vs. VDD at I Figure 110. Typical VOL vs. VDD at I Figure 111. Typical VOL vs VDD at I Figure 112. Typical VOL vs VDD at Figure 113. Typical VOL vs VDD at I

= 2 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

= 4 mA (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

= 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

= 8 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

= 12 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 114. Typical VDD-VOH vs. IIO at VDD = 2.4 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 115. Typical VDD-VOH vs. IIO at VDD = 3 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 116. Typical VDD-VOH vs. IIO at VDD = 5 V (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 117. Typical VDD-VOH vs. IIO at VDD = 2.4 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 118. Typical VDD-VOH vs. IIO at VDD = 3 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 119. Typical VDD-VOH vs. IIO at VDD = 5 V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 120. Typical VDD-VOH vs. V

at IIO = 2 mA (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 121. Typical VDD-VOH vs. VDD at IIO = 4 mA (high sink). . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 122. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 123. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 124. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 125. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 126. ST7LITE49K2 ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 127. 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 241

Figure 128. 32-pin low profile quad flat package (7x7), package outline . . . . . . . . . . . . . . . . . . . . . . . 242

14/245

ST7LITE49K2 Description

1 Description

The ST7LITE49K2 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

The ST7LITE49K2 features Flash memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming (IAP) capability.

Under software control, the ST7LITE49K2 device can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

The ST7LITE49K2 features an on-chip Debug Module (DM) to support In-Circuit Debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Table 1. ST7LITE49K2 device summary

Features ST7LITE49K2

Program memory - bytes 8K

RAM (stack) - bytes 384 (128)

Data EEPROM - bytes 256

Operating Supply 2.4 to 5.5 V

CPU Frequency Up to 8 MHz

Operating Temperature -40 to +125 °C

Packages LQFP32, SDIP32

15/245

Description ST7LITE49K2

8-bit core

ALU

ADDRESS AND DATA BUS

RESET

Port A

Control

RAM

(384 Bytes)

PA7:0

(8 bits)

Power supply

Flash

(8 Kbytes)

LVD, AVD

memory

8-bit

Dual Lite Timer

Port B

SPI

PB7:0

(8 bits)

I2C

10-bit ADC

+ OpAmp

12-Bit

Auto-Reload Dual Timer

Watchdog

Debug Module

Programmable

Internal Reference

Comparators

Port C

PC7:0

(8 bits)

program

16-bit Timer

OSC_IN

OSC_OUT

Internal clock

Ext.

1 MHz

Int.

RC OSC

8 MHz

OSC

16 MHz

CLKIN

/ 2

Int.

RC OSC

32 kHz

8 MHz -> 32 MHz

PLL

Data EEPROM

(256 Bytes)

Figure 1. ST7LITE49K2 general block diagram

16/245

ST7LITE49K2 Pin description

ei1

eix associated external interrupt vector

(HS) 20mA high sink capability

ATPWM0/PA2(HS)

COMPOUTA/BREAK1/PC7

PA 0 (H S ) /C O M PI N A -

ATIC/PA1(HS)

ATPWM1/PA3(HS)

I2CCLK/PA7(HS)

RESET

ATPWM3/PA5(HS)

ATPWM2/MCO/PA4(HS)

I 2 CD ATA /PA 6 ( HS )

DDA

PB0/AIN0

PB1/AIN1/CLKIN

OSC1/CLKIN

OSC2

SSA

PB2/AIN2

PB3/AIN3

PC1/AIN9 PC0/AIN8 PB7/AIN7

PB6/AIN6 PB5/AIN5/COMPOUTB PB4/AIN4

PC6/COMPINA+ PC5/COMPINB+/BREAK2 PC4/LTIC/COMPINBPC3/ICCCLK PC2/ICCDATA

ei2

ei0

ei2

Note 1: Available on 8K version only

SSA

DDA

AIN0/PB0

CLKIN/AIN1/PB1

AIN2/PB2

OSC1/CLKIN

OSC2

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10111213141516

1 2 3 4 5 6 7 8

PB6/AIN6/SCK PB5/AIN5/EXTCLK_A/COMPOUTB PB4/AIN4/MISO PB3/AIN3/MOSI

PC2/ICCDATA PC1/AIN9/ICAP2_A PC0/AIN8/ICAP1_A PB7/AIN7/SS

/OCMP2_A

PC6/COMPINA+

PC5/COMPINB+/BREAK2

PC4/LTIC/COMPINB-

PC3/ICCCLK

PA 2( HS ) /AT P W M0

PA 1( HS ) /AT I C

PA0(HS)/OCMP1_A/COMPINA-

PC7/BREAK1

eix associated external interrupt vector

(HS) 20mA high sink capability

I2CCLK/PA7(HS)

RESET

ATPWM2/MCO/PA4(HS)

I2CDATA/PA6(HS)

ATPWM3/PA5(HS)

ATPWM1/PA3(HS)

ei0

ei2

ei1

2 Pin description

Figure 2. 32-pin SDIP package pinout

Figure 3. 32-pin LQFP 7x7 package pinout

17/245

Pin description ST7LITE49K2

Legend / Abbreviations for Tab le 2 :

Type: I = input, O = output, S = supply

In/Output level: C

= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20 mA high sink (on N-buffer only)

Port and control configuration:

● Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog

● Output: OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 2. ST7LITE49K2 device pin description

number

Pin name

SDIP32

LQFP32

1 5 PA 3( H S ) /AT PW M 1 I/ O CTHS x

PA 4( HS ) /

AT PW M2 /M CO

3 7 PA 5 ( H S ) ATP WM 3 I/ O C

PA 6( HS ) /

I2CDATA

5 9 PA7(HS)/I2CCLK I/O C

6 10 RESET x xReset

812 V

913 V

(2)

10 14 OSC1/CLKIN I

11 15 OSC2 O

12 16 V

13 17 V

SSA

DDA

(2)

Level Port/control

Main

Type

I/O C

Input Output

Input

Output

float

int

wpu

ana

(1)

HS x xx

HS x

ei0

function

(after

reset)

Port A3

(HS)

Port A4

(HS)

Port A5

(HS)

Port A6

(HS)

Alternate

function

AT P WM 1

AT PW M2 /M C

AT P WM 3

I2CDATA

ei0

HS x T

Port A7

(HS)

I2CCLK

S Digital Supply Voltage

S Digital Ground Voltage

Resonator oscillator

inverter input or External

clock input

Resonator oscillator

output

S Analog Ground Voltage

S Analog Supply Voltage

18/245

ST7LITE49K2 Pin description

Table 2. ST7LITE49K2 device pin description

number

Pin name

SDIP32

LQFP32

Type

14 18 PB0/AIN0 I/O C

15 19 PB1/AIN1/CLKIN I/O C

16 20 PB2/AIN2 I/O C

17 21 PB3/AIN3/MOSI I/O C

18 22 PB4/AIN4/MISO I/O C

PB5/AIN5/

19 23

EXTCLK_A/

I/O C

COMPOUTB

20 24 PB6/AIN6/SCK I/O C

Level Port/control

Input Output

Input

Output

float

x xxxPort B1

x x x x Port B2 AIN2

x xxxPort B3

x xxxPort B4

int

wpu

ana

x x x Port B0 AIN0

ei1

x xxxPort B5

x xxxPort B6

(1)

function

Main

(after

reset)

Alternate

function

AIN1/

External

clock source

AIN3/SPI

Master

in/Slave out

data

AIN4/SPI

Master

out/Slave in

data

AIN5/Timer A

input clock/

Comparator

output B

AIN6/SPI

serial clock

21 25

22 26

23 27

PB7/AIN7/SS/

OCMP2_A

PC0/AIN8/

ICAP1_A

PC1/AIN9/

ICAP2_A

I/O C

24 28 PC2/ICCDATA I/O C

25 29 PC3/ICCCLK I/O C

AIN7/SPI

slave select

x xxxPort B7

(active low)/

Timer A

Output

Compare 2

AIN8/Timer A

xxxPort C0

Input

Capture 1

ei2

x xxxPort C1

AIN9/Timer A

input capture

x x x Port C2 ICCDATA

x x x x Port C3 ICCCLK

19/245

Pin description ST7LITE49K2

Table 2. ST7LITE49K2 device pin description

number

LQFP32

26 30

27 31

Pin name

SDIP32

PC4/LTIC/

COMPINB-

PC5/COMPINB+/

BREAK2

Type

I/O C

28 32 PC6/COMPINA+ I/O C

29 1

30 2

PC7/BREAK1/

COMPOUTA

PA0 /C O M P IN A-

/OCMP1_A

I/O C

Level Port/control

Input Output

Input

Output

float

int

wpu

ana

ei2

x xxPort C5

ei2

x xxPort C7

ei0

Main

function

(after

(1)

reset)

xxPort C4

xxPort C6

BREAK1/Ana

xxPort A0

Alternate

function

LTIC/Analog

Comparator

External

Reference

Input B

Analog

Comparator

Input B/

External

break 2

Analog

Comparator

Input A

log

Comparator

Output A

Analog

comparator

external

reference

Input A/ Timer A

Output

Compare 1

31 3 PA1(HS)/ATIC I/O C

32 4 PA2(HS)/ATPWM0 I/O C

1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD are not

implemented).0

2. It is mandatory to connect all available V

HS x xx

and V

pins to the supply voltage and all VSS and V

DDA

Por t A1

(HS)

Por t A2

(HS)

SSA

AT P WM 0

pins to ground.

20/245

AT IC

ST7LITE49K2 Register and memory mapping

3 Register and memory mapping

As shown in Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of Flash program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh.

The highest address bytes contain the user reset and interrupt vectors.

The Flash memory contains two sectors (see ) mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (FFE0h-FFFFh).

The size of Flash Sector 0 and other device options are configurable by option bytes (refer to Section 14.1 on page 230).

Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved

area can have unpredictable effects on the device.

Table 3. Hardware register map

Address Block Register label Register name Reset status Remarks

(1)

0000h 0001h 0002h

0003h 0004h 0005h

0006h 0007h 0008h

0009h to

000Bh

000Ch 000Dh 000Eh 000Fh

0010h

Por t A

Por t B

Por t C

LITE

TIMER

PA DR

PA DD R

PA OR

PBDR

PBDDR

PBOR

PCDR

PCDDR

PCOR

LTCSR2

LTA RR LTCNTR LTCSR1

LT IC R

Port A Data register

Port A Data Direction register

Port A Option register

Port B Data register

Port B Data Direction register

Port B Option register

Port C Data register

Port C Data Direction register

Port C Option register

Reserved area (3 bytes)

Lite Timer Control/Status register 2

Lite Timer Auto-reload register

Lite Timer Counter register

Lite Timer Control/Status register 1

Lite Timer Input Capture register

00h 00h 00h

00h 00h 08h

0Fh 00h 00h

0x00 0000b

xxh

R/W R/W R/W

R/W R/W

Read Only

R/W

Read Only

21/245

Table 3. Hardware register map

Address Block Register label Register name Reset status Remarks

0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h

0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h 002Ah

002Bh Reserved area (1 byte)

AUTO-

RELOAD

TIMER

AT CS R

CNTR1H

CNTR1L

AT R1 H AT R1 L

PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR

DCR0H

DCR0L

DCR1H

DCR1L

DCR2H

DCR2L

DCR3H

DCR3L

ATICRH

AT IC R L

ATCSR2

BREAKCR1

AT R2 H AT R2 L

DTGR

BREAKEN

(1)

(continued)

Timer Control/Status register

Counter register 1 High

Counter register 1 Low

Auto-Reload register 1 High

Auto-Reload register 1 Low

PWM Output Control register PWM 0 Control/Status register PWM 1 Control/Status register PWM 2 Control/Status register PWM 3 Control/Status register

PWM 0 Duty Cycle register High

PWM 0 Duty Cycle register Low

PWM 1 Duty Cycle register High

PWM 1 Duty Cycle register Low

PWM 2 Duty Cycle register High

PWM 2 Duty Cycle register Low

PWM 3 Duty Cycle register High

PWM 3 Duty Cycle register Low

Input Capture register High

Input Capture register Low

Timer Control/Status register 2

Break Control register 1

Auto-Reload register 2 High

Auto-Reload register 2 Low

Dead Time Generation register

Break Enable register

0x00 0000b

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h 03h

R/W Read Only Read Only

R/W

R/W Read Only Read Only

R/W

AUTO-

002Ch

002Dh 002Eh 002Fh

0030h 0031h

0032h Reserved area (1 byte)

0033h WDG WDGCR Watchdog Control register 7Fh R/W

0034h FLASH FCSR Flash Control/Status register 00h R/W

0035h EEPROM EECSR Data EEPROM Control/Status register 00h R/W

0036h 0037h 0038h

0039h Reserved area (1 byte)

003Ah MCC MCCSR Main Clock Control/Status register 00h R/W

RELOAD

TIMER

ITC

ADC

BREAKCR2 Break Control register 2 00h R/W

ISPR0 ISPR1 ISPR2 ISPR3

EICR

ADCCSR ADCDRH ADCDRL

Interrupt Software Priority register 0 Interrupt Software Priority register 1 Interrupt Software Priority register 2 Interrupt Software Priority register 3

External Interrupt Control register

A/D Control Status register

A/D Data register High

A/D Amplifier Control/Data Low Register

FFh FFh FFh FFh 00h

00h xxh 0xh

R/W

R/W Read Only

R/W

22/245

ST7LITE49K2 Register and memory mapping

Table 3. Hardware register map

(1)

(continued)

Address Block Register label Register name Reset status Remarks

003Bh 003Ch

Clock and

RCCR

SICSR

RC oscillator Control register

System integrity control/status register

FFh

011x 0x00b

00h

R/W

Reset

003Dh AVDTHCR

003Eh to

0047h

0048h 0049h

004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

0050h

0051h

AWU

(2)

Clock

Controller

AWUCSR

AWUPR

DMCR DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

DMCR2

CKCNTCSR Clock Controller Status register 09h R/W

Comparator

0052h

Voltage

VREFCR

Reference

AVD threshold selection register / RC

prescaler

Reserved area (10 bytes)

AWU Control/Status register

AWU Preload register

DM Control register

DM Status register DM Breakpoint register 1 High DM Breakpoint register 1 Low DM Breakpoint register 2 High DM Breakpoint register 2 Low

DM Control register 2

Internal Voltage Reference Control

03h R/W

FFh 00h

00h 00h 00h 00h 00h 00h 00h

R/W R/W

R/W R/W R/W R/W R/W R/W R/W

00h R/W

0053h 0054h

0055h 0056h 0057h 0058h

0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h 006Ah

0070h

0071h

0072h

Comparator

16-bit Timer

I2C

SPI

CMPACR

CMPBCR

TAC R2 TAC R1

TA CS R

TA IC H R 1

TA I CL R 1

TAOCHR1

TAO CL R1

TACHR

TAC LR

TAACHR

TA AC L R

TA IC H R 2

TA I CL R 2

TAOCHR2

TAO CL R2

I2CCR I2CSR1 I2CSR2

I2CCCR I2COAR1 I2COAR2

I2CDR

SPIDR SPICR SPISR

Comparator A & B and Internal

Reference Control Register

Timer A Control register 2 Timer A Control register 1

Timer A Control/status register

Timer A Input capture 1 high register

Timer A Input capture 1 low register

Timer A Output compare 1 high register

Timer A Output compare 1 low register

Timer A Output counter high register

Timer A Output counter low register

Timer A Alternate counter high register

Timer A Alternate counter low register

Timer A Input capture 2 high register

Timer A Input capture 2 low register

Timer A Output compare 2 high register

Timer A Output compare 2 low register

C Control register

C Status register 1

I I2C Status register 2

I2C Clock Control register

C Own Address register 1

I I2C Own Address register 2

I2C Data register

SPI Data register

SPI Control register

SPI Status register

00h R/W

00h 00h 00h xxh xxh 80h 00h

FFh FCh FFh FCh

xxh

80h

00h

40h

00h

0xh

00h

xxh

R/W

R/W Read Only Read Only Read Only

R/W

R/W Read Only Read Only Read Only Read Only Read Only Read Only

R/W

Read only Read only

R/W

23/245

0000h

Flash Memory

Interrupt & Reset Vectors

(1)

HW registers

(1)

0080h

007Fh

FFE0h

FFFFh

Reserved

Short Addressing RAM (zero page)

0080h

00FFh

E000h

DFFFh

FFDFh

128 bytes Stack

0100h

017Fh

8 Kbytes

DEE0h

RCCRH1

RCCRL1

01FFh

0200h

RAM

(384 bytes)

0180h

01FFh

DEE1h

DEE2h

RCCRH0

RCCRL0

DEE3h

E000h

(8 Kbytes)

Flash program memory

(4 Kbytes)

Sector 0

FFFFh

(4 Kbytes)

Sector 1

EFFFh F000h

1000h

10FFh

Data EEPROM

(256 bytes)

1100h

Reserved

0FFFh

1. Legend: x=undefined, R/W=read/write.

2. For a description of the Debug Module registers, see ICC protocol reference manual.

Figure 4. ST7LITE49K2 memory map

1. Refer to Ta bl e 3 for information on hardware registers mapping, and to Table 16 for interrupt vectors addresses.

2. Refer to Section 7.1.1: Internal RC oscillator for details on internal RC oscillator calibration.

24/245

ST7LITE49K2 Flash programmable memory

4 Flash programmable memory

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main features

● ICP (In-Circuit Programming)

● IAP (In-Application Programming)

● ICT (In-Circuit Testing) for downloading and executing user application test patterns in

RAM

● Sector 0 size configurable by option byte

● Read-out and write protection

4.3 Programming modes

The ST7 can be programmed in three different ways:

● Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row

and data EEPROM (if present) can be programmed or erased.

● In-Circuit Programming. In this mode, Flash sectors 0 and 1, option byte row and data

EEPROM (if present) can be programmed or erased without removing the device from the application board.

● In-Application Programming. In this mode, sector 1 and data EEPROM (if present) can

be programmed or erased without removing the device from the application board and while the application is running.

4.3.1 In-circuit programming (ICP)

ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET ST7 enters ICC mode, it fetches a specific Reset vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

● Download ICP Driver code in RAM from the ICCDATA pin

● Execute ICP Driver code in RAM to program the Flash memory

pin is pulled low. When the

25/245

Flash programmable memory ST7LITE49K2

Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In-application programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is Write/Erase protected to allow recovery in case errors occur during the programming operation.

4.4 ICC interface

ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:

● RESET: device reset

● V

● ICCCLK: ICC output serial clock pin

● ICCDATA: ICC input serial data pin

● OSC1: main clock input for external source

● V

Note: 1 If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal

isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2 During the ICP session, the programming tool must control the RESET

conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1 k to isolate the application RESET circuit in this case. When using a classical RC network with R>1 k additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3 The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This

pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4 In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a

clock source, regardless of the selection in the option byte. In “disabled option byte” mode (35-pulse ICC mode), pin 9 has to be connected to the PB1/CLKIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte.

: device power supply ground

: application board power supply (optional, see Note 3)

pin. This can lead to

). A schottky diode can be used

or a reset management IC with open drain output and pull-up resistor>1 kΩ, no

Caution: During normal operation the ICCCLK pin must be internally or externally pulled- up (external

pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly

26/245

ST7LITE49K2 Flash programmable memory

PROGRAMMING TOOL

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

VDD

HE10 CONNECTOR TYPE

APPLICATION POWER SUPPLY

246810

97 5 3

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

ST7

PB1/CLKIN

OPTIONAL

See Note 1

See Note 1 and Caution

See Note 2

APPLICATION RESET SOURCE

APPLICATION

I/O

(See Note 4)

during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.

Figure 5. Typical ICC Interface

27/245

Flash programmable memory ST7LITE49K2

4.5 Memory protection

There are two different types of memory protection: Read-Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Read-out protection

Read-Out Protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data EEPROM memory are protected.

In Flash devices, this protection is removed by reprogramming the option. In this case, both program and data EEPROM memory are automatically erased and the device can be reprogrammed.

Read-Out Protection selection depends on the device type:

● In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

● In ROM devices it is enabled by mask option specified in the option list.

4.5.2 Flash write/erase protection

Write/Erase Protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to EEPROM data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Write/Erase Protection is enabled through the FMP_W bit in the option byte.

Caution: Once set, Write/Erase Protection can never be removed. A write-protected Flash

device is no longer reprogrammable.

4.6 Related documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual

4.7 Description of Flash control/status register (FCSR)

This register controls the XFlash erasing and programming using ICP, IAP or other programming methods.

1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

Reset value: 000 0000 (00h)

7 0

00000OPTLATPGM

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Read/write

ST7LITE49K2 Data EEPROM

DATA

MULTIPLEXER

EECSR

HIGH VOLTAGE

PUMP

0 E2LAT00 0 0 0 E2PGM

EEPROM

MEMORY MATRIX

(1 ROW = 32 x 8 BITS)

ADDRESS

DECODER

32 x 8 BITS

DATA LATCHES

ROW

DECODER

DATA BUS

128128

ADDRESS BUS

5 Data EEPROM

5.1 Introduction

The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter.

5.2 Main features

● Up to 32 bytes programmed in the same cycle

● EEPROM mono-voltage (charge pump)

● Chained erase and programming cycles

● Internal control of the global programming cycle duration

● Wait mode management

● Read-Out Protection

Figure 6. EEPROM block diagram

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Data EEPROM ST7LITE49K2

READ MODE

E2LAT=0

E2PGM=0

WRITE MODE

E2LAT=1

E2PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 32 BYTES

IN EEPROM AREA

(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

E2LAT=1

E2PGM=1 (set by software)

E2LAT

CLEARED BY HARDWARE

5.3 Memory access

The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory access modes.

5.3.1 Read operation (E2LAT=0)

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared.

On this device, Data EEPROM can also be used to execute machine code. Take care not to write to the Data EEPROM while executing from it. This would result in an unexpected code being executed.

5.3.2 Write operation (E2LAT=1)

To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 32 data latches according to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to

32) are programmed in the EEPROM cells. The effective high address (row) is determined

by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.

Note: Care should be taken during the programming cycle. Writing to the same memory location

will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data (see Figure 9).

Figure 7. Data EEPROM programming flowchart

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