ST ST7LITE30F2, ST7LITE35F2, ST7LITE39F2 User Manual
ST7LITE3xF2
8-bit MCU with single voltage Flash, data EEPROM, ADC, timers,
SPI, LINSCI
Features
■ Memories
– 8 Kbytes program memory: single voltage ex-
tended Flash (XFlash) Program memory with
read-out protection, In-Circuit Programming
and In-Application programming (ICP and
IAP), data retention: 20 years at 55°C.
– 384 bytes RAM
– 256 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
■ Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector
(AVD) with interrupt capability for implement-
ing safe power-down procedures
– Clock sources: Internal RC 1% oscillator,
crystal/ceramic resonator or external clock
– Optional x4 or x8 PLL for 4 or 8 MHz internal
clock
– Five Power Saving Modes: Halt, Active-Halt,
Wait and Slow, Auto Wake Up From Halt
■ I/O Ports
– Up to 15 multifunctional bidirectional I/O lines
–7 high sink outputs
■ 5 Timers
– Configurable Watchdog Timer
– Two 8-bit Lite Timers with prescaler,
1 realtime base and 1 input capture
– Two 12-bit Auto-reload Timers with 4 PWM
outputs, input capture and output compare
functions
DIP20
■ 2 Communication Interfaces
– Master/slave LINSCI™ asynchronous serial
interface
– SPI synchronous serial interface
■ Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 12 external interrupt lines (on 4 vectors)
■ A/D Converter
– 7 input channels
– 10-bit resolution
■ Instruction Set
8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
■ Development Tools
– Full hardware/software development package
– DM (Debug module)
QFN20
™
SO20
Table 1. Device summary
Features ST7LITE30F2 ST7LITE35F2 ST7LITE39F2
Program memory - bytes 8K
RAM (stack) - bytes 384 (128)
Data EEPROM - bytes - - 256
Peripherals Lite Timer, Autoreload Timer, SPI, LINSCI, 10-bit ADC
Operating Supply 2.7V to 5.5V
CPU Frequency
Operating Temperature -40°C to +125°C
Packages SO20 300”, DIP20, QFN20
Up to 8Mhz
(w/ ext OSC up to 16MHz)
Up to 8Mhz (w/ ext OSC up to 16MHz
and int 1MHz RC 1% PLLx8/4MHz)
Rev. 9
November 2007 1/173
1
Table of Contents
ST7LITE3xF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . 90
11.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS . . . . . . . . . . . . 146
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 155
13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
14.2 THERMAL CHARACTERISTICS
160
15 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 163
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.1 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 169
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16.2 LINSCI LIMITATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
To obtain the most recent version of this datasheet,
please check at www.st.com
Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 169.
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1 INTRODUCTION
ST7LITE3xF2
The ST7LITE3 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.
The ST7LITE3 features FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and InApplication Programming (IAP) capability.
Under software control, the ST7LITE3 device can
be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in
idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
Figure 1. General Block Diagram
Int.
1% RC
CLKIN
OSC1
OSC2
V
DD
V
SS
RESET
Ext.
OSC
1MHz
to
16MHz
1MHz
PLL x 8
or PLL X4
/ 2
Internal
CLOCK
LVD
POWER
SUPPLY
CONTROL
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in section 13 on page 131.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
12-Bit
Auto-Reload
TIMER 2
8-Bit
LITE TIMER 2
PORT A
ADDRESS AND DATA BUS
PORT B
Debug Module
ADC
PA7:0
(8 bits)
PB6:0
(7 bits)
8-BIT CORE
ALU
PROGRAM
MEMORY
(8K Bytes)
RAM
(384 Bytes)
SPI
LINSCI
WDG
DATA EEPROM
( 256 Bytes)
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ST7LITE3xF2
2 PIN DESCRIPTION
Figure 2. 20-Pin QFN Package Pinout
RESET
S
S/AIN0/PB0
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
SS
DD
V
V
1
2
ei3
3
4
ei2
5
ei2
6
78 910
OSC1/CLKIN
17181920
ei0
ei1
OSC2
16
PA0 (HS)/LTIC
15
PA1 (HS)/ATIC
PA2 (HS)/ATPWM0
14
PA3 (HS)/ATPWM1
13
12
PA4 (HS)/ATPWM2
11
PA5 (HS)/ATPWM3/ICCDATA
AIN5/PB5
Figure 3. 20-Pin SO and DIP Package Pinout
V
V
RESET
/AIN0/PB0
SS
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
AIN5/PB5
RDI/AIN6/PB6
SS
DD
1
2
3
4
5
6
7
8
9
10
TDO/PA7(HS)
RDI/AIN6/PB6
MCO/ICCCLKBREAK/PA6
ei3
ei0
ei2
ei1
ei2
(HS) 20mA High sink capability
eix associated external interrupt vector
OSC1/CLKIN
20
OSC2
19
PA0 (HS)/LTIC
18
PA1 (HS)/ATIC
17
PA2 (HS)/ATPWM0
16
PA3 (HS)/ATPWM1
15
PA4 (HS)/ATPWM2
14
PA5 (HS)/ATPWM3/ICCDATA
13
PA6/MCO/ICCCLK/BREAK
12
PA7 (HS)/TDO
11
(HS) 20mA high sink capability
eix associated external interrupt vector
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ST7LITE3xF2
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 2:
Type: I = input, O = output, S = supply
In/Output level: C
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output: OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 2. Device Pin Description
Pin Name
QFN20
SO20/DIP20
19 1 V
20 2 V
1 3 RESET
2 4 PB0/AIN0/SS
3 5 PB1/AIN1/SCK I/O C
46
57
68
7 9 PB5/AIN5 I/O C
8 10 PB6/AIN6/RDI I/O C
9 11 PA7/TDO I/O C
1)
SS
DD
PB2/AIN2/
MISO
PB3/AIN3/
MOSI
PB4/AIN4/
CLKIN**
= CMOS 0.3VDD/0.7VDD with input trigger
T
Level Port / Control
Input Output
Type
Input
Output
float
wpu
int
S Ground
1)
I/O C
S Main power supply
T
I/O C
T
X X Top priority non maskable interrupt (active low)
X
ei3
X XXXPort B1
T
I/O C
I/O C
I/O C
T
X XXXPort B2
T
X ei2 X X X Port B3
T
X XXXXPort B4
T
X
T
T
ei2
X XXXPort B6 ADC Analog Input 6 or LINSCI Input
HS X XXXPort A7 LINSCI Output
Main
ana
OD
Function
(after
reset)
PP
Alternate Function
ADC Analog Input 0 or SPI Slave Select
(active low)
XXXPort B0
Caution: No negative current injection
allowed on this pin. For details, refer to
section 13.2.2 on page 132
ADC Analog Input 1 or SPI Serial Clock
Caution: No negative current injection
allowed on this pin. For details, refer to
section 13.2.2 on page 132
ADC Analog Input 2 or SPI Master In/
Slave Out Data
ADC Analog Input 3 or SPI Master Out
/ Slave In Data
ADC Analog Input 4 or External clock
input
XXXPort B5 ADC Analog Input 5
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ST7LITE3xF2
Level Port / Control
Pin Name
QFN20
SO20/DIP20
PA6 /MCO/
10 12
11 13
12 14 PA4/ATPWM2 I/O C
13 15 PA3/ATPWM1 I/O C
14 16 PA2/ATPWM0 I/O C
15 17 PA1/ATIC I/O C
16 18 PA0/LTIC I/O C
17 19 OSC2 O Resonator oscillator inverter output
18 20 OSC1/CLKIN I
ICCCLK/
BREAK
PA5 /ATPWM3/
ICCDATA
Type
Input
I/O C
I/O C
T
T
T
T
T
T
Output
T
HS X XXPort A5
HS X XXPort A4 Auto-Reload Timer PWM2
HS X
HS X XXPort A2 Auto-Reload Timer PWM0
HS X XXPort A1 Auto-Reload Timer Input Capture
HS X XXXPort A0 Lite Timer Input Capture
Input Output
int
wpu
float
X
ei1
ei0
OD
ana
XXPort A6
XXPort A3 Auto-Reload Timer PWM1
Main
Function
(after
reset)
PP
Main Clock Output or In Circuit Communication Clock or External BREAK
Caution: During normal operation this
pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to
avoid entering ICC mode unexpectedly
during a reset. In the application, even
if the pin is configured as output, any reset will put it back in input pull-up.
Auto-Reload Timer PWM3 or In Circuit
Communication Data
Resonator oscillator inverter input or External
clock input
Alternate Function
Notes:
1. It is mandatory to connect all available V
DD
and V
pins to the supply voltage and all VSS and V
DDA
SSA
pins to ground.
2. For input with interrupt possibility “ei
” defines the associated external interrupt vector which can be as-
x
signed to one of the I/O pins using the EISR register. Each interrupt can be either weak pull-up or floating
defined through option register OR.
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3 REGISTER & MEMORY MAP
ST7LITE3xF2
As shown in Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, 384 bytes of RAM, 256
bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space includes up to 128
bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 4. Memory Map
0080h
E000h
FBFFh
FC00h
FFFFh
00FFh
0100h
017Fh
0180h
01FFh
0000h
007Fh
0080h
01FFh
0200h
0FFFh
1000h
10FFh
1100h
DFFFh
E000h
FFDFh
FFE0h
FFFFh
HW Registers
(see Table 3)
RAM
(384 Bytes)
Reserved
Data EEPROM
(256 Bytes)
Reserved
Flash Memory
(8K)
Interrupt & Reset Vectors
(see Table 6)
The Flash memory contains two sectors (see Fig-
ure 4) mapped in the upper part of the ST7 ad-
dressing space so the reset and interrupt vectors
are located in Sector 0 (F000h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by Option byte.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the
device.
Short Addressing
RAM (zero page)
16-bit Addressing
RAM
128 Bytes Stack
8K FLASH
PROGRAM MEMORY
7 Kbytes
SECTOR 1
1 Kbyte
SECTOR 0
DEE0h
DEE1h
DEE2h
DEE3h
DEE4h
see section 7.1 on page 23
and
RCCRH0
RCCRL0
RCCRH1
RCCRL1
Note 1)
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes
containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM
data or Flash space (including the RC calibration values locations) has been erased (after the read out
protection removal), then the RC calibration values can still be obtained through these addresses.
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1
ST7LITE3xF2
Table 3. Hardware Register Map
Address Block
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
Port A
Port B
LITE
TIMER 2
AUTO-
RELOAD
TIMER 3
Register
Label
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
ATCSR
CNTR1H
CNTR1L
ATR1H
ATR1L
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
ATICRL
ATCSR2
BREAKCR
ATR2H
ATR2L
DTGR
Register Name Reset Status Remarks
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Reserved area (2 bytes)
Lite Timer Control/Status Register 2
Lite Timer Auto-reload Register
Lite Timer Counter Register
Lite Timer Control/Status Register 1
Lite Timer Input Capture Register
Timer Control/Status Register
Counter Register 1 High
Counter Register 1 Low
Auto-Reload Register 1 High
Auto-Reload Register 1 Low
PWM Output Control Register
PWM 0 Control/Status Register
PWM 1 Control/Status Register
PWM 2 Control/Status Register
PWM 3 Control/Status Register
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
PWM 1 Duty Cycle Register High
PWM 1 Duty Cycle Register Low
PWM 2 Duty Cycle Register High
PWM 2 Duty Cycle Register Low
PWM 3 Duty Cycle Register High
PWM 3 Duty Cycle Register Low
Input Capture Register High
Input Capture Register Low
Timer Control/Status Register 2
Break Control Register
Auto-Reload Register 2 High
Auto-Reload Register 2 Low
Dead Time Generator Register
1)
FFh
00h
40h
1)
FFh
00h
00h
0Fh
00h
00h
0x00 00x0b
xxh
0x00 0000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
03h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
2)
R/W
R/W
R/W
Read Only
R/W
Read Only
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
0026h to
002Dh
002Eh WDG WDGCR Watchdog Control Register 7Fh R/W
0002Fh FLASH FCSR Flash Control/Status Register 00h R/W
00030h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W
10/173
Reserved area (8 bytes)
1
ST7LITE3xF2
Address Block
0031h
0032h
0033h
0034h
0035h
0036h
0037h ITC EICR External Interrupt Control Register 00h R/W
0038h MCC MCCSR Main Clock Control/Status Register 00h R/W
0039h
003Ah
003Bh Reserved area (1 byte)
003Ch ITC EISR External Interrupt Selection Register 00h R/W
003Dh to
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
SPI
ADC
Clock and
Reset
LINSCI
(LIN Mas-
ter/Slave)
Register
Label
SPIDR
SPICR
SPICSR
ADCCSR
ADCDRH
ADCDRL
RCCR
SICSR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCICR3
SCIERPR
SCIETPR
Register Name Reset Status Remarks
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
A/D Control Status Register
A/D Data Register High
A/D control and Data Register Low
RC oscillator Control Register
System Integrity Control/Status Register
Reserved area (3 bytes)
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Control Register 3
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
xxh
0xh
00h
00h
xxh
x0h
FFh
0110 0xx0b
C0h
xxh
00xx xxxxb
xxh
00h
00h
00h
00h
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0048h Reserved area (1 byte)
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h to
007Fh
AWU
DM
3)
AWUPR
AWUCSR
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
AWU Prescaler Register
AWU Control/Status Register
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
Reserved area (47 bytes)
FFh
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the DM registers, see the ST7 ICC Reference Manual.
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ST7LITE3xF2
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Programming.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
■ ICP (In-Circuit Programming)
■ IAP (In-Application Programming)
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Sector 0 size configurable by option byte
■ Read-out and write protection
4.3 PROGRAMMING MODES
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and
data EEPROM (if present) can be programmed or erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or
erased without removing the device from the
application board.
– In-Application Programming. In this mode,
sector 1 and data EEPROM (if present) can
be programmed or erased without removing
the device from the application board and
while the application is running.
4.3.1 In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable.
ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory containing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
– Download ICP Driver code in RAM from the
ICCDATA pin
– Execute ICP Driver code in RAM to program
the FLASH memory
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during
the programming operation.
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1
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC INTERFACE
ST7LITE3xF2
ICP needs a minimum of 4 and up to 6 pins to be
connected to the programming tool. These pins
are:
– RESET
–V
: device reset
: device power supply ground
SS
Figure 5. Typical ICC Interface
APPLICATION
POWER SUPPLY
(See Note 3)
DD
V
OPTIONAL
(See Note 4)
CLKIN/PB4
(See Note 5)
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented if another device
forces the signal. Refer to the Programming Tool
documentation for recommended resistor values.
2. During the ICP session, the programming tool
must control the RESET
pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the application RESET circuit in this case. When using a
classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– CLKIN/PB4: main clock input for external
source
: application board power supply (option-
–V
DD
al, see Note 3)
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
975 3
RESET
ICCCLK
1
246810
See Note 1 and caution
ICCDATA
APPLICATION BOARD
APPLICATION
RESET SOURCE
See Note 2
APPLICATION
See Note 1
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 must be connected to the PB4 pin of the
ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with
multi-oscillator capability must have OSC2
grounded in this case.
5. With any programming tool, while the ICP option
is disabled, the external clock must be provided on
PB4.
6. In 38-pulse ICC mode, the internal RC oscillator
is forced as a clock source, regardless of the selection in the option byte. For ST7LITE30 devices
which do not support the internal RC oscillator, the
“option byte disabled” mode must be used (35pulse ICC mode entry, clock provided by the tool).
Caution: During normal operation ICCCLK pin
must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This avoids entering ICC mode
unexpectedly during a reset. In the application,
even if the pin is configured as output, any reset
puts it back in input pull-up.
I/O
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ST7LITE3xF2
FLASH PROGRAM MEMORY (Cont’d)
4.5 Memory Protection
There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.
4.5.1 Read out Protection
Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory.
Even if no protection can be considered as totally
unbreakable, the feature provides a very high level
of protection for a general purpose microcontroller.
Both program and data E
2
memory are protected.
In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E
2
memory are automatically
erased and the device can be reprogrammed.
– Read-out protection selection is enabled and re-
moved through the FMP_R bit in the option byte.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E
2
data. Its purpose is to
provide advanced security to applications and prevent any change being made to the memory content.
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
Write/erase protection is enabled through the
FMP_W bit in the option byte.
4.6 Related Documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual
.
4.7 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
70
00000OPTLATPGM
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing operations.
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
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1
5 DATA EEPROM
ST7LITE3xF2
5.1 INTRODUCTION
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
Figure 6. EEPROM Block Diagram
EECSR
ADDRESS
DECODER
0 E2LAT00 0 0 0 E2PGM
4
DECODER
ROW
5.2 MAIN FEATURES
■ Up to 32 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Readout protection
HIGH VOLTAGE
PUMP
EEPROM
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
ADDRESS BUS
128128
4
4
DATA
MULTIPLEXER
DATA BUS
32 x 8 BITS
DATA LATCHES
15/173
1
ST7LITE3xF2
DATA EEPROM (Cont’d)
5.3 MEMORY ACCESS
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory
access modes.
Read Operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is
cleared.
On this device, Data EEPROM can also be used to
execute machine code. Take care not to write to
the Data EEPROM while executing from it. This
would result in an unexpected code being executed.
Write Operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
Figure 7. Data EEPROM Programming Flowchart
READ MODE
E2LAT=0
E2PGM=0
the value is latched inside the 32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the five Least
Significant Bits of the address can change.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously.
Note: Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
WRITE MODE
E2LAT=1
E2PGM=0
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1
READ BYTES
IN EEPROM AREA
CLEARED BY HARDWARE
WRITE UP TO 32 BYTES
(with the same 11 MSB of the address)
IN EEPROM AREA
START PROGRAMMING CYCLE
E2PGM=1 (set by software)
E2LAT=1
01
E2LAT
DATA EEPROM (Cont’d)
2
Figure 8. Data E
DEFINITION
PROM Write Operation
⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical Address
ROW
ST7LITE3xF2
0
1
...
N
00h...1Fh
20h...3Fh
Nx20h...Nx20h+1Fh
E2LAT bit
E2PGM bit
Read operation impossible
Byte 1 Byte 2 Byte 32
PHASE 1
Writing data latches Waiting E2PGM and E2LAT to fall
Set by USER application
Programming cycle
PHASE 2
Read operation possible
Cleared by hardware
Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not
guaranteed.
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1
ST7LITE3xF2
DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES
Wait mode
The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-HALT
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
Active-Halt mode
Refer to Wait mode.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by RESET
action), the integrity of the data in memory is not
guaranteed.
5.6 Data EEPROM Read-out Protection
The read-out protection is enabled through an option bit (see section 15.1 on page 161).
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out (including a re-write protection).
In Flash devices, when this protection is removed
by reprogramming the Option Byte, the entire Program memory and EEPROM is first automatically
erased.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE WRITE CYCLE
WRITE OF
DATA LATCHES
t
PROG
READ OPERATION POSSIBLE
LAT
PGM
18/173
1
DATA EEPROM (Cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EECSR)
Read/Write
Reset Value: 0000 0000 (00h)
70
000000E2LATE2PGM
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
ST7LITE3xF2
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed
Table 4. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
0030h
Register
Label
EECSR
Reset Value
76543210
000000
E2LAT0E2PGM
0
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1
ST7LITE3xF2
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
6.2 MAIN FEATURES
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
6.3 CPU REGISTERS
The six CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 10. CPU Registers
70
RESET VALUE = XXh
70
RESET VALUE = XXh
70
RESET VALUE = XXh
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
15 8
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
15
RESET VALUE = STACK HIGHER ADDRESS
20/173
PCH
RESET VALUE =
7
70
1C11HI NZ
1X11X1XX
70
8
PCL
1
0
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
X = Undefined Value
CPU REGISTERS (cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
70
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
111HINZC
tions.
ST7LITE3xF2
th
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptible
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N Negative
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
CPU REGISTERS (Cont’d)
STACK POINTER (SP)
Read/Write
Reset Value: 01FFh
15 8
00000001
70
1 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an
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ST7LITE3xF2
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
Figure 11. Stack Manipulation Example
@ 0180h
CALL
Subroutine
Interrupt
Event
PUSH Y POP Y IRET
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
RET
or RSP
SP
@ 01FFh
SP
CC
A
X
PCH
PCL
PCH
PCL
Stack Higher Address = 01FFh
Stack Lower Address =
PCH
PCL
0180h
SP
Y
CC
A
X
PCH
PCL
PCH
PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
SP
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7 SUPPLY, RESET AND CLOCK MANAGEMENT
ST7LITE3xF2
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components.
Main features
■ Clock Management
– 1 MHz internal RC oscillator (enabled by op-
tion byte, available on ST7LITE35 and
ST7LITE39 devices only)
– 1 to 16 MHz or 32kHz External crystal/ceramic
resonator (selected by option byte)
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 8 or 4
(enabled by option byte)
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The device contains an internal RC oscillator with
an accuracy of 1% for a given device, temperature
and voltage range (4.5V-5.5V). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 8-bit calibration value in the RCCR (RC Control Register)
and in the bits [6:5] in the SICSR (SI Control Status Register).
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), i.e. each time the
device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are
stored in EEPROM for 3V and 5V V
ages at 25°C, as shown in the following table.
RCCR Conditions
T
f
T
f
DD
A
RC
DD
A
RC
=5V
=25°C
=1MHz
=3.3V
=25°C
=1MHz
RCCRH0 V
RCCRL0 DEE1h
RCCRH1 V
RCCRL1 DEE3h
DEE0h
DEE2h
supply volt-
DD
ST7LITE3
Addresses
1)
(CR[9:2] bits)
1)
(CR[1:0] bits)
1)
(CR[9:2] bits)
1)
(CR[1:0] bits)
1. DEE0h, DEE1h, DEE2h and DEE3h addresses
are located in a reserved area of non-volatile
memory. They are read-only bytes for the applica-
tion code. This area cannot be erased or programmed by any ICC operation.
For compatibility reasons with the SICSR register,
CR[1:0] bits are stored in the 5th and 6th position
of DEE1 and DEE3 addresses.
Note:
– In 38-pulse ICC mode, the internal RC oscillator
is forced as a clock source, regardless of the selection in the option byte. For ST7LITE30 devices which do not support the internal RC
oscillator, the “option byte disabled” mode must
be used (35-pulse ICC mode entry, clock provided by the tool).
– See “ELECTRICAL CHARACTERISTICS” on
page 131. for more information on the frequency
and accuracy of the RC oscillator.
– To improve clock stability and frequency accura-
cy, it is recommended to place a decoupling capacitor, typically 100nF, between the V
pins as close as possible to the ST7 device
V
SS
DD
and
– These bytes are systematically programmed by
ST, including on FASTROM devices. Consequently, customers intending to use FASTROM
service must not use these bytes.
– RCCR0 and RCCR1 calibration values will not
be erased if the read-out protection bit is reset after it has been set . See “Read out Protection” on
page 14.
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an external reference signal.
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4
or 8 to obtain f
of 4 or 8 MHz. The PLL is ena-
OSC
bled and the multiplication factor of 4 or 8 is selected by 2 option bits.
– The x4 PLL is intended for operation with V
DD
in
the 2.7V to 3.3V range
– The x8 PLL is intended for operation with V
DD
in
the 3.3V to 5.5V range
Refer to Section 15.1 for the option byte description.
If the PLL is disabled and the RC oscillator is enabled, then f
OSC =
1MHz.
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ST7LITE3xF2
If both the RC oscillator and the PLL are disabled,
is driven by the external clock.
f
OSC
Figure 12. PLL Output Frequency Timing
Diagram
LOCKED bit set
4/8 x
input
freq.
t
STAB
t
LOCK
t
STARTUP
Output freq.
t
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
STARTUP
.
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC
a stabilization time of t
STAB
) is reached after
PLL
(see Figure 12 and
13.3.4Internal RC Oscillator and PLL)
Refer to section 7.6.4 on page 34 for a description
of the LOCKED bit in the SICSR register.
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
70
000000
MCO SMS
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
OSC
or f
clock f
0: Normal mode (f
1: Slow mode (f
/32.
OSC
CPU = fOSC
CPU = fOSC
/32)
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
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1
70
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2
Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-
justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the
SICSR register. Refer to section 7.6.4 on page 34
Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.
Figure 13. Clock Management Block Diagram
ST7LITE3xF2
CLKIN
CLKIN/
OSC1
OSC2
OSCRANGE[2:0]
CLKIN
f
CLKIN
CLKIN
1-16 MHZ
or 32kHz
f
OSC
Tunable
Oscillator1% RC
Option bits
DIVIDER
OSC
/32 DIVIDER
/32 DIVIDER
CR6CR9 CR2CR3CR4CR5CR8 CR7
CR1 CR0
1MHz
/2
DIVIDER
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz
OSC Option bit
/2
8-BIT
LITE TIMER 2 COUNTER
f
/32
OSC
f
OSC
1
0
RCCR
Crystal OSC /2
SICSR
CLKIN/2 (Ext Clock)
RC OSC
8MHz
4MHz
PLL
Clock
PLLx4x8
OSC,PLLOFF,
OSCRANGE[2:0]
Option bits
f
LTIMER
(1ms timebase @ 8 MHz f
f
CPU
TO CPU AND
PERIPHERALS
OSC
f
OSC
)
MCO
SMS
MCCSR
f
CPU
MCO
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7.4 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
four different source types coming from the multioscillator block (1 to 16MHz or 32kHz):
■ an external source
■ 5 crystal or ceramic resonator oscillators
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 5. Refer to the
electrical characteristics section for more details.
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Note: when the Multi-Oscillator is not used, PB4 is
selected by default as external clock.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to section 15.1 on page 161 for more details on the
frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have
to be placed as close as possible to the oscillator
pins in order to minimize output distortion and
start-up stabilization time. The loading capacitance values must be adjusted according to the
selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
In this mode, the tunable 1%RC oscillator is used
as main clock source. The two oscillator pins have
to be tied to ground.
The calibration is done through the RCCR[7:0] and
SICSR[6:5] registers.
Table 5. ST7 Clock Sources
Hardware Configuration
ST7
OSC1 OSC2
External ClockCrystal/Ceramic ResonatorsInternal RC Oscillator
EXTERNAL
SOURCE
OSC1 OSC2
C
L1
CAPACITORS
OSC1 OSC2
ST7
LOAD
ST7
C
L2
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7.5 RESET SEQUENCE MANAGER (RSM)
ST7LITE3xF2
7.5.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 15:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 128 for further details.
These sources act on the RESET
pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (see table
below)
■ RESET vector fetch
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recommended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte:
The RESET vector fetch phase duration is 2 clock
cycles.
Clock Source
Internal RC Oscillator 256
External clock (connected to CLKIN pin) 256
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
CPU clock
cycle delay
4096
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
STARTUP
(see
Figure 12).
Figure 14. RESET Sequence Phases
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
7.5.2 Asynchronous External RESET
The RESET
output with integrated R
pin is both an input and an open-drain
weak pull-up resistor.
ON
FETCH
VECTOR
pin
This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized (see Figure 16). This detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
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ST7LITE3xF2
Figure 15. Reset Block Diagram
V
DD
R
ON
RESET
Filter
PULSE
GENERATOR
WATCHDOG RESET
ILLEGAL OPCODE RESET
LVD RESET
INTERNAL
RESET
Note 1: See “Illegal Opcode Reset” on page 128. for more details on illegal opcode reset conditions.
1)
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1
RESET SEQUENCE MANAGER (Cont’d)
The RESET
pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
7.5.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f
A proper reset signal for a slow rising V
is over the minimum
DD
frequency.
OSC
supply
DD
can generally be provided by an external RC network connected to the RESET
pin.
Figure 16. RESET Sequences
V
DD
ST7LITE3xF2
7.5.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET
pulled low when V
V
DD<VIT-
(falling edge) as shown in Figure 16.
The LVD filters spikes on V
avoid parasitic resets.
7.5.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
Starting from the Watchdog counter underflow, the
device RESET
low during at least t
pin acts as an output that is
DD<VIT+
(rising edge) or
larger than t
DD
g(VDD)
to
pin acts as an output that is pulled
w(RSTL)out
.
V
IT+(LVD)
V
IT-(LVD)
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
RUN
LVD
RESET
ACTIVE PHASE
RUN
t
h(RSTL)in
EXTERNAL
RESET
ACTIVE
PHASE
WATCHDOG UNDERFLOW
RUN RUN
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
WATCHDOG
RESET
ACTIVE
PHASE
t
w(RSTL)out
CPU
)
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ST7LITE3xF2
7.6 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by
the SICSR register.
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 128 for further details.
7.6.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the V
below a V
IT-(LVD)
reference value. This means that
supply voltage is
DD
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The V
IT-(LVD)
lower than the V
reference value for a voltage drop is
IT+(LVD)
reference value for poweron in order to avoid a parasitic reset when the
MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
is below:
V
DD
–V
–V
IT+(LVD)
IT-(LVD)
when VDD is rising
when VDD is falling
The LVD function is illustrated in Figure 17.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum V
the oscillator frequency) is above V
value (guaranteed for
DD
IT-(LVD)
, the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
Use of LVD with capacitive power supply: with this
type of power supply, if power cuts occur in the application, it is recommended to pull V
down to
DD
0V to ensure optimum restart conditions. Refer to
circuit example in Figure 99 on page 154 and note
4.
The LVD is an optional function which can be se-
lected by option byte.
It is recommended to make sure that the V
DD
supply voltage rises monotonously when the device is
exiting from Reset, to ensure the application functions properly.
Figure 17. Low Voltage Detector vs Reset
V
DD
V
IT+
(LVD)
V
IT-
(LVD)
RESET
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V
hys
1
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